1. In the XC4000-derived architectures, the LUT RAM and the
FFs-or-latches have independent clock inversions, so within a single CLB
you can write into the RAMs on the clock rising edge and capture or latch
the RAM outputs on the falling edge. No such luck in Virtex-derived
architectures including Spartan-II. There, there is only a common
clock inversion for both LUT RAM and FFs, and if you write into the RAMs
on a rising edge, you can only clock the FFs on the rising edge, and (as
far as latches) they close on the rising edge too. So you can't clock
the FFs/latches on the other edge as with xr16 on XC4000. If you
want to, you have to put the FFs/latches in another column of CLBs, and
the extra interconnect delays hurt.
Jan Gray, Gray Research LLC
2. There was a serious, glaring bug in the Xilinx tools for Virtex with
respect to clock inversion between the LUT RAM and the FFs/latches, which
led good-intentioned designers down a garden path. Read all about
it the archive.