FPGA-FAQ    0006

Understanding The Bitstream Format for Parallel Configuration

Vendor Xilinx
FAQ Entry Author Philip Freidin
FAQ Entry Editor Philip Freidin
FAQ Entry Date 02/19/2001

Q. Please explain the Bitstream format, my chip cooks when configured

A. (Philip Freidin 13 Oct 1994)

Almost certainly what is wrong is that you are not giving the chip a valid bitstream. This is either because the data you are giving it is wrong because of address line or data line confusion, or because the data is not in the PROM the right way. After the program pin is released, there is a delay (depends on size of the device, for your XC3064, the 80mS delay is normal) that is called housecleaning, and is the chip scrubbing the memory to a known state before programming. During this time the address lines are not driven, but have a light pullup resistor enabled. The chip looks for some leading '1' bits, followed by a bit pattern of 0010 followed by a length count. The 0010 is read left to right, in terms of what the chip is looking for, and the length count is expected msb first. See page 2-120 of the data book (1994). I am assuming that you are selecting parallel up mode, so the addreses start at 0. For master down, the data is the same, just the address sequence starts  at ffff and counts down.

For serial configuration mode, the address lines are not driven, and the serial data is presented 1 bit at a time. The end result though is the same.

Assuming you have a length count of 46112 (decimal), 0x00B420 (hex) here is what the start of your PROM  MUST look like:

 msb            lsb      HEX
addr 0  1 1 1 1  1 1 1 1 FF
addr 1  0 0 0 0  0 1 0 0 04  (the 0 is the top 4 bits of LC, the 4
                              is the 0010)
addr 2  1 1 0 1  0 0 0 0 D0  (the 0 is the next 4 bits of LC, and the
                              D is the B of the LC)
addr 3  0 1 0 0  0 0 1 0 42  (the 2 is the 4 of LC, and the 4 is the
                              2 of the LC)
addr 4  1 1 1 1  0 0 0 0 F0  (the 0 is the lest sig nibble of LC, and
                              the F is the dummy bits before the
                              first data frame)
addr 5  x x x x  x x x 0 Xx  (the leat sig bit is the start bit of
                              the first data frame, the rest is
                              design dependant.)

As you can see, the data is sent MSB first, but is shifted from the LOW order end of the byte wide data comming from the EPROM. I.E. the first bit seen by the config logic is the LSB of ADDR 0.

If data is not sent in correctly, then the chip miss configures, and contention usually occurs. This leads to high current drawn. Dont put a bigger power supply on this, fix the bitstream. 

At the start of configuration, all of the header upto and including the first dummy bit that follows the length count comes out of the DOUT pin. If you watch this pin and the CCLK pin with a storage scope, or analyser, you should see the header in the sequence of 0010, 24 bit LC (MSB first), then constant high. If you see anything else, you have a problem. If the LC coming out is not what you expect, then check that you have the data lines connected up in the right order.