FPGA-FAQ    0019

Divide A Clock by N.5

FAQ Entry Author Philip Tsao
FAQ Entry Editor Philip Freidin
FAQ Entry Date 2004/07/31
Entry Update 2004/09/14

Q. How do I divide a clock N.5 and try to keep the duty cycle to 50%

Dividing a clock frequency by (N+1/2) (where N is an integer) is the same as 
multiplying the clock by 2/(2N+1). That is, multiplying the clock by two and 
dividing the result by 2N+1. The remainder of this article deals with how to 
multiply and divide clock frequencies by integer amounts.

Note that some fpgas may have fancy DLL's (delay locked loops) and/or PLL's 
(phase locked loops) with prescalars that can divide the clock for you. Check 
the vendor's documentation.


Dividing a clock frequency by an integer ratio can be done with sequential 
logic. Two or more frequency dividers can be cascaded to increase the divisor 
(resulting divisor is the product of the divisors of the individually cascaded 
dividers). Dividing a clock by two (or any power of two) simply requires that 
one toggle the output clock with every rising (or falling, depending on desired 
phase) edge of the input clock. The canonical example is a "divide-by-two" 
circuit implemented by a D flip flop with D driven by /Q, input clock going to 
CLK and output clock driven by Q.

  module divide_by_two( inclk, outclk );
    input inclk;
    output outclk;
    reg outclk;

    always @ ( posedge inclk )
        outclk = ~outclk;

Unfortunately, that was completely useless to us, because our desired divisor is 
of the form 2N+1 which is clearly not a power of 2.

Dividing by an odd number is somewhat trickier if we want to achieve 50% duty 
cycle of the output, as one is required to count ALL edges (both rising and 
falling) of the input clock. This can be done easily with flip flops that 
trigger on both edges of the clock. Unfortunately, the availability of these 
critters is hit or miss on an FPGA (more easily created if you're designing a 
fully custom ASIC) and if done the wrong way can create undesirable glitches and 
other hazards. The topic of dual edge triggered flip flops will be left to 
another story another time.

An alternative method to construct frequency dividers is to use a counter (up or 
down, it does not matter). Combinational logic is used to reset the counter 
after 2N cycles (where N is the divisor). The number of D (or T) flip flops is 
approximately equal to ceiling of log( divisor ).

The following is an example divide-by-3

      |             +---------------| )-+
      | +---------+ | +---------+ +-|/  |
      | |  -----  | | |  -----  | |     |
      | +-|D  /Q|-+ | +-|D  /Q|-+ |     |
      |   |     |   |   |     |   |     |
clkin-+---|> R Q|---+---|> R Q|---+out  |
           -----         -----          |
             |             |            |

The D flip flops are falling edge triggered. Rising edge trigger devices may be 
used with a different reset condition. This circuit is not guaranteed to power 
up in a valid state but will quickly converge to a valid state. Relative phase 
may be adjusted with a reset override. Note that while 50% duty cycle is 
maintained in this implementation, there is some phase delay (at least 2 clock-
to-Q delays). If a 50% duty cycle is not required, a simpler reset condition may 
be possible.


There appear to be two popular strategies for frequency multiplication: the 
Phase Locked Loop (PLL) and Delay Locked Loop (DLL). Both loops require a phase 
detector to compare the input clock and an internal reference signal. The output 
of the PLL phase detector controls a tunable high frequency oscillator while the 
output of the DLL phase detector controls a tunable delay line.

The following is an example implementation of a phase/frequency detector.

  logic high-|D Q|-----+--phi_1_leads
             |   |     |
       phi_1-|> R|     |
              ---   /|-+
                |--( |
              ---   \|-+
  logic high-|D R|     |
             |   |     |
       phi_2-|> Q|-----+--phi_2_leads

phi_1 and phi_2 are the signals that are to be compared. The outputs 
(phi_1_leads, phi_2_leads) either control a variable frequency oscillator
or a tunable delay line.

In the case of the PLL, the built in oscillator must operate at or well above 
the desired frequency multiple. The output of this oscillator is divided down 
(depending on the desired multiple) so it can be compared with the input clock. 
The frequency of the oscillator is adjusted by the phase detector (not directly, 
but generally through a loop filter for stability reasons) until the phase 
relationship between the input clock and the divided output is nearly the same. 
When this happens, the output is said to be in "phase lock" with the input.

The DLL replaces the oscillator with a high precision tunable delay line with 
periodic output taps. The clock input is fed into one side of the delay and the 
phase detector compares this input with whatever comes out the other end. When 
the input and output are in phase with each other (hopefully delayed by 2pi 
radians), the signals from the periodic output taps represent equi-phase shifted 
versions of the input signal around the unit circle. The number of output taps 
determines the frequency multiplier. These phase shifted signals can be combined 
to generate the multiplied clock.

Both the PLL and DLL can be constructed out of purely digital or mixed signal 
(analog and digital) components. Pure digital implementations only permit 
control of oscillator frequencies and delay line latencies over discrete 
intervals and may produce undesirable jitter. Mixed signal implementations allow 
for continuous control over loop parameters.

The following is an outline of a DLL implementation that multiplies an input 
signal by two. As this is an outline of a design, there are optimization 
opportunities depending on the specifics of your requirements.

        +---------------------------|phase   |-+
        |                           |        | |  __
        |        +------------------|detector| +--\ \
        |        |                   --------     |  )--output
        |        |                             +--/_/
        |        |                   --------  |
        |        |      +-----------|phase   |-+
        |        |      |           |        |
        |        |      |         +-|detector|
        |        |      |         |  --------
        |  ---------------------  |
        +-| D E L A Y   L I N E |-+
        |  ---------------------  |
        |  --------  | |          |
  input-+-|phase   |-+ |delay     |
          |        |   |ctrl      |
        +-|detector|---+          |
        |  --------               |
        |                         |

Note that the multiplier can produce a 50% duty cycle output even when the input 
duty cycle is not 50%.

If a 50% duty cycle is not needed, then a full PLL or DLL multiplier may not be 
necessary. Tricks include feeding the input clock and a delayed copy into an XOR 
gate. One must be very careful in designing systems without 50% duty cycle 
clocks in the absense of PLL's or DLL's.

Non 50% duty cycle dividers
Non 50% duty cycle multiplier
XOR and shift registers approach
Phase frequency detector
Delay locked loops (DLL)
Frequency synthesizers
Unusual clock dividers by Peter Alfke
An HDL generator that may prove useful