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On Mon, 22 Sep 1997 19:14:48 -0700, db <"brandis<NO-SPAM>"@dlcc.com> wrote: >Is this true? I believe that Neocad could have placed & routed a Xilinx >FPGA and output a .lca file, which is just a netlist-like description of >the final design. At that point the user would run the Xilinx Makebits >utility to create the actual bitstream. You would not need to know the >actual bitstream format. Of course, you would still have to buy >software from Xilinx. However, I never used Neocad so I am not sure of >any of this...I'm only guessing. Am I right? NeoCAD generated bitstream. You did not buy additional tools, except the front-end :-) Stuart -- For Email remove "die.spammer." from the addressArticle: 7576
Could anyone recommend an in-system (re-)programmable serial EEPROM which can boot and configure the Altera FLEX 10k devices? And a cheap programmer/serial cable assembly to program these EEPROMs in-situ? Could you also indicate whether one EEPROM can boot a number of PLDs, and if so, how do you create the single burn file from the individual device files. Marty Hoffensetz CAE MRad Pty Ltd Adelaide, Australia marty@mrad.com.auArticle: 7577
Hi, We have an opportunity for an individual who has done some complex Circuit Board/FPGA design to work at a place where cutting edge technology is the norm, and one of the very best design staffs in the country awaits. This position is for someone who has between 3-10 years of high performance custom circuit design under his/her belt. You will be working on some of the "neatest" projects you've ever seen, and will become a stellar hardware designer for your efforts. Some of the "buzz": We are looking for High Speed Digital Designers, having some experience with PLD's, FPGA's (ASICS), complex designs (nothing simple at this place), understands timings, etc... Not a person who still needs a lot of instruction, we are hoping to find an individual who can stand alone and bring a project in from scratch to production. This is a great company! Our guarantee is this: If you go in and chat with these people, you WILL want to work there, especially if you can do this type of work. They are located on the North side of Chicago, near Skokie or Evanston, just off the Kennedy. Salary will be very nice, they're not cheap, as they're looking for the best we can bring in. Please E-mail or Fax us at: Hunter International E-mail: cleaner@starnetinc.com Fax: (815)356-9225 Thanks, Dave...Article: 7578
Hi, I'm using Xilinx Foundation M1.3 tools for an XC4000XL design. I have a top level schematic with VHDL coded symbols. On the schematic I have the startup symbol. I have tried using the attribute attribute Xilinx_GSR : boolean; but it doesn't work. After I examin the on-line help in detail I saw that this only works if you output in XNF format. I have been outputing in EDIF format. Any suggestions???? ThanksArticle: 7579
Is there any development software for CPLD^s on other platforms than DOS/WINDOWS ? (eg.: LINUX) This time I like the MACH family from AMD/Vantis, but it could be other too. Simple CPLD Assembler and JTag Programmer would be fine. Thanx, DirkArticle: 7580
On Mon, 22 Sep 1997 22:21:45 -0600, Matt Boman <bo3468ma@uscolo.edu> wrote: >I got the eval software from xilinx, with a 250 times key. I've >installed the whole pro series software, which is what I need to use for >the design (XC3000). When I start ProCapture everything works fine >untill I want to add a component and I get a windows error (included in >message). If anyone has used this sofware with win95 oem2, Please give >me any information that can make this stuff work, I realy need it and I >dont want to install win3.11.... Pro series and Win95? Never seen it work. Either get the Aldec stuff (Foundation) or insist on a WVOffice loan. Why is Xilinx still shipping this old (unsupported) stuff anyway? Stuart -- For Email remove "die.spammer." from the addressArticle: 7581
On Tue, 23 Sep 97 15:47:33 GMT, andym@trend.demon.co.uk (Andrew Morley) wrote: >You mean there's silicon available which is infinitely fast? I guess I haven't >been keeping abreast of the latest technology. Don't give the marketeers ideas! : "XYZ Corporation predicts infinite speed FPGAs by 2000. XYZ Corporation announced plans for superconductor zillion gate FPGA's today. I M A Liar (VP marketing) said that the new devices will be so cheap, they will be available at sub $1 per 50,000 gates in OEM quantities. (Big *don't blame us if you get burnt* disclaimer)" :-) Stuart -- For Email remove "die.spammer." from the addressArticle: 7582
hi, i've used pro series w/ win 3.1 and it would of course crash but it was relatively usable. but this is pretty *old* stuff and w/ win '95 we use the wv office product. of course that crashes too but is relatively usable. i'd call viewlogic to see if proseries is even compatible w/ win '95 or email them - they generally respond quickly. if my memory is working at this early hour, it's 1-800-cae-view or pc-support@viewlogic.com hope this helps, ------------------------------------------------------------ rk "there's nothing like real data to screw up a great theory," - me, modified from the slightly more colorful original ------------------------------------------------------------ Matt Boman <bo3468ma@uscolo.edu> wrote in article <342743D8.6747DB34@uscolo.edu>... > I got the eval software from xilinx, with a 250 times key. I've > installed the whole pro series software, which is what I need to use for > the design (XC3000). When I start ProCapture everything works fine > untill I want to add a component and I get a windows error (included in > message). If anyone has used this sofware with win95 oem2, Please give > me any information that can make this stuff work, I realy need it and I > dont want to install win3.11.... > > Matt > > Windows 95 crash dump (this happens EVERY time): > PROCAPTU caused a stack fault in module USER.EXE at 001c:00003112. > Registers: > EAX=00000000 CS=16e7 EIP=00003112 EFLGS=00000216 > EBX=83cb0012 SS=4c67 ESP=00000000 EBP=83cb0028 > ECX=00000000 DS=16c7 ESI=00000028 FS=433f > EDX=00000000 ES=015f EDI=00022608 GS=0000 > Bytes at CS:EIP: > 9a 38 07 af 17 36 89 44 f0 36 89 54 f2 8b 5e 2c > Stack dump: > 00000000 00090000 4b482608 fedafeda 00000000 00000000 4c670000 00000000 > 00040000 16e72c18 bff714d9 00000157 83cb1698 0000015f 0000433f 00020000 > > > -------------==== Posted via Sexzilla News ====------------------ > http://www.sexzilla.com Search, Read, Post to Usenet > -------------==== With A Whole Lot More ====------------------ > >Article: 7583
Achim Gratz wrote:
> "Daniel K. Elftmann" <dane@usinternet.com> writes:
>
> > Actel has free software downloadable off the web site for FPGA devices up
> > to 8K. This includes ActMap VHDL synthesis, ActGen module generator, and
> > Designer Place and Route.
>
> Oh, did you mention that you can't use the 3200 series _with_ RAM,
> because they start at 10K gates (the 32100DX). You can generate
> macros with RAM allright, but then you're stuck. Could Actel please
> consider raising the bar to 10K (that would just add the 14100 and the
> 32100, IIRC) or limiting to the gates used instead of available?
>
I love the idea of Quicklogic.They have a complete development system for sale.
On the other hand they have the place and route tools
available for free. This is a great thing for us owner of
front end software, like Synario, because you only want
the back end tools to interface with the front end. Usually
you don't need all the fancy front end tools the company
has decided to sell.
Bye
Matija
> Achim Gratz.
In chaos all things are possible.
Matija Milostnik, RDHW, IskraTEL, Ljubljanska 24a, SLO-4000 Kranj, Slovenia
Tel: +386 64 27 2125, Fax: +386 64 221 552, Email: milostnik@iskratel.si
-------------==== Posted via Sexzilla News ====------------------
http://www.sexzilla.com Search, Read, Post to Usenet
-------------==== With A Whole Lot More ====------------------
Article: 7584hello, I m make a schematic with viewlogic, in this you have some VHDL block and logiblox. To make the simulation with logiblox you have a special soft, but he remove the vhdl parts. i m enjoy to make a schematic with the vhdl and simulate all. do you have one idea?Article: 7585
Hi, I would like to generate EDIF 2.0.0 entries for the XACTStep 6000 series tool of Xilinx. I'am looking for informations about the EDIF specs of xc6200 gates (for example, an EDIF file corresponding to a combinational or sequential circuit mapping on xc6200). Many thanks for help. Bye. ll -- ------------ Laurent Lemarchand PhD student Universite de Bretagne Occidentale E-mail: lemarch@univ-brest.fr UFR Sciences et Techniques Tel: (33-2) 98 01 62 17 Departement d'Informatique Fax: (33-2) 98 01 62 15 BP 809 (33-2) 98 01 69 80 29285 Brest Cedex ------------Article: 7586
Is it possible to do gray code math? In particular: I'm using two 4-bit gray code counters as FIFO pointers. Is there a simple circuit that can determine when the difference between these two pointers is greater than 7.Article: 7587
Looking at the 4-bit grey code table found on http://www.udri.udayton.edu/imagepro/graycode/graycode.html it looks as though you just need to XOR the most significant bits to do what you want. As for more general arithmetic, I don't know. regards, tom (tburgess@drao.nrc.ca) Don Husby wrote: > > Is it possible to do gray code math? > > In particular: > I'm using two 4-bit gray code counters as FIFO pointers. > Is there a simple circuit that can determine when the difference > between these two pointers is greater than 7.Article: 7588
Tom Burgess tburgess@drao.nrc.ca wrote:
> Looking at the 4-bit grey code table found on
> http://www.udri.udayton.edu/imagepro/graycode/graycode.html
> it looks as though you just need to XOR the most significant
> bits to do what you want. As for more general arithmetic,
> I don't know.
You can use something like that to tell when two numbers differ
by exactly 8, but not to tell if the difference is >=8.
Consider, for example 8 and 3 (1100 and 0010). Just XORing the
upper bits is not good enough.
Answering my own question, I came up with a circuit that uses
1.5 ORCA PFUs (or 3 Xilinx 4000 CLBs)
It doesn't answer the general question regarding gray code math, but
it does solve my particular problem:
---------------------------------------------------------
Given two gray code counters (write pointer and read pointer)
W3,W2,W1,W0 and R3,R2,R1,R0
Construct a function of the upper bits that determines whether
the difference is less than 8 (L) greater than eleven (G) or
between 8 and 11 (EA or ED). Let EA indicate that R1 and R2 are
in an ascending gray code sequence. ED indicates they are descending.
W3,W2
00 01 11 10
R3,R2 -----------------
00 | L | L | EA| G | H1 = L+G = /R3@W3 + /R2@W2
----------------- H0 = L+EA = R3@W2 + /R3*/R2*/W3 + R3*R2*W3
01 | G | L | L | ED|
-----------------
11 | EA| G | L | L |
-----------------
10 | L | ED| G | L |
-----------------
Construct functions of the lower bits that indicate W1,W0 >= R1,R0
for both the ascending sequence (GA) and descending sequence (GD).
W1,W0
00 01 11 10
R1,R0 -----------------
00 | GA| GA| GA| GA| GA = /R1*/R0 + W1*/W0 + /R1*W0 + R0*W1
-----------------
01 | | GA| GA| GA|
-----------------
11 | | | GA| GA|
-----------------
10 | | | | GA|
-----------------
W1,W0
00 01 11 10
R1,R0 -----------------
00 | GD| | | | GD = /W1*/W0 + R1*/R0 + /W1*R0 + W0*R1
-----------------
01 | GD| GD| | |
-----------------
11 | GD| GD| GD| |
-----------------
10 | GD| GD| GD| GD|
-----------------
The output function is
OUT = G ! W-R > 11
+ EA*GA ! 11 >= W-R >= 8 and R1,R0 are ascending
+ ED*GD ! 11 >= W-R >= 8 and R1,R0 are descending
OUT = H1*/H0 + /H1*H0*EA + /H1*/H0*ED
The whole function fits easily in three XC4000 CLBs.
Article: 7589Marty Hoffensetz wrote in article >Could anyone recommend an in-system (re-)programmable serial EEPROM which >can boot and configure the Altera FLEX 10k devices? And a cheap >programmer/serial cable assembly to program these EEPROMs in-situ? > Check-out http://www.atmel.com/atmel/products/fpga/fpga1.html there is a section on Altera towards the bottom of the AT17 series FAQ. >Could you also indicate whether one EEPROM can boot a number of PLDs, and >if so, how do you create the single burn file from the individual device >files. > If the PLDs are JTAG based loading then I think you are stuck with a microcontroller and NV memory (Flash/EEPROM/EPROM) type solution and writing the JTAG loading scheme in microcode. Configurators only work with the '17' series style programming interface. Martin Mason. Atmel Corp. > >Marty Hoffensetz >CAE MRad Pty Ltd >Adelaide, Australia >marty@mrad.com.au > >Article: 7590
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Article: 7591In a previous article nickg@hpqt0220.sqf.hp.com (Nick Gent) writes: : ;I know this subject has been covered here before, but I am still not sure of :one detail. ; :Can a 3.3v xilinx chip (4000XL or 5200XL -series) safely drive 5v CMOS parts? ; :The Oct '96 data book on page 6-2 suggests that "an external pull-up resistor ;to 5v on each such input will assure a sufficiently high input voltage" (i.e. :> 3.5v). (However, it then warns that your 3.3v supply could be compromised by ;all the currents flowing back through the ESD protection on the 3.3v drivers.) : ;I have contacted our local Xilinx support, and they sent me an email suggesting :that we use TRISTATE outputs (drive low, hi-z for high). Are they implicitly ;suggesting that there is a problem with a simple pull-up? : ;Has anyone actually tried this for real? Do you get a good enough drive for :CMOS (with some noise margin)? MOS transistors conduct current in both directions. When an output is trying to drive high, it switchs on the P-channel transistor and connect the output to the supply rail. Which way the current flows depends on which side has higher voltage. If you are pulling the output above 3.3V using a resistor, then current will flow into the supply rail and compromising the 3.3V supply. Thus the advise you got from them was to never turn on the P-channel transistor, which means never actively drive the output high. Depending on your design, you may be able to get away with active driving high, and then use feedback to shut it off as soon as it see that the output is already high.Article: 7592
Matt I saw your message on arch.fpga NG. We can get you some complete software to do your XC3000 series stuff at a very low cost! No run limits. Schematic capture, (ALDEC which is VIEWLOGIC compatible and is what XILINX ships with the router),full CPLD support and some XC4000 and Xc5200 support plus ROUTER $375.00!!! This comes with the one years support and free upgrades direct from XILINX! I have one at this price. -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 7593
Richard Schwarz wrote: > Matt > > I saw your message on arch.fpga NG. We can get you some complete > software > to do your XC3000 series stuff at a very low cost! No run limits. > Schematic capture, > (ALDEC which is VIEWLOGIC compatible and is what XILINX ships with the > > router),full CPLD support and some XC4000 and Xc5200 support plus > ROUTER > > $375.00!!! This comes with the one years support and free upgrades > direct from XILINX! I have one at this price. > > -- > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > __/ > > Richard Schwarz, President EDA & Engineering Tools > Associated Professional Systems (APS) http://www.associatedpro.com > 3003 Latrobe Court richard@associatedpro.com > Abingdon, Maryland 21009 > Phone: 410.569.5897 Fax:410.661.2760 > > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > __/ This is one which is left over from a canceled project. This is not a typical saleand is offered to anyone -not just Matt- who may need the tools. The tools are brand new still in the box. They also include the download cables. I hope this helps someone out. (I know I would have appretiated it when I was first starting out) -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 7594
New Lattice ISP Synario System will support all of the ispLSI1000 and 2000 family of devices including the ispLSI1048. List price is $495. Contact your local Lattice Rep. --ISP is Lattice-- > Bulent UNALMIS <unalmis@club-internet.fr> wrote in article > <341A5F6C.359A@club-internet.fr>... > > Hello, > > > > I have " Lattice Synario System ". > > Can I extend this system for ISPLSI1048 FPGA. ? > > Did you know any way ? (I search economic solve)Article: 7595
The next APS-EDA-Quarterly Newsletter is about to be released.. It is a free newsletter which discusses VHDL and FPGA topics as well as advances and the latest news in the EDA community. The next issue will be sent out in October. If you wish to subscribe just email us at eda@associatedpro.com with the words EDA SUBSCIBE in the subject header. You can see past issues on-line from our home page at http://www.associatedpro.com/aps -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 7596
I am currently working on an PCMCIA card with a Philips PZ3128 CPLD. I'm looking for a PCMCIA library for this kind of CPLD. If anybody knows how I can find this kind of library, I will be very interested. Thanks in advance. Emmanuel SIMLER E-mail : emmanuelsim@calva.netArticle: 7597
Arnie Buck wrote: > Hi, > > I'm using Xilinx Foundation M1.3 tools for an XC4000XL design. I have > a > top level schematic with VHDL coded symbols. On the schematic I have > the > startup symbol. I have tried using the attribute > > attribute Xilinx_GSR : boolean; > > but it doesn't work. After I examin the on-line help in detail I saw > that this only works if you output in XNF format. I have been > outputing > in EDIF format. > > Any suggestions???? > > Thanks Hello Arnie, I would not use the "Xilinx_GSR" attribute in your VHDL modules since you already have a STARTUP symbol in your schematic. Also, this attribute will not be supported by FPGA Express when it is integrated with Foundation. Assuming that you have an external pin that is connected to the GSR pin of STARTUP (possibly through an inverter), I would code all clocked processes with an active-high asynchronous reset/preset signal (i.e. the same physical signal that is attached to GSR). This will result in a routed reset signal attached to all applicable FFs in the design. Now functional simulation of a reset will work like the *real* device. Do not worry about the routed reset. The M1 program MAP will remove this redundant connection automatically and save routing resources. NOTE: MAP will only remove the redundant reset/GSR connection if the same physical net that is connected to GSR is connected to your FFs in the netlist. This is why I specified an active-high reset/preset. A synthesizer will infer an inverter if you specify an active-low reset, and then you do not have the same physical net, even though it is logically equivalent. There is an open bug at Xilinx to have MAP recognize logical equivalence. Hope this helps, -- / /\/ Ray Ehrisman \ \ Applications Engineer / / Xilinx Inc. Dallas, TX \ \/\ Telephone: (972) 960-1043Article: 7598
Editor's Note: Yikes! There's only 4 working days left for the SNUG'98 CFP
submission deadline so I thought I'd repost it plus add that Synopsys now
has a web page about it at "http://www.synopsys.com/events". - John
SNUG '98 Call For Papers
------------------------------
WHAT: Eighth Annual Synopsys Users Group (SNUG '98)
WHEN: March 11th-13th
WHERE: Double Tree Inn, San Jose, CA (formerly the Red Lion Inn)
An Invitation to Contribute
SHARE Your Experiences!
The success of a user's group depends on the active participation of users
who are willing to share their experiences with others. If you have
information on High-Level Design methodology or experiences with Synopsys
tools that would be of interest to other users, you are encouraged to
present in one of the sessions described below.
Preliminary User Breakout Sessions
These sessions are always the hit of the conference. Hear Synopsys users'
experience on specific topics. Each user breakout session will consist of
three presentations, twenty-five minutes each, with another five minutes for
questions and answers. Preliminary topics include:
*Synthesis/Design Productivity
Strategies, experiences, and best practices for design productivity
with an emphasis on synthesis. Automation and Optimization
techniques for synthesis.
*High-Level Verification
Verification strategies covering design for test and system-level
verification. Users share experiences in developing a test bed to
verify the combined hardware and software systems. Design for
test strategies for complex, large designs.
*Higher Levels of Abstraction / Behavioral Synthesis
This sessions covers real-world experiences in making the transition
to high-level design. Topics include the methodology for top-down
design, behavioral synthesis, & high-level techniques for DSP design.
*Deep Submicron / Large Designs
Concentrating on the unique challenges of submicron and large
designs. Sessions provide experience with automating scripts for
submicron, special techniques for managing wireloading,
floorplanning, and non-linear delay modeling.
*Makefiles/Synthesis Scripting
This is a popular session that was added to SNUG last year to
address the increased effort to automate and extend the synthesis
process through scripting. The session includes case studies by
users that have taken advantage of the power of Make and Perl
drive synthesis iterations and to extend DC Shell.
*Configuration Management
Management of files and directory structures is a big key
toward design success. This session will explore approaches
or methods like MAKE used to manage the complex designs of today.
*Design Reuse
This session includes a practical methodology for design reuse
based on real-world experience. Issues and guidelines are explored.
*FPGA Synthesis
This year a new session will be added that will focus directly on
synthesis of FPGAs. Tricks and techniques used for designing and
synthesizing FPGAs will be presented. Experiences with FPGA Express
will also be included.
To present your experiences with a contribution in an user session, please
forward a summary or brief description of your idea to the conference
Technical Committee, (snug_tech@synopsys.com), by October 1, 1997. You
will be notified of your acceptance shortly afterwards. A Technical
Committee member will work with each author to develop and review the paper
and presentation. Please review the Author's kit posted on the Synopsys
web site for details on paper format and structure.
Final drafts are due by January 5, 1998.
Final papers are due for publication in the SNUG proceedings by
February 2, 1998.
A Preliminary SNUG '98 Schedule
Wednesday, March 11th
Morning 1/2 day Tutorial Sessions
Afternoon Industry related Panel Discussion
Evening R&D Cocktail Party /Synopsys New
Product Demos
Thursday, March 12th
Morning Executive Status
Morning/Afternoon User Breakout Sessions
Evening Cocktail Party / Vendor Fair
Friday, March 13th
Morning 1/2 day Tutorial Sessions
Who to Contact
Should you wish to discuss your potential contribution, please feel free to
contact your local Synopsys applications engineering manager or the SNUG'98
Technical Committee via email at:
snug_tech@synopsys.com
All email sent to this alias will be reflected to User Group Technical
Chairperson and the Technical Committee. These addresses are NOT for basic
information on attending the conference itself.
Don Mills, Renae Cunningham,
SNUG '98 User Chairman SNUG '98 Synopsys Program Manager
640 North 2200 West 700 E. Middlefield Road
MS F1-J12 Mtn. View, CA. 94043
Salt Lake City, UT Fax: 415-965-2539
Phone: 801-594-3270 renae@synopsys.com
donald.r.mills@lmco.com
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 5459 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 7599
(believe I sent just to Don, meaning to send to group - forgive me
if this is a double post)
Don Husby wrote:
>
> Tom Burgess tburgess@drao.nrc.ca wrote:
> > Looking at the 4-bit grey code table found on
> > http://www.udri.udayton.edu/imagepro/graycode/graycode.html
> > it looks as though you just need to XOR the most significant
> > bits to do what you want. As for more general arithmetic,
> > I don't know.
>
> You can use something like that to tell when two numbers differ
> by exactly 8, but not to tell if the difference is >=8.
> Consider, for example 8 and 3 (1100 and 0010). Just XORing the
> upper bits is not good enough.
>
<remainder snipped>
Oops!, you are quite correct. What was I thinking? I think the general
problem is complicated since the Gray code is a non-weighted code,
requiring conversion to weighted binary before arithmetic
(in general) can be performed. Looking at how a Gray to Binary
conversion works,
B0 = (G0 ^ G1 ^ G2 ^ G3), B1 = (G1 ^ G2 ^ G3), B2 = (G2 ^ G3), B3 = G3
the fan-in to the least significant bit is highest and decreases towards
the upper bits, which is the opposite of the fan-in increase of an adder
(including carry propagation). Thus it seems unlikely to me that
starting with a combination of Gray conversion and a general
addition-type function one will have much success with logic
minimization, except for special cases.
regards, tom
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