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Which synthesis tool are you using? The fact that it doesn't fit my have
nothing
to do with lack of LCELLs.
Regards,
Kayvon Irani
Los Angeles, US
lzh@bd748.pku.edu.cn wrote:
> Dear all: i'm using Altera's Maxplus2 to complete my project and use
> VHDL as design entry, because the logic is complex,Maxplus2 fails to fit
> it,i think i have to insert some LCELLs into my VHDL source files,but i
> have no idea about how to do this,can anybody help me? any help will be
> appreciated!!
>
> -------------------==== Posted via Deja News ====-----------------------
> http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 8501APS offers a great selection of low cost FPGA test and debug boards which can be used on the PC ISA and stand alone. The advantage of being on the ISA bus is that the SRAM FPGAs can have their configuration images loaded right into the FPGA via the ISA Bus using ant PC IO control mechanism, like a C/C++/PASCAL/BASIC/etc.. compiler. Further the design or test code can be exersised via the programable IO on the test boards which can be controllerd and read from the PC ISA bus. Boiler Plates and example designs doing just that are available and come with the test boards. VHDL labs and projects are also available: See: http://www.associatedpro.com/aps -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 8502
On running xnfdrc.exe (in XDM/XACT v2.10) the following error is encountered at the start of program execution. The PC is an 486DX2/66 with 16meg. The same version runs fine on my 486/25. The error also occurs on a Cyrix 6x86 P133+ with 32meg (the Xilix dongle is not even recognized with this PC). Compile times on the 486/25 are running 3.5 hours so I really need to speed things up. Since this version is no longer supported (& I cannot afford to upgrade) Xilinx has no answers. "Abnormal program termination: memory fault CS:EIP = 000C:000173E7" Any ideas would be greatly appreciated. Thanks in advance, Bill Manzarek billmanzarek@worldnet.att.net -or- Bill.manzarek@nmp.nokia.comArticle: 8503
> >>>I got the new M1 product update to XACT step for PCs, and I would love to >>>try it but the licensing system is seriously braindead. It uses flexlm and >>>a parallel port dongle for copy protection. This would be fine (PADS PCB >>>uses this method also, and it works fine), but it also requires a matching >>>hard drive partition serial number. Now I don't understand how this >>>improves security either, but there it is. They require it. In fact their >>>flexlm license file is generated to match it, and their web-based license >>>file generator gives you only one shot to create this file, and gives you >no >>>opportunity to change your mind about what hard drive you're going to >>>install the program on. >>> >>>So they expect: >>> - you to run their software on one machine only: no switching dongles to >>> my lap-top anymore >>> >>> - your hard drive to never break >>> >>> - you to never upgrade the hard drive in your machine >>> >>> - hmm... maybe they don't require the dongle any more and the security >>> is based entirely on the partition serial number. This is great news! >>> I'll install it on all my machines and edit the volume name entry of >>> each of them to match! >> >>It's true! The key is no longer needed and the security is entirely based >>on the partition serial number. This is vastly more conventient than that >>silly hardware key thing. I won't have to lug that key around when I use >>my laptop anymore. >> >>Now suppose you have linux installed on your hard (as I do) and the >>Windows-95 vfat partition is /dev/hda2 and you want the serial number to be >>(hex) AABB-CCDD: >> >>log into root, >> >>type: joe /dev/hda2,39,4 # edits bytes 39-42 of drive C boot sector >>type: ^T T # put joe into overtype mode >>type: ` x D D ` x C C ` x B B ` x A A # Enters new serial number >>type: ^K X # saves data back to disk >> >>You could also do this from Windows-95 but you would have to write a C >>program. Remember it's bytes 39-42 of the first sector of the C: partition. >>Be sure to make backups before messing with your boot sector. > >Actually I forgotten about the MS-DOS debug command, which >surprisingly, is >still provided with windows-95. This is the easiest way to change the >serial number without linux, but be very careful (back up your >files!), as >debug is not very forgiving: > >C:\>debug >l 0 2 0 1 - load one sector beginning with sector 0 of > drive 2 (C:) into address 0 (of some >segment) >e 27 - hex entry mode >DD <SPACE> CC <SPACE> BB <SPACE> AA <RETURN> >d 0 - display to verify results >w 0 2 0 1 - write boot sector back to hard drive >q - quit >C:\> > > > > > Take notice of the need to back up your hard disk first! I tried the "debug" method on one PC without problems. When I tried it on another PC, which had a newer version of Windows 95 with FAT32 (?), the computer would no longer boot off drive C:, and I had to reformat it to recover. A colleague spotted that the serial number was at a different location (required e43 rather than e27) with this type of FAT. When we changed it here it appeared to change the serial number OK, but again the computer would not boot from drive C: Anyone got any idea how to get round these problems? THANKS, S E EdwardsArticle: 8504
In article <6868um$a72@mtinsc04.worldnet.att.net>, bill manzarek <billmanzarek@worldnet.att.net> writes >On running xnfdrc.exe (in XDM/XACT v2.10) the following error is >encountered sorry cant help with that apart from to say an early version of apr fails (crashs around the end of routing) on several new pentiums I have tried. My suspicion was that there was a memory problem with the DOS extender but I have not been able to fix it. As several of my designs are still with the old (non-unified) libraries its a pig. >at the start of program execution. The PC is an 486DX2/66 with 16meg. >The >same version runs fine on my 486/25. The error also occurs on a Cyrix >6x86 P133+ with 32meg (the Xilix dongle is not even recognized with this >PC). I *think* you could try adding an ISA parallel port board to connect the dongle, the older the better. I tried that and it worked for me even though it was a relatively new ISA board with some extended modes. > Compile times on the 486/25 are running 3.5 hours so I really need to >speed >things up. Since this version is no longer supported (& I cannot afford >to upgrade) Xilinx has no answers. > > "Abnormal program termination: memory fault > CS:EIP = 000C:000173E7" > >Any ideas would be greatly appreciated. -- Steve Goodwin... De-spamming active, remove any _DSPM from addressArticle: 8505
Steve Goodwin wrote: > > In article <6868um$a72@mtinsc04.worldnet.att.net>, bill manzarek > <billmanzarek@worldnet.att.net> writes > >On running xnfdrc.exe (in XDM/XACT v2.10) the following error is > >encountered > sorry cant help with that apart from to say an early version of apr > fails (crashs around the end of routing) on several new pentiums I have > tried. My suspicion was that there was a memory problem with the DOS > extender but I have not been able to fix it. As several of my designs > are still with the old (non-unified) libraries its a pig. I DO know that anything over 16meg seems to crash DOS\16m(DOS extender). It won't even pass the pmtest. NEVER have been able to get XACT 2.10 running on any PC with more than 16m. > > >at the start of program execution. The PC is an 486DX2/66 with 16meg. > >The > >same version runs fine on my 486/25. The error also occurs on a Cyrix > >6x86 P133+ with 32meg (the Xilix dongle is not even recognized with this > >PC). > I *think* you could try adding an ISA parallel port board to connect the > dongle, the older the better. I tried that and it worked for me even > though it was a relatively new ISA board with some extended modes. > > > Compile times on the 486/25 are running 3.5 hours so I really need to > >speed > >things up. Since this version is no longer supported (& I cannot afford > >to upgrade) Xilinx has no answers. > > > > "Abnormal program termination: memory fault > > CS:EIP = 000C:000173E7" > > > >Any ideas would be greatly appreciated. > -- > Steve Goodwin... De-spamming active, remove any _DSPM from addressArticle: 8506
lzh@bd748.pku.edu.cn wrote: > > Dear all: i'm using Altera's Maxplus2 to complete my project and use > VHDL as design entry, because the logic is complex,Maxplus2 fails to fit > it,i think i have to insert some LCELLs into my VHDL source files,but i > have no idea about how to do this,can anybody help me? any help will be > appreciated!! > > -------------------==== Posted via Deja News ====----------------------- > http://www.dejanews.com/ Search, Read, Post to Usenet Hi, I did it with Exemplar's Galileo and Leonardo before. First of all, add LCELL component definition in your architecture declaration. The port order can be found in Altera's macro data book. Depending on the Synthesis tool you use, you might have to bind the component to pre-compiled component package, so that the synthesis tool can consider the timing and area contributed by these Lcells. In this case, you might need to add LIBRARY statement before the entity statement. However, most of the synthesizers would do by treating them as BLACK BOX. In this case, just dont write any component binding statement. Secondly, using standard component instantiation and port map syntax in the architecture body. You think inserting Lcell can help fitting in the Flex devices? Well, adding Lcell has some effects in successful routing. With more advanced version of Max+PlusII, which can add Lcell automatically, you seem not have to do that, since you will make your VHDL mode TECHNOLOGY DEPENDENT. Regards, Felix CHENArticle: 8507
In article <6888f9$q2@bgtnsc03.worldnet.att.net>, bill manzarek <billmanzarek@worldnet.att.net> writes >Steve Goodwin wrote: >> >> In article <6868um$a72@mtinsc04.worldnet.att.net>, bill manzarek >> <billmanzarek@worldnet.att.net> writes >> >On running xnfdrc.exe (in XDM/XACT v2.10) the following error is >> >encountered > >> sorry cant help with that apart from to say an early version of apr >> fails (crashs around the end of routing) on several new pentiums I have >> tried. My suspicion was that there was a memory problem with the DOS >> extender but I have not been able to fix it. As several of my designs >> are still with the old (non-unified) libraries its a pig. > >I DO know that anything over 16meg seems to crash DOS\16m(DOS extender). >It won't even pass the pmtest. NEVER have been able to get XACT 2.10 >running on any PC with more than 16m. Thanks for the info, I never thought I'd be taking memory *out* regards -- Steve Goodwin... De-spamming active, remove any _DSPM from addressArticle: 8508
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Ken Chung wrote: > I have an experience. Consider a simple asynchronous reset D-type flip > > flop, I have successfully got the bitstream file by using Synopsys and > Xilinx M1.3.7 in WS. But, I failed in PC by using Foundation. It > minimized my design such that it contained nothing. I don't know why. > Any idea? > > Regards, > Ken If you have foundation implementation tools installed you have no problem but in case if you are using Alliance implementation tools on PC (which doesn's have metamor PM) will result in trimming of BUFG's and the following logic (in your case D-Flop). A simple workaround is try running ngdbuild with -p option, this forces to add PAD's to all top level port signals thus preserving bufg's (note bufg's should be on toplevel). Or else you can use rules file having ngdbuild -p option in it. Regards, -Prashanth Banuru.Article: 8510
>I DO know that anything over 16meg seems to crash DOS\16m(DOS extender). >It won't even pass the pmtest. NEVER have been able to get XACT 2.10 >running on any PC with more than 16m. PMTEST certainly crashes on any PC over 16MB, but I have been successfully running the old software (Viewlogic and APR) on a P200 with 32MB RAM. This is software dated 1991. PPR from XACT 2 I cannot speak for, since the only PPR I have used is from XACT6 and that one is certainly OK. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8511
G. Herrmannsfeldt wrote: > I am wondering about the dynamic power. > If on the average a signal changes every other clock cycle, > how much power should I expect out of this? > Glen, Look in Xilinx 1996 databook, Page 13-12.Article: 8512
> Or else you can use rules file having ngdbuild -p > option in it. I meant ngdbuild -a option.Article: 8513
> >> In article <6868um$a72@mtinsc04.worldnet.att.net>, bill manzarek > >> <billmanzarek@worldnet.att.net> writes > >> >On running xnfdrc.exe (in XDM/XACT v2.10) the following error is > >> >encountered I am no longer get the error message........ The problem was an invalid (& unused) directory in the path statement (very strange error message for that & never caused any other problem)...... Only remaining problem is getting the P166+ 6x86 to recognize the "Hardware Protection Key". I'm using an OLD ISA parallel card & still no luck. Any ideas?? Thanks in advance, Bill Manzarek billmanzarek@worldnet.att.net -or- Bill.manzarek@nmp.nokia.comArticle: 8514
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Article: 8515On Tue, 16 Dec 1997 00:49:50 -0500, "Sanford Hayes" <shayes@plainfield.bypass.com> wrote: >Anbody care to comment on why Xilinx stock has been dropping this year ? It's dropped a bit in 1997, but the long term trend is still upward. Xilinx was around $38 in December 96, rose to a peak of $57 in May 97, and then fell back to about $34 in December '97 month. Altera exhibited a similar cycle with a start of $35, a steady(ish) rise to $65 in August, but then steeper decline again to about $34 in December. Couple of ideas though on why the drop for Xilinx: Negligible growth '96 to '97 results (Profits fairly stable though). Loss of market lead to Altera. Fire at UMC(?) A perception that they had lost the technical lead. The abortive excursion into antifuse. Stock repurchase scheme in December '96 (Supply side economics?) Repeated this month. You can take a look at www.nasdaq.com to see the historical numbers and graphs. e.g.: Past 12 Past 3 month month Close 12 month 3 month high high now movement movement Altera $65 $58 $34 -60% -41% Xilinx $57 $54 $34 -40% -37% Intel $100 $98 $72 -28% -27% See, you can make everybody look like they are in the smelly stuff, with Altera actually worse than Xilinx. Spooky isn't it? Why has it happened? Nobody really knows, the market is a fickle beast. Perhaps the fire at UMC(?) didn't help anyone. Maybe technical analysts are getting tired of the latest promises from the vendors, when customers are having to deal with the reality of today. That's true across all areas of the semiconductor industry. After all, two million gates at 10 Hertz isn't going to be much of a draw is it? Perhaps analysts see the market slowing in incremental growth, with an emphasis on price, rather than margin. The recent problems in Asia may have caused a temporary blip, but may help the fortunes of US and European semiconductor companies who don't have too large a reliance on the Asia-Pacific market, which by and large seems to be true of the programmable logic companies, althought growth in Asia has been strong over the last 12 months. Helpfully, Altera produces a graph showing quarter by quarter revenue from Q4/92 to Q3/97, which matches very closely with their stock price variation over the same period. (No surprises there. People buy stock to make money, and for them to make money, you have to make money, and pay nice fat dividends.) The price cutting strategy of Altera that really started in '96 (ish) seemed to impact CY96 Q2,Q3,Q4 revenue and net profit for both themselves & Xilinx, and it was only by Q1/97 that Altera got back past the Q1/96 figure. It probably seemed like a good idea at the time, but the growth after the reduction seems to be at a fairly similar rate as before. Altera could be heading for a reduction in growth if the reported problems of low speed and high power consumption of the larger 10K parts continue. There is a definite rolling 1.5 to 2 year cycle of semiconductor company stock prices, with a generally increased rate of climb that began around Q1/95. There's indication of a general market climb one year, and decline the next, but it's usually a case of two steps forward, one step back. Possibly an oversupply then "pull back" behaviour. Even the Intel stock price shows a similar pattern. If you pull the Nasdaq 72 month graphical results and stick them next to each other, you'll see the pattern. Why the recent drop for Xilinx and Altera? (almost in unison with each other) Some of it is natural market cycle, but if you look at what both companies are doing in the marketplace, then I believe that it offers some indication. Each company seems to be gunning for the other's core market space, but Altera appears to be making a better job of it. Somebody suggested to me the picture of Xilinx and Altera as two greyhounds at a race track who are so busy sniffing each other's behind, that they miss the rabbit altogether. :-) There is the structural problem of demand elasticity which still (IMHO) isn't clear. If Altera slashes the cost of a 10K100 from $140 to $20 over a 3 year period as it has forecast, then it will have to ship 7 times as many units in the year 2000 just to stand still in revenue terms (margins will likely reduce as well). That's a CAGR that is pretty frightening in what is perhaps a more mature market than some pundits predict. If you have the cash, you can buy a market by bombing prices, but long term it's a strategy that doesn't pay off in the silicon game. (ask the Koreans about DRAM and SRAM). Programmable logic vendors seem to rely more heavily on their newest/fastest/biggest poducts to generate their higher ASP and profitability, with the main line product families being lower margin, but hopefully higher revenue generators. I am not convinced whether this can continue for long. If vendors truly deliver a tenfold increase in density by the year 2000, and at the same time reduce costs to $1 per 5K gates, I wonder: What customers will be able to, or want to, use a million gate device? What the tool flow will be (Schematics anyone?). Big FPGA's become like big ASIC designs, so why not do the ASIC? What will the P&R time be? How much IP core will be around? (and will it be appropriate?) What will the power consumption be? How fast will they run? What support will it require? Just a few thoughts. Stuart -- For Email remove "die.spammer." from the addressArticle: 8516
Say where it is possible to copy the file a16450(MAX PLUS v7.10). Tdf for megafunctions a16450. Why it(he) not ASCII a format? Help to decide a problem ! Thank you very much. mail:paval@elnet.msk.ruArticle: 8517
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I'm using the Xilinx 4010XL and would like to interface it to the standard PC ISA bus. The IC's inputs are 5V tolerant, but can the outputs drive the 5V sensitive IS bus directly? Thanks in advance, Ivan.Article: 8519
>What customers will be able to, or want to, use a million gate device? A lot fewer than the PR machine claims. >What the tool flow will be (Schematics anyone?). Depends on the above. Schematics are certainly an easier way to get into FPGAs in a quick and useful way than VHDL etc. >Big FPGA's become like big ASIC designs, so why not do the ASIC? Quite. I reckon the very big FPGAs are useful for very specialised low volume high cost products, but much more for ASIC prototyping. Either way, volumes will be low. >What will the P&R time be? I think the question would be better phrased as what % utilisation will be achievable. >How much IP core will be around? (and will it be appropriate?) IP cores are useful only with big devices. I know lots of people who use FPGAs, and their ways of doing things just don't square up with the FPGA vendor PR stuff in the press. People still use large volumes of 10 year old XC3020 and 3030, because they replace a lot of logic and are cheap. IMHO. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8520
On Sat, 03 Jan 1998 08:53:23 GMT, z80@ds.com (Peter) wrote: >>What customers will be able to, or want to, use a million gate device? >A lot fewer than the PR machine claims. Agree. >>What the tool flow will be (Schematics anyone?). >Depends on the above. Schematics are certainly an easier way to get >into FPGAs in a quick and useful way than VHDL etc. Schematics are a little unwieldy for large devices. IMHO decent quality VHDL wins out almost all the time now. I've seen designers battle away at 8K gate designs and have over 100 printed sheets of schematics. Takes them ages to get to market too. (I once saw 18 months of engineering time go up in smoke because they missed their market window) >>Big FPGA's become like big ASIC designs, so why not do the ASIC? >Quite. I reckon the very big FPGAs are useful for very specialised low >volume high cost products, but much more for ASIC prototyping. Either >way, volumes will be low. Ahh, the phrase "ASIC prototyping". Guaranteed to strike fear into the heart of every fpga manufacturer (unless they are looking for an 'in' to the customer). >>What will the P&R time be? >I think the question would be better phrased as what % utilisation >will be achievable. Boils to a similar thing. P&R tends to be slightly exponential, as you have more blocks and more possible places to put those blocks. I see granularity inevitably decreasing, as vendors put more logic in a single step-and-repeat block. Will probably suit heirarchical design methodologies best. >I know lots of people who use FPGAs, and their ways of doing things >just don't square up with the FPGA vendor PR stuff in the press. >People still use large volumes of 10 year old XC3020 and 3030, because >they replace a lot of logic and are cheap. Indeed. But the vendors don't make much profit out of those low cost families any more. Eventually, the market will (IMHO) level off at a point where every vendor can do the speed, density, features, and power that 99% of designers require. Then it will just become a pissing match on price. It could even degenerate to the nightmare DRAM/SRAM model. Specialist vendors may survive by providing speciality architectures to the 1% remaining esoteric designs. You might find the vendors decide to cease production of low density parts such as 3000 series type densities. After all, if you pay (say) $3 for a 3020, and they all reach the promised $1 for 5K gates, then you'll probably be offered a 15K gate part as a starting point whether you like it or not. Of course, it'll have to be 1.8V with 3.3V I/O, and if you want a pure 5V part, you'll get screwed with an old 0.5 micron technology and price. Stuart -- For Email remove "die.spammer." from the addressArticle: 8521
I'm using Altera's EPM7128SQC100-15 in a design . I have a problem in my design . In my desing , a global clock is used and it has 30 fan-out . But it looks like it hasn't enough drive ability as many flip-flop don't work . Who can tell me how to resolve the problem ?Article: 8522
Does anyone know about this? I entered a schematic into MaxPlus2 and compiled. There were some gated reset in my schematic, therefore I expected no global reset could be used for the gated reset signal. But the result of the compile showed me that the reset signal used global signal. It confused me and I wondered I can go ahead with using the global signal. Has anyone had an experience like that ?Article: 8523
For design testing and verification FPGA test boards offer a surefire
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--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President EDA & Engineering Tools
Associated Professional Systems (APS) http://www.associatedpro.com
3003 Latrobe Court richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897 Fax:410.661.2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 8524Ivan wrote: > I'm using the Xilinx 4010XL and would like to interface it to > the standard PC ISA bus. The IC's inputs are 5V tolerant, but can the > outputs drive the 5V sensitive IS bus directly? > I don't have the ISA spec here, but I can tell you what the XC4000XL outputs can do: Actively pulling Low, the output impedance is between 14.4 and 20.5 Ohm, but the dc current should not continuously exceed 20 mA ( metal migration is the limiting factor). Actively pulling High, the output source impedance is 28 to 41 Ohm, same current warning. Driving more than its own Vcc is not possible, and you also cannot pull the active High output any higher than Vcc, since a CMOS output is resistive in both directions of current. The simple solution is to use "open collector" with a resistive pull-up, which really slows you down on the way to 5V. But: You can be sneaky and drive an active High level, but use the input coming from the same pin, and make it shut off the output drive ( OE ). Thus you get the benefit of a 30 Ohm impedance driving to 3.3 V, and the resistor ( 330 Ohm?) only has to finish the work. If teh OE control is a few ns slow, that actually helps in this case. It's a really neat trick ! Somebody else in Xilinx beat me to it, I am green with envy. We have characterized this, and it works like a champ. Peter Alfke, Xilinx Applications
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