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Messages from 100425

Article: 100425
Subject: Re: Accessing compact flash?????????
From: sachink321@gmail.com
Date: 8 Apr 2006 15:08:42 -0700
Links: << >>  << T >>  << A >>

Ray Andraka wrote:
> sachink321@gmail.com wrote:
>
> > Hi  Ray
> > im using CF for only Mass storage
> > it does not have to be read by PC
> > the problem is to address a particular sector
> > will LBA make it easier to address?
> > how do i do this addressing?
> > how does this thing work?
> >
>
> LBA makes it easier.  Basically you give it a sector number, which is an
> address to one of the sectors.  It will access one sector at at time,
> each sector is 512 bytes, presented two bytes at a time.  In order to be
> successful accessing it you really have to pick up the Compact Flash
> specification and study that.  I can't adequately describe the interface
> in a post.  You'll need either a state machine or a small
> microcontroller to sequence the commands to it.  For basic access,
> you'll need at least the identify, read sector and write sector commands.


Thanks,  that helps

i have already gone through CF spec
but one thing tht troubles me is this

lets suppose there are some files already in a compact flash
im trying to read those files
how will i know at which adresss or at which sector number or LBA is
tht particular file???
once i know tht particular LBA
i can acceess using read sector commmand
But how will i knw which Sector is tht particular file????


Article: 100426
Subject: C-Compiler for free VHDL controller core ?
From: Peter Winkler <idontwant@totell.com>
Date: Sun, 09 Apr 2006 00:10:20 +0200
Links: << >>  << T >>  << A >>
Hi !

I would like to use a free microcontroller core on my
Spartan 3 FPGA. 

There are quite some free cores available, but I would like to know
what everybody is using. It would be great if the free core would be
supported by gcc or some other free C-Compiler.

I also need a UART, so what I am searching for is:

* free FPGA controller core (with UART)
* C-Compiler supporting it

Do you know if something like this is available ? It is not
practical for a non-professional to license a controler
core and tool-chain, or ?

TIA
Peter



Article: 100427
Subject: Re: C-Compiler for free VHDL controller core ?
From: "Isaac Bosompem" <x86asm@gmail.com>
Date: 8 Apr 2006 16:10:26 -0700
Links: << >>  << T >>  << A >>
Maybe an OpenRISC?

They have a GCC port for the chip on freecores.org, though the simplest
config on my XC3S200 would use up ~75% of it!

-Isaac


Article: 100428
Subject: asynchronous FIFO design
From: "kelvins" <kelvins.huang@gmail.com>
Date: 8 Apr 2006 16:58:42 -0700
Links: << >>  << T >>  << A >>
As I have a problem in asynchronous FIFO design.
My case is described as below,

I want to design a FIFO as write in clock VD domain, and read in clock
CP domain.
And there is a signal (VD domain) informs 32-bytes is completed write
to FIFO, then
can be read out in clock CP domain, and guarantee there is not any data
coming in
the read out phase.

The RTL code is below, It's passed in simulation phase. My problem is
can it
pass the synthesis phase? Will it have any issue? Thanks.

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// assume clk_cp = 50 Mhz, clk_vd = 30 Mhz.
// input data and enable
input       datain_en; // based on clk_vd, high active
input [7:0] datain;    // based on clk_vd;

// assuming write 32 bytes data, will send a completed packet_end
signal
// for informing we can read out in clk_cp clock domain. And make sure
// there is not any datain_en coming in the read out phase.
input pkt_end;  // based on clk_vd;

output dataout_valid;
output [7:0]  dataout;

reg [4:0]  wptr;    // based on clk_vd
reg [4:0]  rptr;    // based on clk_cp
reg [7:0]  mem [4:0];
always @(negedge vd_rst_n or posedge clk_vd)
begin
    if(~vd_rst_n) begin
        wptr <=5'b0;
    end else begin
        if(datain_en) begin
           mem[wptr] <= datain;
           wptr      <= wptr + 1;
        end
    end
end

// assume clk_cp = 50 Mhz, clk_vd = 30 Mhz.
// avoid the metastable
reg [3:0] pkt_end_cp;
always @(negedge cp_rst_n or posedge clk_cp)
begin
    if(~cp_rst_n) begin
        pkt_end_cp <= 4'b0;
    end else begin
        pkt_end_cp <= { pkt_end_cp[2:0], pkt_end};
    end
end

wire pkt_end_cp_en = ~pkt_end_cp[3] & pkt_end_cp[2] ;

reg dataout_valid;
reg [4:0] data_vld_cnt;
always @(negedge cp_rst_n or posedge clk_cp)
begin
    if(~cp_rst_n) begin
        dataout_valid <= 1'b0;
    end else begin
        if (dataout_valid && data_vld_cnt==5'd31)
           dataout_valid <= 1'b0;
        else if(pkt_end_cp_en)
           dataout_valid <= 1'b1;
    end
end

always @(negedge cp_rst_n or posedge clk_cp)
begin
    if(~cp_rst_n) begin
        data_vld_cnt  <= 5'b0;
    end else begin
        if (dataout_valid && data_vld_cnt==5'd31)
           data_vld_cnt  <= 5'b0;
        else if(dataout_valid)
           data_vld_cnt  <= data_vld_cnt + 1;
    end
end


always @(negedge cp_rst_n or posedge clk_cp)
begin
    if(~cp_rst_n) begin
        rptr <=5'b0;
    end else begin
        if(dataout_valid) begin
           rptr      <= rptr + 1;
        end
    end
end

assign dataout = mem[rptr];

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


Article: 100429
Subject: Re: asynchronous FIFO design
From: "Peter Alfke" <peter@xilinx.com>
Date: 8 Apr 2006 19:29:54 -0700
Links: << >>  << T >>  << A >>
Basically, your design is very simple. You just use one BlockRAM port
to write with one clock, and the other port to read using the other
clock.

The devil is in the handshaking logic, where you must send a signal
from one clock domain to the other, and back.
Concentrate on this handshake signal. The rest is trivial.
Peter Alfke


Article: 100430
Subject: Re: shared BRAM between PPC and FPGA fabric
From: "MM" <mbmsv@yahoo.com>
Date: Sat, 8 Apr 2006 23:52:35 -0400
Links: << >>  << T >>  << A >>
Amit,

All you have to do is to declare the pins related to the other port
external. I am assuming that your top-level design is in ISE and your EDK
susbsytem is an instantiation in the top-level design.

/Mikhail


"amit" <amitshukla1979@gmail.com> wrote in message
news:1144410286.775287.66600@i39g2000cwa.googlegroups.com...
> Hi
>
> I am trying to implement a shared memory interface between PPC and FPGA
> fabric. I am using EDK to create a dual port RAM and connect it to a
> DSOCM controller. I have been able to write to BlockRAM from my
> application code.
> My question is that how do I connect the other port of the BRAM to my
> FPGA design?
> Should the HDL module be added as a core from the " import peripheral"
> utility?
> If so, then which bus should it connect to?
>
> Thanks
> Amit
>



Article: 100431
Subject: Re: Help needed
From: "motty" <mottoblatto@yahoo.com>
Date: 8 Apr 2006 21:14:36 -0700
Links: << >>  << T >>  << A >>
There is documentation in the EDK installation directory...specifically
how to create user IP cores and how to connect them to the OPB bus.
The wrapper files that instatiate the OPB logic are the key.  You have
to instatiate your core in one of those (user_logic.v or vhdl) and
create ports that connect to your IP instantiation.  When you make the
port connections to your instantiated core, you can either specify one
of the external ports you have declared in the user_logic or you can
specify a slave register bitfield.  The external ports are mapped into
the upper level wrapper file (vhdl) and you must specify them in the
mpd file.  Once you do this, those ports are available in the EDK
whenever you pull in your core.

It's not trivial, but it will make sense once you do it a couple times.
 Then you can use software to write to the slave register for your core
and connect the external signals however you want to...even bring them
out to the FPGA pins if needed.

Hope that makes some sense.


Article: 100432
Subject: Re: Testing sample Aurora design on ML321 board
From: "MM" <mbmsv@yahoo.com>
Date: Sun, 9 Apr 2006 00:28:46 -0400
Links: << >>  << T >>  << A >>
"Duane Clark" <junkmail@junkmail.com> wrote in message
news:79yXf.50473$2O6.6875@newssvr12.news.prodigy.com...
> billu wrote:
> >
> > I'm trying to download the design onto the board using IMPACT. All the
> > processes (Program, Get Device ID, Read Status Register.. ) seem to
> > work except the Verify process. Is that something that I should be
> > concerned about.Can I assume that design has been uploaded to the
> > board, once I run program, and it says program successful?
>
> I would say, yes you should be concerned if the verify doesn't work. But
> if the board seems to be running okay... ?

For verify to work you need to configure bitgen to generate an extra file
with bit masks. It is not generated by default.

/Mikhail



Article: 100433
Subject: decoding
From: "shereen.ahmed" <shereen.ahmed@gmail.com>
Date: 8 Apr 2006 23:07:46 -0700
Links: << >>  << T >>  << A >>
Dear  all


Can any one help me to understand  LDPC code


1) If LDPC code decode using viterbi algorithm and sum product
algorithm , which one will be  performance better ?


2) What are the different decoding algorithms for LDPC ?


3) What is the advantage of itterative decoding  over non itterative ?


4) Why the sum product algorithm is the best decoding algorithm  for
LDPC ? 


thanks


Article: 100434
Subject: Re: C-Compiler for free VHDL controller core ?
From: Tommy Thorn <foobar@nowhere.void>
Date: Sat, 08 Apr 2006 23:13:25 -0700
Links: << >>  << T >>  << A >>
Isaac Bosompem wrote:
> Maybe an OpenRISC?
> 
> They have a GCC port for the chip on freecores.org, though the simplest
> config on my XC3S200 would use up ~75% of it!

That's an option that should work.  The OP mentioned a microcontroller, 
so that case I'd expect an AVR clone would be good enough (I think I've 
seen them around but regardless it would not be hard to reproduce).  GCC 
supports AVR quick nicely.

Another all time favorite is MIPS for which GCC have had well tested 
support for quite a while.

The best alternative however is likely the microblaze clone aeMB which 
is a better fit for FPGAs and has good GCC support.  However, license 
issues aren't not entirely clear, but for non-commercial use I wouldn't 
worry.

There.  I'm sure there are other excellent choices.  No, ARM is not one 
of them :-)

Tommy

Article: 100435
Subject: Re: C-Compiler for free VHDL controller core ?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 9 Apr 2006 02:11:21 -0700
Links: << >>  << T >>  << A >>
choices
* Pico(Paco)Blaze
* AVR
* C16 from opencores
* aeMB is not fully compliant as MicroBlaze i have tested with assembly
programs but some commands are wrong, so its not ready for c compiler

if you have S400 or larger than you can use some 32 bit cores, in S200
it is getting very tight with 32 bit processors (commercial MicroBlaze
is ok in S200)

if you are looking to have full normal GCC support the there are no so
many options :(
LEON3 smallest system fits s400

Antti


Article: 100436
Subject: Re: C-Compiler for free VHDL controller core ?
From: burn.sir@gmail.com
Date: 9 Apr 2006 03:45:08 -0700
Links: << >>  << T >>  << A >>
The gr16/32 CPUs are very old and designed in Verilog, but you might
still find them useful.

I think Jan Gray ported LCC to the architecture and also had a complete
SoC example with UART and everything.



Speaking of aaMB, did they actaully looked if it FITS into an apa150
when they wrote the docs??


Article: 100437
Subject: Re: Virtex-4 RocketIO and G.709 OTU-2
From: Allan Herriman <allanherriman@hotmail.com>
Date: Mon, 10 Apr 2006 00:31:57 +1000
Links: << >>  << T >>  << A >>
On Fri, 07 Apr 2006 16:50:08 +0200, Gerhard Hoffmann
<dk4xp@freenet.de> wrote:

>On Wed, 22 Mar 2006 12:00:26 +1100, Allan Herriman <allanherriman@hotmail.com> wrote:
>
>>On 21 Mar 2006 09:08:21 -0800, "Alain" <no_spa2005@yahoo.fr> wrote:
>>
>>>Unfortunately, even OC-192 is excluded form Virtex- 4 (ug076.pdf :
>>>"Payload compatible only"), so no hope for OTU-2 I think.
>>>We have to wait Virtex-5 family ?
>>
>>No.  That is unlikely to have sufficient jitter performance, due to
>>certain compromises that must be made when putting an MGT on an FPGA.
>>In particular, it's likely to use a ring oscillator rather than an LC
>>oscillator which would have better perfomance.
>
>Is jitter the only limitation? Most fiber optic transceivers (XFP & friends)
>have eye openers of their own and resynchronize everything anyway.

An XFP will have a JTF bandwidth in the order of 1MHz.  A SERDES will
have a JTF bandwidth of 1-2 orders of magnitude less than that, so
resynchronisation in the XFP doesn't solve all the jitter problems.

Regards,
Allan

Article: 100438
Subject: Re: DDR SDRAM Controller
From: "ada" <annedorianashley@googlemail.com>
Date: Sun, 09 Apr 2006 11:18:29 -0500
Links: << >>  << T >>  << A >>
Hi all,
 could someone give me a tip about using DCMs?

I have seen many different memory interface clocking schemes but
unfortunately I did not find any explanation related to a general scheme
just different examples. Could someone explain it to me? I'd like to know
in which case which scheme I should use. 

I think I really have a clock synchronization problems but I can not check
it because I do not have an osci.  
I have 2 memory feedback clocks (feedback output and feedback input) -
clk_ddr_fb_out and clk_ddr_fb_in correspondingly. So clk_ddr_fb_out is
connected to ddr_clk and driven into the memory and clk_ddr_fb_in is
driven from the memory to my design. In my design two separate DCMs are
being used, one internal DCM for the memory controller design inside the
FPGA and the other external DCM to forward clocks to the external memory
device. Look at this picture. 
http://img115.imageshack.us/img115/6523/dcms1pv.jpg

But in this case DCM1 does not lock:( Am I doing something wrong? Any
ideas?

Article: 100439
Subject: Re: C-Compiler for free VHDL controller core ?
From: Peter Winkler <idontwant@totell.com>
Date: Sun, 09 Apr 2006 18:41:20 +0200
Links: << >>  << T >>  << A >>
Thanks for your suggestions ! I think I will have a look at these two:

>* Pico(Paco)Blaze
>* AVR

I very much like AVR controllers, so maybe it is a good idea to
look at this core. And there is also WinAVR. I hope I can get
it to run on my XC3S200. 

Don't you think it is somewhat strange, that there are so few
options for a soft prozessor for hobby stuff ? Is it so much work
to design a soft core ? Not sure, but looking at the AVR core
from opencores, it seems development was stopped in 2003
and only a limited number of I/O lines are available. However,
 I am very glad that it exists at all ... ;)

P.

Article: 100440
Subject: Re: C-Compiler for free VHDL controller core ?
From: "Antti Lukats" <antti@openchip.org>
Date: Sun, 9 Apr 2006 18:42:16 +0200
Links: << >>  << T >>  << A >>

<burn.sir@gmail.com> schrieb im Newsbeitrag 
news:1144579508.239684.10820@e56g2000cwe.googlegroups.com...
> The gr16/32 CPUs are very old and designed in Verilog, but you might
> still find them useful.
>
> I think Jan Gray ported LCC to the architecture and also had a complete
> SoC example with UART and everything.
>
>
>
> Speaking of aaMB, did they actaully looked if it FITS into an apa150
> when they wrote the docs??
>
you mean "aeMB" ?
the original author did very little testing and the core is not full,
it does do lots of instructions ok, but I think it messes up with delay 
slots and link register
I think it should fit into APA150 but I havent run that synthesis

but just out curiosity i peeked into my trashbox and did run synthesis of 
NIOS-II clone for Lattice XP3:
605 slices - 39% :)
hum maybe I should continue the work on that

Antti



Article: 100441
Subject: Re: C-Compiler for free VHDL controller core ?
From: "Antti Lukats" <antti@openchip.org>
Date: Sun, 9 Apr 2006 18:46:53 +0200
Links: << >>  << T >>  << A >>
"Peter Winkler" <idontwant@totell.com> schrieb im Newsbeitrag 
news:1ndi32lhgriblsukneeh81cifdf8gnqac2@4ax.com...
> Thanks for your suggestions ! I think I will have a look at these two:
>
>>* Pico(Paco)Blaze
>>* AVR
>
> I very much like AVR controllers, so maybe it is a good idea to
> look at this core. And there is also WinAVR. I hope I can get
> it to run on my XC3S200.
>
> Don't you think it is somewhat strange, that there are so few
> options for a soft prozessor for hobby stuff ? Is it so much work
> to design a soft core ? Not sure, but looking at the AVR core
> from opencores, it seems development was stopped in 2003
> and only a limited number of I/O lines are available. However,
> I am very glad that it exists at all ... ;)
>
> P.

it does exist and does work
I have done some work with it
1) I think i had made verilog version of it
2) tried to use better io peripheral bus system that would be configurable
3) one time had it integrated into Xilinx EDK !
4) I have a special toplevel that works as Atmel appnote AVR910 compatible 
programmer

in the opencores version there is base address of one port wrong
and yes the development is pretty much stopped

an no its not hard to write a processor ip-core not at all
but having full infra-structure, peripheral bus and compiler support, and 
debuf support
is what makes it more complex task

Antti 



Article: 100442
Subject: Re: C-Compiler for free VHDL controller core ?
From: Peter Winkler <idontwant@totell.com>
Date: Sun, 09 Apr 2006 18:50:45 +0200
Links: << >>  << T >>  << A >>
On 8 Apr 2006 16:10:26 -0700, "Isaac Bosompem" <x86asm@gmail.com>
wrote:

>Maybe an OpenRISC?
>
>They have a GCC port for the chip on freecores.org, though the simplest
>config on my XC3S200 would use up ~75% of it!
>
>-Isaac

That may be a little bit too large for me :)


Article: 100443
Subject: Re: Compiler to FPSLIC
From: Niels Sandmann <usenet.s@ndmann.dk>
Date: Sun, 09 Apr 2006 21:56:51 +0200
Links: << >>  << T >>  << A >>
Adam Megacz wrote:
> I'm curious: why have you chosen Atmel's FPSLIC?
Because I thought the integration af af Microncontroller and FPGA would 
be handy, and ease communication between the program and the FPGA.

I have prior experience with microcontrollers with Atmels AVR-core, and 
I have been pleased with them. Also, they are reasonable cheap.

Regards,
Niels Sandmann

Article: 100444
Subject: Re: Compiler to FPSLIC
From: Niels Sandmann <usenet.s@ndmann.dk>
Date: Sun, 09 Apr 2006 22:46:22 +0200
Links: << >>  << T >>  << A >>
Ralf Hildebrandt wrote:
> Remember, that transferring operators to special purpose computing 
> blocks takes some time. The gain of speed with the function block must 
> be big enough to make it worth.
Of course. It would be necessary with a good profiler.

> Mapping a software algorithm to FPGAs is possible with languages like 
> SystemC.
That sounds interesting. At first sight it seems to target simulation of 
system more than actual implementation, but I might be wrong.

> I am not an expert in this area. I just want to give you some words, 
> where your search may start.
I'm glad for any input and ideas I can get.

Regards
Niels Sandmann

Article: 100445
Subject: Re: Compiler to FPSLIC
From: Niels Sandmann <usenet.s@ndmann.dk>
Date: Sun, 09 Apr 2006 23:13:03 +0200
Links: << >>  << T >>  << A >>
Jim Granville wrote:

> depends a lot on the FPGA, and the project, ( and the designer..)
>  [ It is also a dangerous tool in the wrong hands....]
why ?

> Someone has mentioned Altera's new C flow ( not cheap )

> 
> 
> For good examples of FPGA centric work on other languages, look at
> 
> http://www.jopdesign.com/
> 
> http://myhdl.jandecaluwe.com/doku.php/cookbook:intro
> 
> 
> and for an example of a smaller FPGA-Core, and what can be done
> in core-extension, look at this carefully before commiting to the
> FpSLIC ( which is rather a dead-end pathway ).
> 
> http://bleyer.org/pacoblaze/
> 
> A google on Python AVR ( if you MUST use the FpSLIC )
> finds quite a lot, including
> 
> http://savannah.nongnu.org/patch/?func=detailitem&item_id=3763
> 
> http://www.ecs.soton.ac.uk/~jb1403/projects/avrpy/
> 
> 
> -jg
> 
> 

Article: 100446
Subject: Re: Compiler to FPSLIC
From: Niels Sandmann <usenet.s@ndmann.dk>
Date: Sun, 09 Apr 2006 23:50:39 +0200
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> Niels Sandmann wrote:
>> Hi everyone,
>>
>> I'm considering making a compiler for Atmels FPSLIC (combined 
>> microcontroller with FPGA). The idea is to mark expensive funktions, so
>> they can be implemented in the FPGA instead of normal machine code. 
> 
> Sometimes an 'expensive' item might be an operator.
> ie Maths libraries, and their support is one productive area that
> does not need armloads of new software.
> 
>  > I have experience with microcontrollers and construction of 
> compilers, but
>> I have only made very small test-projects with a very old FPGA and 
>> really buggy software.
>>
>> Is this possible to make such a compiler?
> 
> almost anything is possible ...
> 
>> Does it make sense at all to compile high-level language to a FPGA in 
>> this way?
> 
> depends a lot on the FPGA, and the project, ( and the designer..)
>  [ It is also a dangerous tool in the wrong hands....]
why ?

>> Has someone else made it/is this normal procedure today ?
> 
> Someone has mentioned Altera's new C flow ( not cheap )
Do you mean their C2H-compiler for the Nios II as Mike Teseler mentioned 
in another post ?

> For good examples of FPGA centric work on other languages, look at
<snip links>
They are interesting but not exactly what I'm looking for.

> and for an example of a smaller FPGA-Core, and what can be done
> in core-extension, look at this carefully before commiting to the
> FpSLIC ( which is rather a dead-end pathway ).
I'm not committed to the FpSLIC in any way. It was just chosen due to my 
prior experience with AVR.


Article: 100447
Subject: Re: Compiler to FPSLIC
From: Niels Sandmann <usenet.s@ndmann.dk>
Date: Sun, 09 Apr 2006 23:52:32 +0200
Links: << >>  << T >>  << A >>
Mike Treseler wrote:
> Niels Sandmann wrote:
> 
>> Is this possible to make such a compiler?
> 
> There's one for nios:
> http://www.altera.com/literature/wp/C2H_Compiler_FAQ.pdf
That is exactly what I'm looking for. It proofs that it can be done, so 
I'll look further in to it. Thanks.

Best regards
Niels Sandmann

Article: 100448
Subject: Re: Compiler to FPSLIC
From: Niels Sandmann <usenet.s@ndmann.dk>
Date: Mon, 10 Apr 2006 00:09:13 +0200
Links: << >>  << T >>  << A >>
Tim Wescott wrote:
> Niels Sandmann wrote:
>> Hi everyone,
>>
>> I'm considering making a compiler for Atmels FPSLIC (combined 
>> microcontroller with FPGA). The idea is to mark expensive funktions, so
>> they can be implemented in the FPGA instead of normal machine code. I 
>> have experience with microcontrollers and construction of compilers, 
>> but I have only made very small test-projects with a very old FPGA and 
>> really buggy software.
>>
>> Is this possible to make such a compiler?
>> Does it make sense at all to compile high-level language to a FPGA in 
>> this way?
>> Has someone else made it/is this normal procedure today ?
>>
>> Regards,
>> Niels Sandmann
> 
> Boy, that would be interesting.  There may be part of a doctorate in 
> there if you work it right.
Actually it is supposed to be a part of my master thesis. As the link 
Mike Treseler gave it can be done, so I don't think it is that 
revolutionary.

> I think this is possible.  I think the shortest road to success in the 
> confines of one file would be to make a preprocessor that would extract 
> the FPGA stuff to a C language design file which would then go to one of 
> those nifty new C language synthesis tools.
But it wouldn't be as elegant as an integrated solution.

> I suspect, though, that this would cause problems with concurrency. 
Perhaps. I still don't know which language I will use. Probably I'll 
design my own pascal-like language. So I could design the language to 
take care of these problems.

Best regards
Niels Sandmann

Article: 100449
Subject: Re: Compiler to FPSLIC
From: Tim Wescott <tim@seemywebsite.com>
Date: Sun, 09 Apr 2006 15:45:12 -0700
Links: << >>  << T >>  << A >>
Niels Sandmann wrote:

> Tim Wescott wrote:
> 
>> Niels Sandmann wrote:
>>
>>> Hi everyone,
>>>
>>> I'm considering making a compiler for Atmels FPSLIC (combined 
>>> microcontroller with FPGA). The idea is to mark expensive funktions, so
>>> they can be implemented in the FPGA instead of normal machine code. I 
>>> have experience with microcontrollers and construction of compilers, 
>>> but I have only made very small test-projects with a very old FPGA 
>>> and really buggy software.
>>>
>>> Is this possible to make such a compiler?
>>> Does it make sense at all to compile high-level language to a FPGA in 
>>> this way?
>>> Has someone else made it/is this normal procedure today ?
>>>
>>> Regards,
>>> Niels Sandmann
>>
>>
>> Boy, that would be interesting.  There may be part of a doctorate in 
>> there if you work it right.
> 
> Actually it is supposed to be a part of my master thesis. As the link 
> Mike Treseler gave it can be done, so I don't think it is that 
> revolutionary.
> 
>> I think this is possible.  I think the shortest road to success in the 
>> confines of one file would be to make a preprocessor that would 
>> extract the FPGA stuff to a C language design file which would then go 
>> to one of those nifty new C language synthesis tools.
> 
> But it wouldn't be as elegant as an integrated solution.
> 
>> I suspect, though, that this would cause problems with concurrency. 
> 
> Perhaps. I still don't know which language I will use. Probably I'll 
> design my own pascal-like language. So I could design the language to 
> take care of these problems.
> 
> Best regards
> Niels Sandmann

If you're going to go as far as looking into different languages then 
look into Occam.  I haven't had to use it, but as prior art goes it is 
Not To Be Ignored.  Perhaps noted and neglected, but not _ignored_.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/



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