Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, During synthesis, with Xilinx ISE 8.2 it seems it cannot find the library file I used: ERROR:HDLParsers:3317 - "..." Line 43. Library SPARTAN3E cannot be found. ERROR:HDLParsers:3013 - "..." Line 44. Library SPARTAN3E is not declared. I used the following line in my code: library SPARTAN3E; use SPARTAN3E.vcomponents.all; The library is found on my computer since I can simulate with it (Using Active HDL). The question is how do I point ISE to it. Thanks AmishArticle: 109651
>on LM32 all memories are on Wishbone bus making the access to BRAM >based memory block slower than the access to external memory (assuming >cache hit). Can you cheat and build a system with cache and no memory, then preload the cache with the data you want? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 109652
Before I get spamed for this I have done a search and I see there are references to what I'm looking for on www.opencores.org but for some reason I'm unable to connect. What I'm looking for is a resource like, if it existed, Numerical Receipes in HDL (VHDL/Verilog). I have a need for the basic floating point functions like sin( a ) and x ** y. For floating point numbers that are only 12 to 18 bits I can use lookup tables but I was wondering if there was another way of calculating these values. Most of the books I have cover addition/subtraction, multiplication and division but nothing more advance or even hints at how to go about it. >From sin( a ) and x ** y I plan on deriving cos( a ), tan( a ), cot( a ), and yth root of x. I'm looking for any helpful or constructive suggestions. Thanks, DerekArticle: 109653
"Hal Murray" <hmurray@suespammers.org> schrieb im Newsbeitrag news:F4idnX0B6paUobzYnZ2dnUVZ_vSdnZ2d@megapath.net... > >>on LM32 all memories are on Wishbone bus making the access to BRAM >>based memory block slower than the access to external memory (assuming >>cache hit). > > Can you cheat and build a system with cache and no memory, then > preload the cache with the data you want? > > -- not sure, this approuch works nicely for Virtex PPC caches, but for LM32 guess it needs deep look into the RTL code to see if it is possible option or not. currently I disabled the caches while the use some function in an way that is not supported by ISE (and I was too lazy-busy to fix it), and actually I wantes to have resource useage numbers for minimal setup (eg no cache system) anyway adding direct memory is of course possible as all RTL is available (and supposedly has at least partial support there) but lets see if there will be some updates to the LM32 release AnttiArticle: 109654
Hal Murray wrote: > >on LM32 all memories are on Wishbone bus making the access to BRAM > >based memory block slower than the access to external memory (assuming > >cache hit). > > Can you cheat and build a system with cache and no memory, then > preload the cache with the data you want? As far as I can see, I don't think this is supported via the GUI yet, but would of course be possible if you hacked the RTL to change the cache memories and tags to be initialised with the correct data, which should be fairly straightforward to do. However, this would not be as efficient as using the instruction ROM and data RAM that are in the RTL, as you end up wasting resources on memories for the cache tag RAMs which aren't needed, and all of the cache refill logic etc.. Cheers, JonArticle: 109655
I had similar issues with opencores until now. It is working now. Derek Simmons wrote: > Before I get spamed for this I have done a search and I see there are > references to what I'm looking for on www.opencores.org but for some > reason I'm unable to connect. > > What I'm looking for is a resource like, if it existed, Numerical > Receipes in HDL (VHDL/Verilog). I have a need for the basic floating > point functions like sin( a ) and x ** y. For floating point numbers > that are only 12 to 18 bits I can use lookup tables but I was wondering > if there was another way of calculating these values. Most of the books > I have cover addition/subtraction, multiplication and division but > nothing more advance or even hints at how to go about it. > > >From sin( a ) and x ** y I plan on deriving cos( a ), tan( a ), cot( a > ), and yth root of x. > > I'm looking for any helpful or constructive suggestions. > > Thanks, > DerekArticle: 109656
for integer implementations the cordic algorithm covers most of the
trigonometric functions
you need (no multipliers, but some latency)
Aurash
Derek Simmons wrote:
>Before I get spamed for this I have done a search and I see there are
>references to what I'm looking for on www.opencores.org but for some
>reason I'm unable to connect.
>
>What I'm looking for is a resource like, if it existed, Numerical
>Receipes in HDL (VHDL/Verilog). I have a need for the basic floating
>point functions like sin( a ) and x ** y. For floating point numbers
>that are only 12 to 18 bits I can use lookup tables but I was wondering
>if there was another way of calculating these values. Most of the books
>I have cover addition/subtraction, multiplication and division but
>nothing more advance or even hints at how to go about it.
>
>>From sin( a ) and x ** y I plan on deriving cos( a ), tan( a ), cot( a
>), and yth root of x.
>
>I'm looking for any helpful or constructive suggestions.
>
>Thanks,
>Derek
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 109657The declaration was missing pre EDK 8.2i releases. It was added in EDK 8.2i and is available in "xmk.h". You can modify the Xilkernel TCL file (procedures generate, execs_generate or post_generate) and add in a string or a integer declaration which passes in the version info into a header file (say os_config.h). Refer to the Embedded Systems Tool Reference Manual to figure out how to modify MLD/TCL files using a custom copy of an EDK library. Vasanth "Bernhard Sputh" <sputhnic@yahoo.de> wrote in message news:4oa3ueFcq1gaU1@individual.net... > Hi group, > > I'm currently developing a Communicating Sequential Processes library for > the Xilinx Micro Kernel (XMK). I recently went and used the compiler flags > -Wall and -Werror to let the compiler detect any potential problems. So > far everything works out fine, except that now the compiler complains > about an implicit declaration of the function: `xilkernel_main()'. I > searched through the include files for the corresponding MicroBlaze core > without finding any declaration for it. Does anybody out there know where > this function is declared? > > Another problem I have run into is to detect which version of XMK my code > is currently being compiled with. Any idea how I could acquire this > information during compile time? > > > Cheers > Bernhard > > -- > William of Ockham, Albert Einstein, and Stephen Hawking walk into a bar. > Bartender: Oh, NO! Not another bloody parallel programming joke.Article: 109658
If www.opencores.org link does not work, try http://www.opencores.org:8080/ cbr_929rr wrote: > I had similar issues with opencores until now. It is working now. > > Derek Simmons wrote: > > Before I get spamed for this I have done a search and I see there are > > references to what I'm looking for on www.opencores.org but for some > > reason I'm unable to connect. > > > > What I'm looking for is a resource like, if it existed, Numerical > > Receipes in HDL (VHDL/Verilog). I have a need for the basic floating > > point functions like sin( a ) and x ** y. For floating point numbers > > that are only 12 to 18 bits I can use lookup tables but I was wondering > > if there was another way of calculating these values. Most of the books > > I have cover addition/subtraction, multiplication and division but > > nothing more advance or even hints at how to go about it. > > > > >From sin( a ) and x ** y I plan on deriving cos( a ), tan( a ), cot( a > > ), and yth root of x. > > > > I'm looking for any helpful or constructive suggestions. > > > > Thanks, > > DerekArticle: 109659
Hi Derek, Derek Simmons wrote: > I'm looking for any helpful or constructive suggestions. You might have a look at the cordic algorithms. Regards, Norbert StuhrmannArticle: 109660
hi IO has been the thoughts of late. As all IO is from or to 1K x 16 bit words memory mapped buffers certain limits are placed on the devices My current plans are PAL 1024 character display using 1 buffer, but would need a character ROM, or character bit map page. ascII 256 could be fitted into 1K x 16 bits as an 8 by 8 font, allowing five of the extra 16 bits in the character index to select a buffer page then 3 bits are left for character representing modifications i.e. eight colours. A UART working at MIDI data rate for musical applications, along with translation software to provide an instrument control buffer i.e. easy variables for control wheel signals automatically modified by data stream. A DAC 8 times oversampling delta sigma converter.again for musical applications which does 1K x16 bit buffer DMA output. A minimal extra parts needed ADC based on the DAC with fixed size buffer DMA. A bit reversal load store memory cell for FFT indexing. which may be extended to do auto FFT and programable hardware biquad chains. A USB controller/ slave mode too. A display and keypad scan multiplex controller. A data compression codec. what else would people require in terms of modular cores? cheers.Article: 109661
In short, the answer is no. RAW API mode does not require any kernel services. The sockets mode is implemented using kernel features and hence you need xilkernel when using Sockets mode. Sathya u_stadler@yahoo.de wrote: > hi > > thanks for the answer. i did look at those pdfs and initialised the raw > mode according to the manual. still the sys_thread_new function dosen't > work. can't i use raw mode with the xilkernel?Article: 109662
Instead of editing the UCF manually open the constraints editor, or open the design in FPGA editor and you will be able to see the proper hierarchy and net names. Your clock probably iriginates in the ISE portion of the design where it is most likely called differently. The clocks are always constrained as close to the source as possible. /Mikhail "Steve" <sgfallows@gmail.com> wrote in message news:1159791657.009347.243040@m7g2000cwm.googlegroups.com... > I have a Xilinx EDK based design for a Virtex II Pro using the PowerPC > Processor. The PPC subsystem from EDK is a submodule of an ISE based > schematic design. There are about 7 cores around the PPC and all was > working fine. Then I added a second GPIO for some input lines and it > won't run at all anymore. > > So, I want to add some timing constraints for the clocks. However when > I do so ISE complains; I added these lines to the UCF file: > > NET "sys_clk_s" TNM_NET = "sys_clk_s"; > TIMESPEC "TS_sys_clk_s" = PERIOD "sys_clk_s" 10 ns HIGH 5; > > ISE says it can't find sys_clk_s in the design. > > So I tried these variations of the net name (PPD_DDR is the EDK project > name): > > PPC_DDR/sys_clk_s > PPC_DDR\sys_clk_s > > PPC_DDR_stub/sys_clk_s > PPC_DDR_stub\sys_clk_s > > all with the same result. > > How am I supposed to refer to a net in the EDK design in the ISE .ucf > file? >Article: 109663
Hi Vasanth, thank You for Your help. On Mon, 02 Oct 2006 09:57:03 -0700, Vasanth Asokan wrote: > The declaration was missing pre EDK 8.2i releases. It was added in EDK > 8.2i and is available in "xmk.h". OK, good to know so I don't bother with this warning any longer and will upgrade asap. > You can modify the Xilkernel TCL file (procedures generate, > execs_generate or post_generate) and add in a string or a integer > declaration which passes in the version info into a header file (say > os_config.h). Refer to the Embedded Systems Tool Reference Manual to > figure out how to modify MLD/TCL files using a custom copy of an EDK > library. OK, I will try that out. However, that requires that anyone wanting to use my library to do the same, not how I would wish it to be. Xilinx should add such a version string by default, IMHO. Cheers Bernhard -- William of Ockham, Albert Einstein, and Stephen Hawking walk into a bar. Bartender: Oh, NO! Not another bloody parallel programming joke.Article: 109664
hi Antti, unfortunately, that's one of the downsides to accepting comments instantly, without approval. you post a comment, it will be up on our blog right away! some people will spam. typepad isn't able to block all spam. we deleted that "adult" spam comment this morning, right when we saw it. please do not hesitate to add comments to our blog based on the actions of one spammer. http://latticeblogs.typepad.com/frontier/2006/09/soft_processor_.html#comments if we continue to have issues with spam, we will have to pre-"approve" all comments, but we aren't to that point yet! rgds, bart --------- Bart Borosky Manager, Online Marketing Lattice Semiconductor > Bart, > > please look at > > http://latticeblogs.typepad.com/frontier/2006/09/soft_processor_.html#comments > > its full of adult avertizing! > > I was about to post a comment there, but when I see that spam there... > brr! > > AnttiArticle: 109665
cbr_929rr wrote: > Hi, > I'm working on interfacing I2S audio and am new at doing this. Could > someone describe how I2S serial data (20-bit left justified format) is > converted to parallel format and the Channel status, Valid and Z bits > are generated. Any links to VHDL/Verilog code would also be of great > help. The very first result of a Google search for "I2S channel status" was: http://pd.pennnet.com/Articles/Article_Display.cfm?ARTICLE_ID=247465&p=21&cat=DESIG -aArticle: 109666
jacko schrieb: > hi > > IO has been the thoughts of late. As all IO is from or to 1K x 16 bit > words memory mapped buffers certain limits are placed on the devices [] > what else would people require in terms of modular cores? > > cheers. you are not doing the things in right order IMHO 1) Arch description 2) HDL testbench or fixture 3) toolchain + assembler compiler tests 4) onchip bus infrastructure only when the above is finalized then there the peripherals make sense, unless the cores is working verified and supported by tested software tools, the existance (or lack of) peripherals makes absolutly no difference. AnttiArticle: 109667
MM wrote: > Instead of editing the UCF manually open the constraints editor, or open the > design in FPGA editor and you will be able to see the proper hierarchy and > net names. Your clock probably iriginates in the ISE portion of the design > where it is most likely called differently. The clocks are always > constrained as close to the source as possible. Thanks for the reply. The clock I was thinking of constraining, is the PLB and OPB clock in the EDK design. It is generated by a DCM in the EDK design, multiplied up from 10 MHz to 100 MHz. Your answer made me realize I should put a (period) constraint on the 10 MHz clock. My question now is, will a constraint on a DCM input clock "propagate through" the DCM and create a period constraint on the generated clock(s)?Article: 109668
> >What I'm looking for is a resource like, if it existed, Numerical > >Receipes in HDL (VHDL/Verilog). Elementary Functions, Algorithms and Implementation by Jean-Michel Muller. No HDL code but the algorithms are there.Article: 109669
Derek Simmons wrote: > >From sin( a ) and x ** y I plan on deriving cos( a ), tan( a ), cot( a > ), and yth root of x. Integer exponents are pretty straightforward. It is a similar algorithm to multiplication (multiply by 2 and optionally add), but with higher order operations (square and optionally multiply). Integer roots are probably best done by something like Newton-Raphson. Arbitrary powers probably require computing logarithms first. One issue with that is that you can't compute them for negative numbers. If you just want integer roots, computing arbitrary powers probably isn't the best way to do it.Article: 109670
Antti wrote: > jacko schrieb: > > > hi > > > > IO has been the thoughts of late. As all IO is from or to 1K x 16 bit > > words memory mapped buffers certain limits are placed on the devices > [] > > what else would people require in terms of modular cores? > > > > cheers. > > you are not doing the things in right order IMHO > > 1) Arch description Read the ISA and look at the circuit this early in the project. > 2) HDL testbench or fixture this will be the FORTH ROM and a modified FORTH-83 test suite. > 3) toolchain + assembler compiler tests The operation of the base vocabularies will depend quite a lot on the utility to which the design will be put. > 4) onchip bus infrastructure it will be avalon or wishbone, when i end up needing to use the on chip bus for a first product development. > > only when the above is finalized then there the > peripherals make sense, unless the cores > is working verified and supported by tested > software tools, the existance (or lack of) > peripherals makes absolutly no difference. i like to see where i'm headed, as well as where i am due to the direction to head in is controlled by the final destination. the pheripheral IO is on the agenda at the moment as this will decide the high level structure of the API. I could do things to an order, but i see no pink slips paying the bills, so i'll have to run it the way i see it in the eye of the mind. i was thinking of a track loop phosphorus-arsnic NMR factorizer by gussian sum, but not now, but it may relate to the HAL generics. cheers > AnttiArticle: 109671
To answer my own question: yes. Looking at the Timing Report it is obvious that timing constraints were generated for the DCM output clocks. Steve wrote: > MM wrote: > > Instead of editing the UCF manually open the constraints editor, or open the > > design in FPGA editor and you will be able to see the proper hierarchy and > > net names. Your clock probably iriginates in the ISE portion of the design > > where it is most likely called differently. The clocks are always > > constrained as close to the source as possible. > > Thanks for the reply. The clock I was thinking of constraining, is the > PLB and OPB clock in the EDK design. It is generated by a DCM in the > EDK design, multiplied up from 10 MHz to 100 MHz. Your answer made me > realize I should put a (period) constraint on the 10 MHz clock. > > My question now is, will a constraint on a DCM input clock "propagate > through" the DCM and create a period constraint on the generated > clock(s)?Article: 109672
Derek Simmons wrote: > Before I get spamed for this I have done a search and I see there are > references to what I'm looking for on www.opencores.org but for some > reason I'm unable to connect. > > What I'm looking for is a resource like, if it existed, Numerical > Receipes in HDL (VHDL/Verilog). I have a need for the basic floating > point functions like sin( a ) and x ** y. For floating point numbers > that are only 12 to 18 bits I can use lookup tables but I was wondering > if there was another way of calculating these values. Most of the books > I have cover addition/subtraction, multiplication and division but > nothing more advance or even hints at how to go about it. > >>From sin( a ) and x ** y I plan on deriving cos( a ), tan( a ), cot( a > ), and yth root of x. > > I'm looking for any helpful or constructive suggestions. > > Thanks, > Derek > It really depends on your precision and accuracy requirements. For arbitrarily high precision, CORDIC is the way to go for sin provided you can live with the latency. The other end of the spectrum is a look-up table. There are intermediate solutions which are generally a combination of angular reductions and interpolation that will get you a reasonably high resolution without a huge look-up table. Linear interpolation perhaps the easiest, and can be done with relatively little hardware. A parabolic fit interpolation will get you considerably smaller errors between table entries allowing a finer resolution, and can be done with relatively low hardware complexity. For X**Y, it is easiest to work with normalized floating point as an input, and then using interpolated LUTs. Normalizing limits the range of the tables. For a general purpose trancendental function calculator, your best bet might be a CORDIC-like iterative engine, as CORDIC and CORDIC-like structures can handle trig, hyperbolic trig, logs and exponents, and multiply and divide. So the point is, that there are many ways to skin this cat, and the "best" way depends heavily upon your particular requirements.Article: 109673
Ray Andraka wrote: By the way, I have a paper on CORDIC on my web site that many have found ot be quite useful. Http://www.andraka.com/papers see: A survey of CORDIC algorithms for FPGA based Computers. I also second the reference to Jean Muller's book elementary functions book for algorithms, although you may have difficulty translating it into hardware.Article: 109674
Ray, In case your company uses Synopsys tools, there is a very simple solution available in their DesignWare library. They have both hardware as well as simulation models for both the above functions, which can be simply instantiated in the code. If you are not looking for any specific algorithm that implements the functions (and if you have access to the library) then this could be the right solution. -Sourabh Disclaimer: This is not push anyone's marketing agenda; just information about a solution for the given problem.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z