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Messages from 109925

Article: 109925
Subject: Re: Spartan3A - internal flash configuration or not?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 8 Oct 2006 06:18:29 -0700
Links: << >>  << T >>  << A >>
Nico Coesel wrote:
> "Antti" <Antti.Lukats@xilant.com> wrote:
>
> >hi
[snip]
> Got any links where there is more information? An S3 with internal
> flash + copy protection is something I could use in a design which
> needs some work on the PCB anyway...
>
> --
> Reply to nico@nctdevpuntnl (punt=.)
> Bedrijven en winkels vindt U op www.adresboekje.nl

sorry - no links, nothing confirmative :(

just thinking about why? and piece of unverified gossip.

Well we have to wait. If there is no flash in Spartan-3A
then it really makes me wonder why make it at all?

Is it really only because additional power saving modes?
sound unlikely, but you never know what consideration
are driving the Spartan-3A development.

hmm, it has ICAP added, so this maybe used to access
the internal flash, no extra interface needed.

Antti
www.microfpga.com


Article: 109926
Subject: Enterpoint PCI Core
From: "John Adair" <g1@enterpoint.co.uk>
Date: 8 Oct 2006 06:48:53 -0700
Links: << >>  << T >>  << A >>
Finally some details now on our website for those asking about the
core. We have delayed the release to maximise the inital stability to
customers so apologies for the time to those waiting for us to release
it. We have been very busy on customer driven projects and our
recruitment drive simply can't keep up.

We have  been doing a fair bit of work ourselves with the core and it
is looking very good in some real applications and over a wide range of
host machines and environmental conditions.

We have build in the capability for the core to act as full hosting
bridge for microprocessors and I expect a development board to appear
in our product ranges in the coming months to take advantage of that
functionality.

Further documentation should be put in place over the next few weeks.
For now the website is the best source of information that we are
putting into the public domain. Any relevant questions that come in to
our support email I will attempt to get answers posted to the FAQ page
for everyone to see.

Links to the core are now in place off most of the PCI board product
pages. The PCI-E core is mentioned in some of the web pages but don't
expect that to release until at least late Q4. We will be taking the
same approach and doing extensive testing on Broaddown4 and some of the
other PCI-E products that are coming before letting any customers near
the core. 

John Adair
Enterpoint Ltd.


Article: 109927
Subject: Re: Spartan 3 DCI
From: Austin Lesea <austin@xilinx.com>
Date: Sun, 08 Oct 2006 06:50:21 -0700
Links: << >>  << T >>  << A >>
yy wrote:

> Hi Austin,
>  ...but the datasheet tells that there should be no more than one DCI
> with Split termination on the same bank? i mean what should be the
> assignment of the pin that is LVDS but in the SSTL_II bank? should it
> assign it to SSTL_II_DCI instead?
> 
> 
> Ayon kay Austin Lesea:

yy:

I am confused.  LVDS_25_DCI is also split termination, one each on the + 
input, and the - input (two separate split terminations).

Each IOB has its own attribute.  The bank is not all of any type of IO.

The SSTL_II_DCI attribute will be one IO pin, and one IOB, and the 
LVDS_25_DCI attribute will use two IO pins, and one IOB...

Austin

Austin

Article: 109928
Subject: Re: Spartan 3 DCI
From: "yy" <yy7d6@yahoo.com.ph>
Date: 8 Oct 2006 09:01:21 -0700
Links: << >>  << T >>  << A >>
Hi Austin,

I'm confused too. Anyway here's what the Datasheet says:

"The rules guiding the use of DCI standards on banks are as
follows:
1. No more than one DCI I/O standard with a Single
Termination is allowed per bank.
2. No more than one DCI I/O standard with a Split
Termination is allowed per bank.
3. Single Termination, Split Termination, Controlled-
Impedance Driver, and Controlled-Impedance Driver
with Half Impedance can co-exist in the same bank."
-- Spartan 3 Datasheet

-yy

Ayon kay Austin Lesea:
> yy wrote:
>
> > Hi Austin,
> >  ...but the datasheet tells that there should be no more than one DCI
> > with Split termination on the same bank? i mean what should be the
> > assignment of the pin that is LVDS but in the SSTL_II bank? should it
> > assign it to SSTL_II_DCI instead?
> >
> >
> > Ayon kay Austin Lesea:
>
> yy:
>
> I am confused.  LVDS_25_DCI is also split termination, one each on the +
> input, and the - input (two separate split terminations).
>
> Each IOB has its own attribute.  The bank is not all of any type of IO.
>
> The SSTL_II_DCI attribute will be one IO pin, and one IOB, and the
> LVDS_25_DCI attribute will use two IO pins, and one IOB...
> 
> Austin
> 
> Austin


Article: 109929
Subject: Antifuse, lower cost?
From: scott moore <nospam@nowhere.com>
Date: Sun, 08 Oct 2006 09:37:44 -0700
Links: << >>  << T >>  << A >>
Does anyone have experience with antifuse fpgas? Are they lower cost
than static ram fpgas?

Thank you,

Scott Moore

Article: 109930
Subject: Re: Spartan 3 DCI
From: Austin Lesea <austin@xilinx.com>
Date: Sun, 08 Oct 2006 10:15:12 -0700
Links: << >>  << T >>  << A >>
I agree,

Those rules ARE confusing.

I will ask tomorrow am at work.  But I know from the way the IOB is 
designed, that the ONLY limitations are the Vcco has to be the same (for 
all standards in a bank), and the choice of DCI impedance (ie 50 ohms) 
will mean that all series terminated drivers in the back (eg LVDCI) will 
be 50 ohms, and all split terminated inputs (or outputs) will also be 50 
ohms (100 ohms to Vcco, 100 ohms to ground).

Once the referencve resistors are set in value, then the choices of 1/2, 
1, and 2X the reference impedance are fixed in actual value.

Perhaps the rules are implying that you can not have a 50 ohm, and a 68 
ohm reference DCI standard in the same bank?  This does make sense, as 
there is only one DCI controller per bank.

Austin

yy wrote:

> Hi Austin,
> 
> I'm confused too. Anyway here's what the Datasheet says:
> 
> "The rules guiding the use of DCI standards on banks are as
> follows:
> 1. No more than one DCI I/O standard with a Single
> Termination is allowed per bank.
> 2. No more than one DCI I/O standard with a Split
> Termination is allowed per bank.
> 3. Single Termination, Split Termination, Controlled-
> Impedance Driver, and Controlled-Impedance Driver
> with Half Impedance can co-exist in the same bank."
> -- Spartan 3 Datasheet
> 
> -yy
> 
> Ayon kay Austin Lesea:
> 
>>yy wrote:
>>
>>
>>>Hi Austin,
>>> ...but the datasheet tells that there should be no more than one DCI
>>>with Split termination on the same bank? i mean what should be the
>>>assignment of the pin that is LVDS but in the SSTL_II bank? should it
>>>assign it to SSTL_II_DCI instead?
>>>
>>>
>>>Ayon kay Austin Lesea:
>>
>>yy:
>>
>>I am confused.  LVDS_25_DCI is also split termination, one each on the +
>>input, and the - input (two separate split terminations).
>>
>>Each IOB has its own attribute.  The bank is not all of any type of IO.
>>
>>The SSTL_II_DCI attribute will be one IO pin, and one IOB, and the
>>LVDS_25_DCI attribute will use two IO pins, and one IOB...
>>
>>Austin
>>
>>Austin
> 
> 

Article: 109931
Subject: Re: Spartan 3 DCI
From: "yy" <yy7d6@yahoo.com.ph>
Date: 8 Oct 2006 10:45:36 -0700
Links: << >>  << T >>  << A >>
Hi Austin,
 Thanks, I will wait for your information tomorrow then.
--yy

Ayon kay Austin Lesea:
> I agree,
>
> Those rules ARE confusing.
>
> I will ask tomorrow am at work.  But I know from the way the IOB is
> designed, that the ONLY limitations are the Vcco has to be the same (for
> all standards in a bank), and the choice of DCI impedance (ie 50 ohms)
> will mean that all series terminated drivers in the back (eg LVDCI) will
> be 50 ohms, and all split terminated inputs (or outputs) will also be 50
> ohms (100 ohms to Vcco, 100 ohms to ground).
>
> Once the referencve resistors are set in value, then the choices of 1/2,
> 1, and 2X the reference impedance are fixed in actual value.
>
> Perhaps the rules are implying that you can not have a 50 ohm, and a 68
> ohm reference DCI standard in the same bank?  This does make sense, as
> there is only one DCI controller per bank.
>
> Austin
>
> yy wrote:
>
> > Hi Austin,
> >
> > I'm confused too. Anyway here's what the Datasheet says:
> >
> > "The rules guiding the use of DCI standards on banks are as
> > follows:
> > 1. No more than one DCI I/O standard with a Single
> > Termination is allowed per bank.
> > 2. No more than one DCI I/O standard with a Split
> > Termination is allowed per bank.
> > 3. Single Termination, Split Termination, Controlled-
> > Impedance Driver, and Controlled-Impedance Driver
> > with Half Impedance can co-exist in the same bank."
> > -- Spartan 3 Datasheet
> >
> > -yy
> >
> > Ayon kay Austin Lesea:
> >
> >>yy wrote:
> >>
> >>
> >>>Hi Austin,
> >>> ...but the datasheet tells that there should be no more than one DCI
> >>>with Split termination on the same bank? i mean what should be the
> >>>assignment of the pin that is LVDS but in the SSTL_II bank? should it
> >>>assign it to SSTL_II_DCI instead?
> >>>
> >>>
> >>>Ayon kay Austin Lesea:
> >>
> >>yy:
> >>
> >>I am confused.  LVDS_25_DCI is also split termination, one each on the +
> >>input, and the - input (two separate split terminations).
> >>
> >>Each IOB has its own attribute.  The bank is not all of any type of IO.
> >>
> >>The SSTL_II_DCI attribute will be one IO pin, and one IOB, and the
> >>LVDS_25_DCI attribute will use two IO pins, and one IOB...
> >>
> >>Austin
> >>
> >>Austin
> > 
> >


From henrik.kirneh@gmail.com Sun Oct 08 10:47:31 2006
Path: newssvr21.news.prodigy.com!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!news.linkpendium.com!news.linkpendium.com!news.banetele.no!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail
Message-Id: <452939b3$0$49200$14726298@news.sunsite.dk>
From: Henrik Pedersen <henrik.kirneh@gmail.com>
Subject: Xilinx-Modelsim on Linux
Newsgroups: comp.arch.fpga
Reply-To: henrik.kirneh@gmail.com
Date: Sun, 08 Oct 2006 19:47:31 +0200
User-Agent: KNode/0.10.4
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Xref: prodigy.net comp.arch.fpga:120866

Hey there 

I have a lot of trouble finding directions/guides/manuals on how to get
subject working.

Anyone able to point me in the right direction ?

Henrik

Article: 109932
Subject: Re: Xilinx-Modelsim on Linux
From: "=?iso-8859-1?B?R2FMYUt0SWtVc5k=?=" <taileb.mehdi@gmail.com>
Date: 8 Oct 2006 10:55:47 -0700
Links: << >>  << T >>  << A >>
Hi,
After you got the libraries compiled using the compxlib tool (included
in ISE), you shouldn't get any trouble.
Please precise the exact problem you encountred


On Oct 8, 9:47 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote:
> Hey there
>
> I have a lot of trouble finding directions/guides/manuals on how to get
> subject working.
> 
> Anyone able to point me in the right direction ?
> 
> Henrik


Article: 109933
Subject: Re: free CAN field bus IP for EDK ?
From: "Jake" <xilinx_master@hotmail.com>
Date: 8 Oct 2006 12:00:50 -0700
Links: << >>  << T >>  << A >>

rponsard@gmail.com wrote:
> in order not to reinvente the wheel is there a free and publicly
> available CAN protocol IP for microblaze/EDK (8.1 eval. version) ?
>
> or does somebody port the one in opencores into an IP for EDK 8.1 ?
>
>
> thanks
Hello,

Please notice that your core can be for free but that you must take
into
account the licence fees to Bosch for the use of the CAN protocol
http://www.semiconductors.bosch.de/en/20/can/2-license.asp

Therefore it is better to use an external component for which the
licence
fee is already payed when you buy a component. E.g. Microchip MCP2510.
All you need is an SPI core from Xilinx and a small logic core which
controls the reset and interrupt.

Kind regards,

Jake


Article: 109934
Subject: Re: Xilinx-Modelsim on Linux
From: Henrik Pedersen <henrik.kirneh@gmail.com>
Date: Sun, 08 Oct 2006 21:08:13 +0200
Links: << >>  << T >>  << A >>
GaLaKtIkUs™ wrote:

> Hi,
> After you got the libraries compiled using the compxlib tool (included
> in ISE), you shouldn't get any trouble.
> Please precise the exact problem you encountred
> 
> 
> On Oct 8, 9:47 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote:
>> Hey there
>>
>> I have a lot of trouble finding directions/guides/manuals on how to get
>> subject working.
>> 
>> Anyone able to point me in the right direction ?
>> 
>> Henrik

I'm a step further from that.
What libs should i compile.

Let me resume for a moment.
Downloaded WebPack 8,2,03i and installed it.
Done a few recomended jumps and it works.

When i click "Simulate Behavorial" i get a error saying:
Model technologies vsim cannot be found be Project navigator. ....

Where do i start ?

Henrik

Article: 109935
Subject: Re: Spartan 3 Starter Kit I/O ports
From: "vu_5421" <nugentoffer@gmail.com>
Date: 8 Oct 2006 12:50:02 -0700
Links: << >>  << T >>  << A >>
I will start implementation later in the week, I'll post my results.

Thanks for everyone's help.

John Adair wrote:
> The way we do it in our development board products is to use a bus
> switch to protect the Spartan-3 with pullups to 5V on the keyboard side
> to ensure we make 5V CMOS levels. Using the bus switch, or a series
> resistor, is probably better than an active device as some lines are
> bi-directional using open drain style driving. Controlling an active
> driver can have a few issues if you are not very careful on these
> lines. Have a look at our schematics as to what we do. Follow link to
> our PS2 module on our module page
> http://www.enterpoint.co.uk/moelbryn/modules/modules.html to access
> them.
>
> Most keyboards etc with PS2 will be happy with TTL level capable of
> being driven by the Spartan-3 but occasionally we have seen some that
> need the higher CMOS levels.
>
> John Adair
> Enterpoint Ltd.
>
> vu_5421 wrote:
> > Hello,
> >
> > I am relatively new to VHDL design, and I bought this board as a first
> > time learning kit.
> >
> > I was mainly interested in the I/O expansion connector for this board.
> > It appears that the connector has both 3.3V and 5V outputs. If I had
> > wanted to interface the board with a PS/2 port for example (which uses
> > 5V logic levels), how can I force the Spartan board to output 5V logic
> > levels and not 3.3V output?
> >
> > I'm not too sure if this is even possible since the FPGA's voltage
> > requirements is only 3.3v. 
> > 
> > Thanks for your help.


Article: 109936
Subject: Re: Xilinx-Modelsim on Linux
From: Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com>
Date: Sun, 08 Oct 2006 22:02:57 +0200
Links: << >>  << T >>  << A >>
Henrik Pedersen wrote:
> GaLaKtIkUs™ wrote:
> 
>> Hi,
>> After you got the libraries compiled using the compxlib tool (included
>> in ISE), you shouldn't get any trouble.
>> Please precise the exact problem you encountred
>>
>>
>> On Oct 8, 9:47 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote:
>>> Hey there
>>>
>>> I have a lot of trouble finding directions/guides/manuals on how to get
>>> subject working.
>>>
>>> Anyone able to point me in the right direction ?
>>>
>>> Henrik
> 
> I'm a step further from that.
> What libs should i compile.
> 
> Let me resume for a moment.
> Downloaded WebPack 8,2,03i and installed it.
> Done a few recomended jumps and it works.
> 
> When i click "Simulate Behavorial" i get a error saying:
> Model technologies vsim cannot be found be Project navigator. ....
> 
> Where do i start ?

Contact modeltech to buy modelsim ...

The free/limited modelsim-XE doens't exists for linux, so you need the
full one. But you could use the included ISE simulator. In your project
settings or global preferences, there should be an option to select your
simulation tool.


Sylvain

Article: 109937
Subject: Re: Spartan 3 Starter Kit I/O ports
From: John_H <newsgroup@johnhandwork.com>
Date: Sun, 08 Oct 2006 20:06:39 GMT
Links: << >>  << T >>  << A >>
vu_5421 wrote:
> I will start implementation later in the week, I'll post my results.
> 
> Thanks for everyone's help.

Just please read the section on the PS2 port in the Spartan3E users 
guide before adding any resistors.  They're already there.

Article: 109938
Subject: Re: free CAN field bus IP for EDK ?
From: "Thomas Entner" <aon.912710880@aon.at>
Date: Sun, 8 Oct 2006 22:42:02 +0200
Links: << >>  << T >>  << A >>
Hi Jake,

do you have any estimates regarding license-costs?

Thomas

"Jake" <xilinx_master@hotmail.com> schrieb im Newsbeitrag 
news:1160334050.484948.274520@k70g2000cwa.googlegroups.com...
>
> rponsard@gmail.com wrote:
>> in order not to reinvente the wheel is there a free and publicly
>> available CAN protocol IP for microblaze/EDK (8.1 eval. version) ?
>>
>> or does somebody port the one in opencores into an IP for EDK 8.1 ?
>>
>>
>> thanks
> Hello,
>
> Please notice that your core can be for free but that you must take
> into
> account the licence fees to Bosch for the use of the CAN protocol
> http://www.semiconductors.bosch.de/en/20/can/2-license.asp
>
> Therefore it is better to use an external component for which the
> licence
> fee is already payed when you buy a component. E.g. Microchip MCP2510.
> All you need is an SPI core from Xilinx and a small logic core which
> controls the reset and interrupt.
>
> Kind regards,
>
> Jake
> 



Article: 109939
Subject: 75Mhz Spartan3e microblaze
From: "u_stadler@yahoo.de" <u_stadler@yahoo.de>
Date: 8 Oct 2006 13:50:40 -0700
Links: << >>  << T >>  << A >>
hi

i hvea a question about implementing a microblaze with ethernet. i'm
using a spartan 3e 500 an edk8.2. i created a new project with a
microblaze, an ethernet core, sdram, timer debug module an uart. in the
ethernet datasheet it says that in order to be able to use 100MBit the
obp bus hast to run at least with 65 MHz. my problem now is the the
design wont synthesize with more than 59 MHz even if i do multiple
iterations.
can anybody give me a hint what to do?
do i have to set some more constraints or anything else?

thanks
urban


Article: 109940
Subject: Re: 75Mhz Spartan3e microblaze
From: "siva.velusamy@gmail.com" <siva.velusamy@gmail.com>
Date: 8 Oct 2006 14:43:23 -0700
Links: << >>  << T >>  << A >>
> obp bus hast to run at least with 65 MHz. my problem now is the the
> design wont synthesize with more than 59 MHz even if i do multiple
> iterations.

you should try using xplorer. Keep the MB cache size to < 8K.

/Siva


Article: 109941
Subject: Re: Xilinx-Modelsim on Linux
From: "=?iso-8859-1?B?R2FMYUt0SWtVc5k=?=" <taileb.mehdi@gmail.com>
Date: 8 Oct 2006 15:05:29 -0700
Links: << >>  << T >>  << A >>
Try to type in a shell: comxlib --s mti_se -arch all -l all -lib all -w
-smartmodel_setup
If it doesn't compile tell me the exact error message.
Be sure that the modelsim's binary files are accessible (update you
PATH environment variable)

On Oct 8, 11:08 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote:
> GaLaKtIkUs=99 wrote:
> > Hi,
> > After you got the libraries compiled using the compxlib tool (included
> > in ISE), you shouldn't get any trouble.
> > Please precise the exact problem you encountred
>
> > On Oct 8, 9:47 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote:
> >> Hey there
>
> >> I have a lot of trouble finding directions/guides/manuals on how to get
> >> subject working.
>
> >> Anyone able to point me in the right direction ?
>
> >> HenrikI'm a step further from that.
> What libs should i compile.
>
> Let me resume for a moment.
> Downloaded WebPack 8,2,03i and installed it.
> Done a few recomended jumps and it works.
>
> When i click "Simulate Behavorial" i get a error saying:
> Model technologies vsim cannot be found be Project navigator. ....
>=20
> Where do i start ?
>=20
> Henrik


Article: 109942
Subject: Re: An implementation of a clean reset signal
From: "Andrew FPGA" <andrew.newsgroup@gmail.com>
Date: 8 Oct 2006 16:23:55 -0700
Links: << >>  << T >>  << A >>
> If you take a step back and realize that you probably shouldn't expect
> anything useful out of a part that is not receiving the proper inputs yet
> (perhaps by design, after all it could be a power saving measure) then the
> outputs that do not actually reset themselves until the clock does start up
> is not really an issue.

Ok but what if those FPGA outputs can cause problems for other parts of
the system, say if the FPGA is on a bus. Maybe there are some bus
protocols out there where the bus clock can stop, and the peripheral
needs to be able to be reset by the bus master??

To be honest, all my designs to date have used synchronous resets so I
can't come up with a specific example where I had to have an async
initiated reset. The synchronous reset is simpler for me to understand
and analyse so thats what I use.


Article: 109943
Subject: Re: An implementation of a clean reset signal
From: "KJ" <kkjennings@sbcglobal.net>
Date: Mon, 09 Oct 2006 00:04:37 GMT
Links: << >>  << T >>  << A >>

"Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message 
news:1160349835.918930.124340@i42g2000cwa.googlegroups.com...
>> If you take a step back and realize that you probably shouldn't expect
>> anything useful out of a part that is not receiving the proper inputs yet
>> (perhaps by design, after all it could be a power saving measure) then 
>> the
>> outputs that do not actually reset themselves until the clock does start 
>> up
>> is not really an issue.
>
> Ok but what if those FPGA outputs can cause problems for other parts of
> the system, say if the FPGA is on a bus. Maybe there are some bus
> protocols out there where the bus clock can stop, and the peripheral
> needs to be able to be reset by the bus master??
Like I said, I don't discount that there may be these cases...but have yet 
to hear anyone actually name a specific case where the clock isn't running 
but a specific reset condition is required.

Can anyone actually provide one?  Hard to believe that such a case doesn't 
exist, but also hard to believe that one hasn't been articulated 
either....oh well.

KJ 



Article: 109944
Subject: Re: nicer code => slower code??
From: "KJ" <kkjennings@sbcglobal.net>
Date: Mon, 09 Oct 2006 00:19:22 GMT
Links: << >>  << T >>  << A >>

<burn.sir@gmail.com> wrote in message 
news:1160073562.629841.275340@c28g2000cwb.googlegroups.com...
> Mike Treseler wrote:
>> burn.sir@gmail.com wrote:
>>
>> > Would this go away if I somehow "flattened" my design?
>>
>> I would back out the changes one at a time
>> to find the culprit. Maybe adding the entities
>> created a pipeline stage somehow.
>> Also check the rtl viewer.
>>
>>    -- Mike Treseler
>
>
> Actually, both designs are _indentical_. I know that because we have
> some
> really tough tests for them. In addition, I spent 3-4 hours manually
> inspecting the code, the tests and all the simulation logs..
That is not very strong proof that they are 'identical' unless your 
testbench covered darn near every possible logic path and checked for 
outputs to be identical on each and every clock cycle, there may be 
something subtle about the change that is being overlooked.

What you should do is look at the critical timing path in the slower design 
and compare that to the same path in the original design in both cases 
looking at the synthesis output code (not your source).  That may give you a 
clue as to where the original and the cleaned up' design start to differ in 
the synthesis implementation.

>
> What happened is that the synthesis tool stopped optimising after
> a certain depth. At least, that is my theory...
And like any theory, you need to test it.  So since you now have two 
representations of a design that you believe to be functionally identical 
but one has more 'depth' to it, then you need to analyze those two designs 
and figure out why the performance of one is worse than the other (or hope 
that someone else has seen this behaviour too and what they found)....and if 
the theory holds up, open up a bug report with the folks at Synplify telling 
them what you've found.

Posting what you found here would be interesting too.  I haven't seen this 
particular problem with Synplify (or other tools) but also haven't 
specifically looked for it either.  I have been knee deep in 
analyzing/improving timing paths and never ran across hierarchy depth as 
being the culprit.

KJ 



Article: 109945
Subject: Re: An implementation of a clean reset signal
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 8 Oct 2006 17:28:08 -0700
Links: << >>  << T >>  << A >>
I suppose the following is common knowledge:
In all Xilinx FPGAs the internal flip-flops (and there are between
2,000 and 200,000 of them) are automatically asynchronously reset (or
preset, as an individual option). Any (desirable) additional
synchronous clear or set is up to the user, but usually the number of
critical flip-flops is quite limited...
Peter Alfke
==============
KJ wrote:
> "Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message
> news:1160349835.918930.124340@i42g2000cwa.googlegroups.com...
> >> If you take a step back and realize that you probably shouldn't expect
> >> anything useful out of a part that is not receiving the proper inputs yet
> >> (perhaps by design, after all it could be a power saving measure) then
> >> the
> >> outputs that do not actually reset themselves until the clock does start
> >> up
> >> is not really an issue.
> >
> > Ok but what if those FPGA outputs can cause problems for other parts of
> > the system, say if the FPGA is on a bus. Maybe there are some bus
> > protocols out there where the bus clock can stop, and the peripheral
> > needs to be able to be reset by the bus master??
> Like I said, I don't discount that there may be these cases...but have yet
> to hear anyone actually name a specific case where the clock isn't running
> but a specific reset condition is required.
>
> Can anyone actually provide one?  Hard to believe that such a case doesn't
> exist, but also hard to believe that one hasn't been articulated
> either....oh well.
> 
> KJ


Article: 109946
Subject: Re: Antifuse, lower cost?
From: "jacko" <jackokring@gmail.com>
Date: 8 Oct 2006 17:39:41 -0700
Links: << >>  << T >>  << A >>

scott moore wrote:
> Does anyone have experience with antifuse fpgas? Are they lower cost
> than static ram fpgas?
>
> Thank you,
>
> Scott Moore

are they the eeprom ones, or a high current blow?

just wondering if a reverse biased very small diode potential divider
pair could charge a FET for passthrough switch on, by the division
node. a discharge on the reverse bias diode using fet gate c as energy
source, goes forward bias, and may melt open circuit fuse. achiving cut
off.

EEPROM cell best, but physical failure is potential after so many
reprogramming cycles.

a quantum tunnel PIN+ diode gate arrangement would work the best due to
electron injection being the conduction charger of the P- gate rather
than zenner breake down. this allows the substrate voltage to be
increased. but then discharging of the floating gate becomes
statistically unlikely. UV-EPROM magnetic induction discharge also
possible.

N+ doping on far gate end placed over insulator, and also p track in
the substate beloe that, allows substrate discharge of whole chip. and
p track can be volts held to reverse bias of discharge PIN+ diodes via
p track. external to chip would be a two pin header with preserve
jumper.

cheers


Article: 109947
Subject: Re: An implementation of a clean reset signal
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Mon, 09 Oct 2006 13:46:22 +1300
Links: << >>  << T >>  << A >>
KJ wrote:
> Like I said, I don't discount that there may be these cases...but have yet 
> to hear anyone actually name a specific case where the clock isn't running 
> but a specific reset condition is required.
> 
> Can anyone actually provide one?  Hard to believe that such a case doesn't 
> exist, but also hard to believe that one hasn't been articulated 
> either....oh well.

any application where the FPGA is driving downstream power devices :
eg in Motor Drive applications.

That said, normally that type of hard reset, is normally done with
external logic devices that collect a number of 'OK' signals before
actually allowing the power devices to turn on...

-jg


Article: 109948
Subject: Re: Antifuse, lower cost?
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 8 Oct 2006 18:39:33 -0700
Links: << >>  << T >>  << A >>
We do not need any speculation. Antifuse FPGAs have been around for 20
years, Actel is the oldest supplier, Quicklogic the younger one.
The antifuse is a very small (lless than one cubic micron?) speck of
silicon that is normally an insulator, but becomes permanently
conductive when a certain (rather high) voltage and current is applied.

The system advantages are "instant-on" (no configuration process),
inherent (but limited) security and a higher radiation tolerance.
The disadvantages that have relegated antifuses to a niche market, are
one-time-only (and very slow) programmability (now that designers have
become accustomed to reprogrammability, and volatility is no longer a
dirty word), the inability of complete testing, and a seemingly natural
max size limitation.

But no need for speculation, just google Actel or Quicklogic, they will
be happy to explain...
Peter Alfke
==============
jacko wrote:
> scott moore wrote:
> > Does anyone have experience with antifuse fpgas? Are they lower cost
> > than static ram fpgas?
> >
> > Thank you,
> >
> > Scott Moore
>
> are they the eeprom ones, or a high current blow?
>
> just wondering if a reverse biased very small diode potential divider
> pair could charge a FET for passthrough switch on, by the division
> node. a discharge on the reverse bias diode using fet gate c as energy
> source, goes forward bias, and may melt open circuit fuse. achiving cut
> off.
>
> EEPROM cell best, but physical failure is potential after so many
> reprogramming cycles.
>
> a quantum tunnel PIN+ diode gate arrangement would work the best due to
> electron injection being the conduction charger of the P- gate rather
> than zenner breake down. this allows the substrate voltage to be
> increased. but then discharging of the floating gate becomes
> statistically unlikely. UV-EPROM magnetic induction discharge also
> possible.
>
> N+ doping on far gate end placed over insulator, and also p track in
> the substate beloe that, allows substrate discharge of whole chip. and
> p track can be volts held to reverse bias of discharge PIN+ diodes via
> p track. external to chip would be a two pin header with preserve
> jumper.
> 
> cheers


Article: 109949
Subject: Re: An implementation of a clean reset signal
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Sun, 08 Oct 2006 18:43:15 -0700
Links: << >>  << T >>  << A >>
On Mon, 09 Oct 2006 00:04:37 GMT, "KJ" <kkjennings@sbcglobal.net>
wrote:

>
>"Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message 
>news:1160349835.918930.124340@i42g2000cwa.googlegroups.com...
>>> If you take a step back and realize that you probably shouldn't expect
>>> anything useful out of a part that is not receiving the proper inputs yet
>>> (perhaps by design, after all it could be a power saving measure) then 
>>> the
>>> outputs that do not actually reset themselves until the clock does start 
>>> up
>>> is not really an issue.
>>
>> Ok but what if those FPGA outputs can cause problems for other parts of
>> the system, say if the FPGA is on a bus. Maybe there are some bus
>> protocols out there where the bus clock can stop, and the peripheral
>> needs to be able to be reset by the bus master??
>Like I said, I don't discount that there may be these cases...but have yet 
>to hear anyone actually name a specific case where the clock isn't running 
>but a specific reset condition is required.
>
>Can anyone actually provide one?  Hard to believe that such a case doesn't 
>exist, but also hard to believe that one hasn't been articulated 
>either....oh well.

How about TriState contention?  If I'm controlling TriState buffers
with FFs that aren't initialized until the clock comes along, I run
the risk of turning on more than one set of TriStates on a signal or
bus.  And when you're using high-current drivers, this can cause
smoke; I've seen it.

Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com




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