Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
This is what I had in the ucf - > SYSTEM_JITTER = 300 ps; > > NET fpga_clk100 TNM_NET = TNM_fpga_clk100; > TIMESPEC TS_fpga_clk100 = PERIOD TNM_fpga_clk100 10 ns HIGH 50 % > INPUT_JITTER 300 ps; > This is what I saw in the timing report (ISE 8.1.03) > Requirement: 10.000ns > Data Path Delay: 5.399ns (Levels of Logic = 6) > Clock Path Skew: 0.000ns > Source Clock: CLOCK100 rising at 0.000ns > Destination Clock: CLOCK100 rising at 10.000ns > Clock Uncertainty: 0.260ns How did the timing analyzer figure out Clock uncertainity was 260pS? Input clock goes to a DCM and the 1x output is used as CLOCK100. I understand input, system and DCM jitter values are added quadratically. I am not able to get a resultant jitter value of 520pS (so we get 260pS subtracted from clock).Article: 113501
"sonetguest" <sanjay112@gmail.com> wrote in message news:1166141318.048459.197540@l12g2000cwl.googlegroups.com... > Why do we do a quadratic add of jitter when calculating total jitter. > For example, with an input jitter of +/- 100 pS, and a DCM jitter of > +/- 100pS, will there not be an instant (with very low probability) > that when the input hits the -100pS, the DCM follows it with another - > 100pS, leading to a total time period narrowing of 200pS? Because the jitter has a statistical distribution. If your jitter were 100 ps deviation where the deviation is sinusoidal at 10 kHz added to a 9 kHz sinusoidal jitter deviation (these are not realistic situations) the jitter will add. If you use 6 sigma values for peak-to-peak, the values will add to give you a 12 sigma probability which is way beyond the 6 sigma value you're using for the peak-to-peak result. RMS noise is a quadratic add for amplitude measurements. RMS jitter (or the scaled peak-to-peak jitter) is also a quadratic add. - John_HArticle: 113502
How are these used in the case of FROM TO specs? For example, CLK In goes to a DCM, the CLK0 and CLK180 are used as CLK and CLKN. SYSTEM_JITTER = 100pS INPUT_JITTER = 200pS timegroup 1 is on CLK0 timegroup 2 is on CLK180 if I have a FROM timegroup1 TO timegroup2 of 2400 pS, how will the timing analyzer figure in the two jitter specs and the DCM jitter/skew values?Article: 113503
Jerry Avins wrote: > ma wrote: > > Hello, > > > > I learned that when a signal is multiplied by an IQ signal, the > > signal can be down sampled by 2. So assume that I have a signal that samples > > at 100MS and I multiplied it by an IQ signal. Then I can down sample each I > > and Q to 50MS. How is it working? Do I need a filter before down sampling? > > Or can I down sample without any filtering? Any example design that show how > > I can do this preferably in FPGA? > > A signal needs two samples taken in the time of the period of its > highest frequency. They can either be assembles as one stream at the > given rate or as two streams at half that rate, one I and one Q. In > different words, one complex sample can replace two real-only samples. > > What do you mean by "multiplied by an IQ signal? I don't understand the > procedure you allude to. > Hey Jerry, an IQ multiplier refers to the machine built by the Krell. It was Dr. Mobius' undoing. ClayArticle: 113504
Clay wrote: ... > Hey Jerry, an IQ multiplier refers to the machine built by the Krell. > It was Dr. Mobius' undoing. Just goes to show what I know! I thought is was a Montessori thing. Flowers for Algernon, anyone? Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 113505
Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.0.18 now. The missing cygwin dll problem is fixed. http://www.dspia.com/gtkwave.htmlArticle: 113506
Hi I want to change the LVTTL to SSTL-3 pins.My design is performing worse in noisy conditions.I am using cyclone II EP1C120Q240C8.What are the steps for conversion.VCCINT is 1.5V VCCIO is 3.3 V for both Thanking you vsrpkumarArticle: 113507
ram wrote: > Hi > I want to change the LVTTL to SSTL-3 pins.My design is performing worse > in noisy conditions.I am using cyclone II EP1C120Q240C8.What are the > steps for conversion.VCCINT is 1.5V > VCCIO is 3.3 V for both > Thanking you > vsrpkumar I used LVTTL standard for I/O pins.I want to change all of then to SSTLArticle: 113508
Hello This error is due to the system ace is looking for .ace file for configuring the FPGA. If it can not find the file the led will bi lit.Article: 113509
When you understand the details of a particular application, you can use all sorts of trickery and compromises, etc. I have always been forced to design a universal FIFO at the highest possible speed, with the greatest versatility, without unnecessary limitations. That limits the freedom to explore special and limited design styles. The fate of an IC applications engineer...But I am not complaining. Peter Alfke On Dec 14, 10:43 am, "Tommy Thorn" <tommy.th...@gmail.com> wrote: > Peter Alfke wrote: > > In an asynchronous FIFO, reading and writing is controlled by two > > counters with independent clocks. > > If you need to detect FULL or EMPTY, you compare the two counters for > > identity. > > If you do that with binary counters, you are vulnerable to strange > > decoding glitches, while multiple binary bits change (almost, but not > > quite, simultaneously). You never have that problem with Gray counters, > > where only one bit changes, from one state to the next.How about a different way? Couldn't one simply maintain two views (one > for each clock) of the state of the FIFO, always a conservative > approximation to the "true" state, and use standard handshake > techniques to communicate to the writer "since our last handshake, I've > dequeued X words", and visa versa. > > The advantage of this (besides simplicity) is that one can pipeline the > handshake arbitrarily much, only at the expense of added latency > between full->non-full and empty->non-empty transitions. > > Isn't this a standard technique? > > TommyArticle: 113510
mk wrote: > Hi, > I updated the GTKWave for Win32 port I am maintaining. It's at 3.0.18 > now. The missing cygwin dll problem is fixed. > > http://www.dspia.com/gtkwave.html Great job. Thanks. We will use it as viewer of our new Open Logic Analyzer based on the JTAGkey + FPGA . Best regards, Laurent www.amontec.comArticle: 113511
"ma" <ma@nowhere.com> wrote in message news:NWYfh.100069$qd7.26588@fe1.news.blueyonder.co.uk... > > I have a real signal that sampled at say 100MSPS. I want to create an IQ > signal from it. I am multiplying it with I and Q signals. After this > multiplication, I have two signals one I and one Q. As you explained, it > is a complex representation of my signal. So I can have 50MSPS on each > stream. How can I do downsampleing in this case? Should I filter the > signal before downsampling or not? If I am not doing any filtering, is > there any chance for aliasing in this case? Where can I read more about > this subject? I think what the OP is alluding to when saying that s/he's "multiplying it with I and Q signals" is that the input signal's being mixed by a 50MHz quadrature oscillator. Rick Lyons' excellent treatise on the subject is here: http://www.dspguru.com/info/tutor/QuadSignals.pdf. For me, this was one of those articles you read where the penny miraculously drops. Cheers, HowardArticle: 113512
> Wow, that's some sea-of-pals! > What parts are they ? well there are three different pal's out there. 22v10-15,22v10-10 and 16R8 > > and eight XC3130 series(VHDL) into state of the art FPGA devices. > > Does this need to be 'instant-on' ? - or 5V complaint ? i dont have a specific requirement on instant-on and 5V complaint. i am currently writing all the ABEL code in one architecture and individual PAL functionality's in different process.I doubt whether this will help in true sense.:-) Jim Granville wrote: > lingamaneni.naveen@gmail.com wrote: > > > Hello Guys, > > First of all thanks for all of your valuble suggestions.I was able to > > get the source code (ABEL) for all the PAL's now.Since most of the > > PAL's were absolute now and for ROHS compliance we are redesigning the > > board and now we want to replace bulky PAL's around 70 > > Wow, that's some sea-of-pals! > What parts are they ? > > > and eight XC3130 series(VHDL) into state of the art FPGA devices. > > Does this need to be 'instant-on' ? - or 5V complaint ? > > > Coming to my first point > > 1. Can i have a VHDL main module and integrate all the individual .ABL > > files as it is and achieve the same functionality of all the PAL's > > within FPGA. > > (With out converting ABEL to VHDL) > > See Gabor's post. This sounds worth trying, perhaps on a couple > of Xilinx tool flows (and I think Lattice also have Abel in their > flows ) > > > > > 2. Here the board performance (timing of PAL) has to remain the same > > with high speed FPGA also.Never worked on timing issues till now but > > heard registering and using flip flop can solve problem any better > > ideas? > > (First i am working out on how to get the timing of a PAL from the old > > board before knowing how to achieve the same timing with in a high > > speed FPGA ) > > > > Sorry for my list of questions and Thanks for being supportive. > > This could be interesting... > Trying to actually match timing is not going to be easy. > If the PLD code is all Clock-based, then you only need to be > 'the same, or faster' on the FPGA. > - but the PLD code may not be quite that clean.... > > I'd suggest a scan of the Abel sources, and also compile the sources > you have (minimal changes, non-merged), to a legal target (XC2C32A?), > and read the warnings and fitter report files. > The try merge of a couple of sources, into one Abel source file, > if you use PIN for the external signals, and nodes for the ones that > are only pal-pal, then the tools can optimise if they need to, or > use keep if you want to avoid that. > > -jgArticle: 113513
Thanks a lot David, I got access to prea!! Mehdi David wrote: > Antonio, > > Actually, the Spartan3 and Virtex4 do have bus macros available for use > with ISE 8.x. The only place I know of on the web that has the latest > bus macros is Xilinx's Partial Reconfiguration Early Access Software > Tools website. There are early access tools, so you need to apply and > be granted access. I believe Xilinx requires a certain level of local > support to be in place before granting access. You can apply for access > at > http://www.xilinx.com/xlnx/xil_entry2.jsp?sMode=login&group=prealounge > > I hope this helps, > > David > > A.D. wrote: > > Hi all, > > does anybody know how partial reconfiguration is carried > > out in new Xilinx FPGAs (Spartan3 and Virtex4)? > > These devices have no internal three-state buffers or > > bus macros, so is there a way to avoid contentions during > > reconfiguration?!? > > > > Thanks, > > AntonioArticle: 113514
I have never been using the GUI interface, so I can't help you with
that.
But for your first test, I would suggest that you launched the
different commands by hand. For instance, try to launch the ngdbuild
command with the name of your bmm file directly (PPC_DDR_stub.bmm):
the command line should be :
ngdbuild -p <device_name> -uc <design>.ucf -bm <design>.bmm <design>
the device name being for instance "-p xc2vp70ff1704-6" if you are
using a V2P70 with package FF1704 and speed 6.
You then launch the map, the par, the trce and the bitgen with the
options you want.
Bitgen should create the _bd.bmm file that you need to use in the
data2mem command to put the soft (.elf file) in the BRAMs. Here is the
command you should be using (if your soft file is called
executable.elf, and the output bit file your want to generate is called
download.bit):
data2mem -bm <file>_bd.bmm -bt <file>.bit -bd executable.elf tag
plb_bram_if_cntlr_1_bram -o b download.bit
A .bmm file looks like this:
ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xfffe0000:0xffffffff]
BUS_BLOCK
plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s1_s1_0
[63:63] ;
plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s1_s1_1
[62:62] ;
...
END_BUS_BLOCK;
END_ADDRESS_BLOCK;
And the generated _bd.bmm file should look like this (this is the same,
but placed):
ADDRESS_SPACE plb_bram_if_cntlr_1_bram RAMB16 [0xFFFE0000:0xFFFFFFFF]
BUS_BLOCK
plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s1_s1_0
[63:63] PLACED = X1Y17;
plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s1_s1_1
[62:62] PLACED = X1Y18;
...
END_BUS_BLOCK;
END_ADDRESS_SPACE;
Hope this helps.
Article: 113515Actually there is a typo in the subject line. We see this behaviour on Virtex-4FX20CES4. Kolja Sulimma schrieb: > Hi! > > Does anybody here have experience with Virtex-4 MGTs in SONET alignment > configuration? > > We turn of ENPCOMMAALIGN and ENMCOMMAALIGN immediately after we see > COMMDA_DETECT and still the byte aligner shifts bits around the next > time it sees an A1 or A2 pattern.(This happens a couple of clock cycles > after the sync pattern of 12 times A1 folloed by 12 times A2 was received. > > Kolja Sulimma > cronologic ohgArticle: 113516
Hi, I'm currently preparing a design for a V4 sx55, of course it shall do a lot of signal processing. Against this background I estimate the resources needed. The FIR compiler provides the number of DSP-Slices and BRAMs, furthermore I use grep across the vhdl simulation model to count the number of FDs. Here I'm surprised that my filter shall need 1300 FD/FDR/FDSE/... Because I have to implement tens of filters it wouldn't fit. Does the number of FD* instances within the simulation file fit the number of real used FDs? I fear it:-(. If not, how can I obtain the real number of used Slices/FDs? Bye TomArticle: 113517
"Thomas Reinemann" <tom.reinemann@gmx.net> wrote in message news:eltuea$rjc$1@news.boerde.de... > Hi, > > I'm currently preparing a design for a V4 sx55, of course it shall do a > lot of signal processing. Against this background I estimate the > resources needed. The FIR compiler provides the number of DSP-Slices and > BRAMs, furthermore I use grep across the vhdl simulation model to count > the number of FDs. Here I'm surprised that my filter shall need 1300 > FD/FDR/FDSE/... > Because I have to implement tens of filters it wouldn't fit. > Does the number of FD* instances within the simulation file fit the > number of real used FDs? I fear it:-(. > If not, how can I obtain the real number of used Slices/FDs? > > Bye Tom Hi Tom, I fear it too! Do you realise that you can trade off size against sample rate in an FPGA? You could search for "distributed arithmetic" for more information. HTH, Syms.Article: 113518
>Hi I wanted some help or pointers in Asynchronous LIFO design. My read and write clocks are asynchronous, I don't know how to take care of this nature of clock in a LIFO design. > >I know how to implement a stack if the read and write are in the same clock domain, but not when the clocks are different. > >Any suggestion or pointers will be helpful. > >rgds bijoy > As previously stated, you will have to deal with clock domain crossing issues if you want a reliable design. I would have the memory and counter in the the Read/Pop-side domain, and buffer the Write/Push commands to reduce metastability effects. This will add latency to the Write operations, which may cause a problem if Write/Push and Read/Pop commands happen close together. If there is no handshaking for the Read/Pop commands then at some point you will almost certainly get the wrong data... How 'Asynchronous' is the system? Timing anlaysis, and timing-driven synthesis may be problematical.Article: 113519
>> >> integer'image returns the textual representation of "int", but what is >> wrong with simply writing "int"? Or I guess I should ask what the >> difference between two is? (Is output of "int" type integer and output >> of "integer'image" type char (or is it string of integers?)?) >> >I'm not sure what exactly you mean here or exactly what file format >you're really trying to write. Try having the simulation write out the >file and see what you get. If the file comes out in the format that >you want, then you're done. > >KJ > With VHDL you can write binary files. This is the default. If you write to a binary file, this will be in a machine-specific binary format that will be difficult for a human to read, even with a hex-capable file editor. If you need a file that humans can read, use text files via STD.TEXTIO package procedures, as advised above.Article: 113520
>Hi, > >I'm currently preparing a design for a V4 sx55, of course it shall do a >lot of signal processing. Against this background I estimate the >resources needed. The FIR compiler provides the number of DSP-Slices and >BRAMs, furthermore I use grep across the vhdl simulation model to count >the number of FDs. Here I'm surprised that my filter shall need 1300 >FD/FDR/FDSE/... >Because I have to implement tens of filters it wouldn't fit. >Does the number of FD* instances within the simulation file fit the >number of real used FDs? I fear it:-(. >If not, how can I obtain the real number of used Slices/FDs? > >Bye Tom > If your sample rate is several times slower than the acheivable clock rate of the FPGA, you can time-multiplex the multipliers. If you are running out of flip-flops (registers) that is a more serious matter. You need to come up with a less register-intensive implementation. I suspect that the generated code is not very efficient, and you may have to do it "by hand". I had similar problems with an Altera part. Only took me about 3 months to design something that fitted. ;-)Article: 113521
Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: > [... snip ...] > > > > Steven - you arent working for Altera? > > > > I clicked on the link to plddesignline and got a big flashing Altera > > Stratix-III AD flyer !! > > ok, well its beyound your control, but was amusing. > > similarly as it was amysing to come to Xilinx booth at Electronica2006, all > > it was to > > see was a big Actel Logo as their booth was just befor Xilinx and way more > > visible. > > > > Antti > > I saw that too, but unfortunately I don't get to decide who advertizes > on the EE Times web sites. > > Hey, if you can afford a Stratix-III FPGA, I'd really like to introduce > you to the following superior FPGA product line. :-) > http://www.xilinx.com/virtex5 > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/-3E/-3A FPGAs > http://www.xilinx.com/spartan3e > http://www.xilinx.com/spartan3a > E-mail: steve.knapp@xilinx.com > --------------------------------- > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. Steve, What is the estimate price for the Virtex-5 FPGA?Article: 113522
Netoko Young schrieb: > Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: > > [... snip ...] > Steve, > > What is the estimate price for the Virtex-5 FPGA? Mr Young, the V5 pricing is public, just look at Xilinx Presse Release the pricing is included there AnttiArticle: 113523
hi, i'm working on fpga .. wanna make an vhdl code for lcd .. but as a block diagram .. using mux ( multiplexer ) and counters .. etc etc.. any help ?? thnx meshoshow ..Article: 113524
On 15 Dec 2006 02:39:50 -0800, "Arnaud" <arivaton@gmail.com> wrote: [ much edited out to add one additional point...] >A .bmm file looks like this: >ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xfffe0000:0xffffffff] > BUS_BLOCK > plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s1_s1_0[63:63] ; > plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s1_s1_1[62:62] ; > ... > END_BUS_BLOCK; >END_ADDRESS_BLOCK; > >And the generated _bd.bmm file should look like this (this is the same, >but placed): > >ADDRESS_SPACE plb_bram_if_cntlr_1_bram RAMB16 [0xFFFE0000:0xFFFFFFFF] > BUS_BLOCK > plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s1_s1_0[63:63] PLACED = X1Y17; > plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s1_s1_1[62:62] PLACED = X1Y18; > ... > END_BUS_BLOCK; >END_ADDRESS_SPACE; > >Hope this helps. There used (in EDK 7.1) to be one extra step, not well handled by the tools, when generating a PPC system in EDK, then incorporating it into a top level design in ISE. I don't know if this still applies in ISE/EDK 8.*. EDK will generate the above ".bmm" file as shown. However the PPC system is incorporated into ISE design as one component in a larger system, for example as an instance labelled "myppc_system". (assuming it is incorporated into the top level ISE design; if it is part of block1, the instance label will be "block1/myppc_system") Thus the BRAMs are known by a different name in the top level design; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s1_s1_0 becomes myppc_system/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s1_s1_0 and data2mem cannot find them in the BMM file. If this is the case in your example, you can edit the ".bmm" file in a text editor, and prepend "myppc_system/" (or "block1/myppc_system/") to each line in the BUS BLOCK. I only needed to do this edit once, when I first incorporated the PPC system into the top level design. After this, the tools find the BRAM instances, and bitgen creates the correct "_bd.bmm" file, which can be inspected to see the PLACED constraints as above. Hope this helps, - Brian
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z