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Messages from 114425

Article: 114425
Subject: Re: Surface mount ic's
From: Tim <simon@nooospam.roockyloogic.com>
Date: Mon, 15 Jan 2007 20:59:04 +0000
Links: << >>  << T >>  << A >>
Tim wrote:
> Philip Freidin wrote:
>> I recently bought this:   http://www.sra-solder.com/aoyue_2702.htm
>>
>> and this:                 http://store.amscope.com/sm-3tz.html
>>
>> and this:                 http://store.amscope.com/md600.html
>>
>> I plan to create training movies on how to do SMT board assembly,
>> SMT rework, and SMT repair.  Any interest?
>>
>> Philip
> 
> Now all you need is a Gerber-driven solder paste dot printer! They 
> exist, and news of an affordable unit for prototyping would be interesting.

Following up myself, the Essemtec CDS6700 solder paste printer seems to 
cost around $25,000. Not quite affordable ;-)

Article: 114426
Subject: Re: EDIF format
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 15 Jan 2007 22:05:41 +0100
Links: << >>  << T >>  << A >>
"quad" <fyp.quadruples@gmail.com> writes:

> where can i find a description of the edif format. www.edif.org doesn't
> have the syntax

Try,

http://web.archive.org/web/20051218223743/www.edif.org/documentation/index.html

Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 114427
Subject: Re: ISE 9.1i and partial reconfiguration
From: "-jg" <Jim.Granville@gmail.com>
Date: 15 Jan 2007 13:37:36 -0800
Links: << >>  << T >>  << A >>

Andy Peters wrote:
> El-Mehdi Taileb wrote:
> > Hi all!
> > ISE 9.1i is finally out!
> > I read the marketing papers but didn't find any word about partial
> > reconfiguration support.
>
> They also talk about some kind of source-code control "feature" --
>
> "Source Code Control Capabilities: Allows users to quickly and easily
> identify the files associated with a known version of their design.
> They can then export the source files and scripts needed to regenerate
> the project with the same sources and settings."
>
> Rather than reinvent the wheel, why don't they just make their tools
> friendlier to use with existing SCC systems (Subversion, Perforce,
> Bitkeeper, whatever)?


,,, and did they fix their Binary Project file mis-step ?

There is some info on  incremental changes here
http://www.eeproductcenter.com/embedded/review/showArticle.jhtml?articleID=196900852

Hasn't Altera had that for a while.. ?

No mention if incremental changes works on purely Xilinx flows, or
webpack, the PR is all about Synplicity.

-jg


Article: 114428
Subject: Re: Transport Delays in Modelsim
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Mon, 15 Jan 2007 22:07:11 +0000
Links: << >>  << T >>  << A >>
On Fri, 12 Jan 2007 22:27:16 +0000, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

>On Fri, 12 Jan 2007 10:35:09 -0700, Kevin Neilson
><kevin_neilson@removethiscomcast.net> wrote:
>
>>Jonathan Bromley wrote:
>>> It's panto time... Oh yes it is!!!!
>
>>  I guess it is panto time--whatever that might be.
>
>Sorry, I should have taken note of your timezone.
>
>Someone else please explain :-)

Perhaps this will help....

http://www.shapes.demon.co.uk/photos/Costumes/Panto/tennisboys.jpg

Or maybe not!

- Brian


Article: 114429
Subject: Re: Will FPGAs suit my need?
From: samiam <samiamSPAMTHIS@spamalert.com>
Date: Mon, 15 Jan 2007 22:48:32 GMT
Links: << >>  << T >>  << A >>
> I thought FPGAs might be suitable, but they all appear to try to offer
> more than just something like that. Can anybody point me in some rough
> direction?

You need SPLD's simple programmable logic devices like the 22v10 or 16v8
(which I am using for my designs). You can get them at jameco,allect or
better yet: EBAY

Article: 114430
Subject: Re: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 15 Jan 2007 15:28:19 -0800
Links: << >>  << T >>  << A >>

Vangelis wrote:
> You can also initialize manually the BRAM memory. Use the Language Templates through the ISE to see the way!

Yes.

Actually I can do it by adding some loops in nRESET = '0' statement to
get all signle-port ram initialized, but it is not the same as FPGA
situation.

Weng


Article: 114431
Subject: Verifying a Bidirectional Data Bus
From: "pete o." <portisi@comcast.net>
Date: 15 Jan 2007 19:01:50 -0800
Links: << >>  << T >>  << A >>
I  have had reasonable success verifying some designs using behavioral
verilog and modelsim.
I seem to have trouble with bidirectional data buses. I have a handful
of verilog books, but none of
their simulation examples use bidirectional buses. Someone told me I
must use a transactor?
If anyone can point me to a text or has any tips it would be
appreciated.


Article: 114432
Subject: Registered?
From: "Ian" <ian.shee1@gmail.com>
Date: 15 Jan 2007 20:51:36 -0800
Links: << >>  << T >>  << A >>
Hi,

I'm trying to simulate Error Corection Coding (Reed-Solomon)
ip core with Xilinx Spartan FPGA as the target.
Using ISE v8 as the interface.

Xilinx Logicore has provided a Reed-Solomon Encoder.
Going through the datasheet (DS251) page 2:

"The core's synchronous input control signals
(START, ND, BYPASS, CE) are not registered inside thecore.
It is assumed these will be registered external to the core if
required"

What is the difference between a core with REGISTERED Input and
one WITHOUT REGISTERED input?
Does one have the advantage over the other?
Would adding a Delay Flip-flop do?

Thanks.


Article: 114433
Subject: Re: Registered?
From: "Joel Kolstad" <JKolstad71HatesSpam@Yahoo.Com>
Date: Mon, 15 Jan 2007 21:13:06 -0800
Links: << >>  << T >>  << A >>
"Ian" <ian.shee1@gmail.com> wrote in message 
news:1168923096.202584.258410@v45g2000cwv.googlegroups.com...
> "The core's synchronous input control signals
> (START, ND, BYPASS, CE) are not registered inside thecore.
> It is assumed these will be registered external to the core if
> required"
>
> What is the difference between a core with REGISTERED Input and
> one WITHOUT REGISTERED input?

It means the control signals mentioned are coming out of a flip-flop that's 
clocked off the same clock that's running to the core.

> Does one have the advantage over the other?

Well, if you don't synchronize your control signals to the core's clock, you 
potentially end up with metastability problems (when you inadvertently 
violate the set-up and hold times of the core's internal flip-flops) and the 
core will just generate garabge data for you!  Granted, for signals like 
BYPASS, CE, etc., it'll probably recover sooner or later, but the idea is 
that without synchronization there's no guarantee the thing works at all.

The only disadvantages of the core registering the inputs itself would be 
that (1) it uses up additionally flip-flops and (2) it introduces another 
clock cycle of latency.  In many cases this is a negligible difference, but 
since many people already have synchronous control signals running around 
anyway, Xilinx figures they'll go for the ever-so-slightly higher 
performance/lower gate count solution.

> Would adding a Delay Flip-flop do?

Just add a regular old flip-flop.  Assuming the core came with a timing 
constrains file, place and route will automatically, uh... place and route 
the flip-flops such that the set-up and hold times are met on the control 
signals.

---Joel



Article: 114434
Subject: Constraining Multiple clock design
From: "madair" <umrtech@gmail.com>
Date: 15 Jan 2007 22:08:50 -0800
Links: << >>  << T >>  << A >>
Hi all,

I'm using Mentor Graphic tools to synthesize my design (Leonardo
Spectrum: ASIC and Precision RTL: FPGA).

The problem is I'm not very sure on constraining a multiple clock
design using Mentor tools. Someone please share some TCL scripts
(LeoSpec & Precision) on constraining multi-clock design. It will be a
good reference for me and to other people.

At least, a guideline on this issue.
Any suggestions and/or advice are most welcome and highly appreciated.

Thanks in advance,


Article: 114435
Subject: Digital Filter and external PLL (VCO)
From: "axalay" <axalay@gmail.com>
Date: 16 Jan 2007 00:56:28 -0800
Links: << >>  << T >>  << A >>
I am generate 2.048 MGz with jitter ~5ns if FPGA. I need to reduse
jitter and vander using the digital filter. Tell me please what tipes
of filters will solve this problems.

And next question. I whant generate 19.44 MGz (whith good gitter and
vander) from that 2.048 MGz whith use external VCO. I see 2 ways:

1) use digital faze detector, which generate 2 signais : charge and
discharge the external capasitor (to operate the VCO).
2) use digital PI regulator, which generate PWM. ANd use external
filter.

Ho from 2 ways better?


Article: 114436
Subject: Re: 16-bit DDR memory controller in EDK
From: "Guru" <ales.gorkic@email.si>
Date: 16 Jan 2007 02:08:32 -0800
Links: << >>  << T >>  << A >>
Farhan,

PLB_DDR in EDK 8.2 supports x16 DDR. I have tried it in Virtex4 Mini
Module and it works OK.
If you need a uCLinux made for PPC let me know.

Cheers,

Guru



sheikh.m.farhan@gmail.com wrote:
> Hi,
> I need to know is it possible to have a 16-bit PLB DDR memory
> controller in EDK 8.x for a custom made board. So far what I have seen
> is EDK supports 32 and 64-bits PLB DDR controller for third party base
> systems.
> Has anyone tried to port Linux 2.4.x successfully on PPC running on
> Virtex 4? Any issues.......
> 
> Farhan


Article: 114437
Subject: Re: Constraining Multiple clock design
From: "Hans" <hans64@ht-lab.com>
Date: Tue, 16 Jan 2007 12:00:16 GMT
Links: << >>  << T >>  << A >>

"madair" <umrtech@gmail.com> wrote in message 
news:1168927730.727433.66590@38g2000cwa.googlegroups.com...
> Hi all,
>
> I'm using Mentor Graphic tools to synthesize my design (Leonardo
> Spectrum: ASIC and Precision RTL: FPGA).
>
> The problem is I'm not very sure on constraining a multiple clock
> design using Mentor tools. Someone please share some TCL scripts
> (LeoSpec & Precision) on constraining multi-clock design. It will be a
> good reference for me and to other people.
>
> At least, a guideline on this issue.
> Any suggestions and/or advice are most welcome and highly appreciated.
>
> Thanks in advance,
>

In Precision I would simply use the GUI to constrain the clocks and then cut 
and paste the resulting SDC constructs from the transcript window into a 
script. All clock are by default asynchronous but you can put them in the 
same domain again using the GUI or simply use the -domain argument on 
create_clock. If you have lots of clocks which are not fixed between runs 
then look up the get_ports/get_clocks SDC commands in the manual, with this 
command you can do stuff like:

set clock_list [get_clocks *]
or
set clock_list {clock1 clock2 clock3}

foreach clk_i $clock_list {
    create_clock -period .... -name  $clock_list ... -domain ....
}


Hans
www.ht-lab.com



Article: 114438
Subject: four phase clock using DCM with xilinx FPGA
From: "skyworld" <chenyong20000@gmail.com>
Date: 16 Jan 2007 04:31:15 -0800
Links: << >>  << T >>  << A >>
Hi,
I need to generate four clocks with DCM in VIRTEX4. The frequency is
312MHz. I can't get any output from clk_90 and clk_270. I contacted
Xilinx's FAE and they told me there is no output from 90/270 phase
shift when DCM works at high speed mode. Does anybody know how to
generate these four clocks with equal phase shift in VIRTEX 4? thanks
very much.


Article: 114439
Subject: Two newbie Chipscope questions
From: "kron" <kronkarp@googlemail.com>
Date: 16 Jan 2007 04:45:22 -0800
Links: << >>  << T >>  << A >>
Hi,

I am new to using Chipscope, I've read the manual and lots of
tutorials in the www and threads in this newsgroup.

Is there a way to see the "real" edges of my signals?
All I got to see were these perfect rectangular edges
that I see in the simulation, too.
To find some glitching-related problems, wouldn't it be
useful/necessary to see the actual edges that happen in the FPGA?

How can I trigger a change in a signal, i.e. I want to
start "recording" my signals, when I push a button on my
board?

Thanks in advance for any hints!


Article: 114440
Subject: about XAPP028
From: "axalay" <axalay@gmail.com>
Date: 16 Jan 2007 06:03:43 -0800
Links: << >>  << T >>  << A >>
I am find this document when search information about PLL. There three
phase detector circuts. I simulate its in MAX+, but all output signals
are in "X" state! Whay?


Article: 114441
Subject: Re: Digital Filter and external PLL (VCO)
From: ray@desinformation.de
Date: 16 Jan 2007 06:06:39 -0800
Links: << >>  << T >>  << A >>

axalay schrieb:

> I am generate 2.048 MGz with jitter ~5ns if FPGA. I need to reduse
> jitter and vander using the digital filter. Tell me please what tipes
> of filters will solve this problems.

The loop filter of a PLL/DLL may help here. So you'd build a "analog"
PLL with only a phasecomparator+loopfilter and a VCO. How is the jitter
spectrally distributed ? Design the loop filter appropriately.
Doing it completely in the FPGA may also work, but is limited by the
maximum clock you can do to maybe >1ns jitter with a "multiphase clock
design" or similar.

>
> And next question. I whant generate 19.44 MGz (whith good gitter and
> vander) from that 2.048 MGz whith use external VCO. I see 2 ways:
>
> 1) use digital faze detector, which generate 2 signais : charge and
> discharge the external capasitor (to operate the VCO).
> 2) use digital PI regulator, which generate PWM. ANd use external
> filter.
>
> Ho from 2 ways better?

The 1 Up/Down charge pump seems simpler and has the advanteage of the
only sidebands (Fref 8KHz)proportional to phase difference(jitter).

For 2 the PWM frequency should be high enough compared to the loop
frequency (<8KHz), maybe 200KHz to keep _additional_ VCO sidebands
small enough with a simple RC filter. The RC filter cutoff and phase
shift should be insignificant up to the loop bandwidth. And PWM
resolution needs to be sufficient, because quantization here adds to
jitter. I feel this is not very practical and would go with the 1st
filter.

Sadly, the XILINX DCM will fail as a jitter filter here due to it's
digital nature. But I think XILINX will (or has) redesign(ed) the DCM
to be in the "good old" analog PLL-Style.


Article: 114442
Subject: Re: Two newbie Chipscope questions
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Tue, 16 Jan 2007 14:27:20 -0000
Links: << >>  << T >>  << A >>
Hi,

"kron" <kronkarp@googlemail.com> wrote in message 
news:1168951522.516410.128360@51g2000cwl.googlegroups.com...
> Hi,
>
> I am new to using Chipscope, I've read the manual and lots of
> tutorials in the www and threads in this newsgroup.
> Is there a way to see the "real" edges of my signals?
> All I got to see were these perfect rectangular edges
> that I see in the simulation, too.

No. Chipscope is a logic analyzer, not an oscilloscope. It pretty much 
relies on your logic being synchronous to the clock that's being used to 
sample the data. Plus there are no GHz-bandwidth ADCs embedded in the FPGA 
that could be used to capture these "real" traces.

> To find some glitching-related problems, wouldn't it be
> useful/necessary to see the actual edges that happen in the FPGA?

Unless you're doing something really esoteric in your design, such 
glitch-related problems will never arise. The tools take care of the timing 
closure for you, and the sub-micron designers at Xilinx take care of the 
low-level internal signal integrity issues and so on. So you really truly 
can work at the boolean-or-higher level of abstraction in complete safety 
(or your money back).

If you suspect you have duff signal integrity at the pins of your FPGA, then 
grab yourself a real scope and go to town (but Chipscope won't help you 
there).

Cheers,

      -Ben- 



Article: 114443
Subject: small, free simple state machine processor suggestions?
From: jonas@mit.edu
Date: 16 Jan 2007 06:44:51 -0800
Links: << >>  << T >>  << A >>
Has anyone found or could recommend a small(ish) processor for more
complex state machine tasks that is:

1. ~1000 LUTs or so (smaller is better)
2. available under a free license (say, GPL, LPGL, BSD)
3. available in vhdl?

Ideally something like picoblaze would probably do what I want, except
that it's not under any of the available licenses, and pacoblaze is
vhdl (and potentially an IP nightmare). I've found a bunch of small
processors on opencores and the like but many of them look
half-finished. Any recommendations? These state machines are driving me
mad!

Thanks!

...Eric


Article: 114444
Subject: Setup time path on V4 SX w/ IDELAY
From: "Brandon Jasionowski" <killerhertz@gmail.com>
Date: 16 Jan 2007 06:54:18 -0800
Links: << >>  << T >>  << A >>
I have the following path in an IOTILE:

IBUFDS --> IDELAY (IOBDELAY_TYPE => "FIXED", IOBDELAY_VALUE => 0) -->
FDC

I have a V4 SX55 -11

Here's the output from my map timing:

<SNIP>
Slack (setup path):     1.411ns (requirement - (data path - clock path
- clock arrival + uncertainty))
  Source:               adc1_db_n<11> (PAD)
  Destination:          adc1_iface/id_out_r_11 (FF)
  Destination Clock:    adc_clk rising at 0.000ns
  Requirement:          8.000ns
  Data Path Delay:      7.091ns (Levels of Logic = 3)
  Clock Path Delay:     0.682ns (Levels of Logic = 3)
  Clock Uncertainty:    0.180ns

  Data Path: adc1_db_n<11> to adc1_iface/id_out_r_11
    Delay type         Delay(ns)  Logical Resource(s)
    ----------------------------  -------------------
    Tiopp                 1.241   adc1_db_n<11>
    net (fanout=1)     e  0.000
adc1_iface/array_gen[11].diffend_gen.ibufds_inst/SLAVEBUF.DIFFIN
    Tiodi                 0.000
adc1_iface/array_gen[11].diffend_gen.ibufds_inst/IBUFDS
    net (fanout=1)     e  0.274   adc1_iface/ibuf_out<11>
    Tidockd               5.576   adc1_iface/array_gen[11].idelay_inst
                                  adc1_iface/id_out_r_11
    ----------------------------  ---------------------------
    Total                 7.091ns (6.817ns logic, 0.274ns route)
                                  (96.1% logic, 3.9% route)
</SNIP>

I don't understand why the TIDOCKD time is so long. According to the V4
data sheet it should be 0.87ns. While I'm currently meeting timing, I
really want this path to be under 3 ns (I had to increase the OFFSET
constraint to 8 ns in order to run post-map static timing). At the
moment I'm using the IDELAY as a placeholder, but in the future I might
want to have a non-zero IOBDELAY_VALUE, so I'd rather keep it.

Any ideas?

Btw, what is the default IOSTANDARD, if not specified in the UCF, for
differential and single-ended pins. I thought I remember reading it
somewhere, but I can't find that reference anymore.

Thanks,
-Brandon


Article: 114445
Subject: Re: small, free simple state machine processor suggestions?
From: Sean Durkin <news_jan07@durkin.de>
Date: Tue, 16 Jan 2007 15:56:26 +0100
Links: << >>  << T >>  << A >>
jonas@mit.edu wrote:
> Has anyone found or could recommend a small(ish) processor for more
> complex state machine tasks that is:
> 
> 1. ~1000 LUTs or so (smaller is better)
> 2. available under a free license (say, GPL, LPGL, BSD)
> 3. available in vhdl?
> 
> Ideally something like picoblaze would probably do what I want, except
> that it's not under any of the available licenses, and pacoblaze is
> vhdl (and potentially an IP nightmare). I've found a bunch of small
> processors on opencores and the like but many of them look
> half-finished. Any recommendations? These state machines are driving me
> mad!
Lattice offers the Mico8 as OpenSource, available as Verilog and VHDL
sources. Haven't tested it yet, so I can't comment on it at all. Plus I
don't know if it uses specific features for Lattice-parts or can be
synthesized for any architecture.

Just have a look at the website:

http://www.latticesemi.com/products/intellectualproperty/referencedesigns/8bitmicrocontrollermico8.cfm

-- 
My email address is only valid until the end of the month.
Go figure what the address is going to be after that...

Article: 114446
Subject: Re: small, free simple state machine processor suggestions?
From: jonas@mit.edu
Date: 16 Jan 2007 07:06:30 -0800
Links: << >>  << T >>  << A >>

Sean Durkin wrote:
> jonas@mit.edu wrote:
> > Has anyone found or could recommend a small(ish) processor for more
> > complex state machine tasks that is:
> >
> > 1. ~1000 LUTs or so (smaller is better)
> > 2. available under a free license (say, GPL, LPGL, BSD)
> > 3. available in vhdl?
> >
> > Ideally something like picoblaze would probably do what I want, except
> > that it's not under any of the available licenses, and pacoblaze is
> > vhdl (and potentially an IP nightmare). I've found a bunch of small
> > processors on opencores and the like but many of them look
> > half-finished. Any recommendations? These state machines are driving me
> > mad!
> Lattice offers the Mico8 as OpenSource, available as Verilog and VHDL
> sources. Haven't tested it yet, so I can't comment on it at all. Plus I
> don't know if it uses specific features for Lattice-parts or can be
> synthesized for any architecture.
>
> Just have a look at the website:
>
> http://www.latticesemi.com/products/intellectualproperty/referencedesigns/8bitmicrocontrollermico8.cfm
>
> --
> My email address is only valid until the end of the month.
> Go figure what the address is going to be after that...


Wow, so their license actually looks very reasonable and BSD-like. I'm
going to e-mail them and ask if their license allows the incorporation
of their code into a GPL'd project -- a casual reading suggests yes,
although IANAL.

And you're right, it could rely on lattice-specific primitives and the
like. But if not, wow, it'll work great. 

...Eric


Article: 114447
Subject: Re: Digital Filter and external PLL (VCO)
From: "axalay" <axalay@gmail.com>
Date: 16 Jan 2007 07:40:57 -0800
Links: << >>  << T >>  << A >>

> The loop filter of a PLL/DLL may help here. So you'd build a "analog"
> PLL with only a phasecomparator+loopfilter and a VCO. How is the jitter
> spectrally distributed ? Design the loop filter appropriately.
> Doing it completely in the FPGA may also work, but is limited by the
> maximum clock you can do to maybe >1ns jitter with a "multiphase clock
> design" or similar.

I am generate 2.048 MGz from (19.44 * 8) MGz so:

//=CC=EE=E4=F3=EB=FC =F4=EE=F0=EC=E8=F0=F3=E5=F2 =E8=E7 155.52 =CC=C3=F6 8.=
192 =CC=C3=F6
//=C4=EB=FF =FD=F2=EE=E3=EE =ED=E5=EE=E1=F5=EE=E4=E8=EC=EE =E2=FB=E4=E0=F2=
=FC 126 =F0=E0=E7 10
=EF=E5=F0=E8=EE=E4=EE=E2 =E8 130 =F0=E0=E7 9 =EF=E5=F0=E8=EE=E4=EE=E2
//4 =EB=E8=F8=ED=E8=F5 9 =EF=E5=F0=E8=EE=E4=EE=E2 =E2=FB=E4=E0=E5=EC =ED=E0=
 1-=E9, 64-=E9,
128-=E9 =E8 193-=E9 =F0=E0=E7=FB
module divide_clk (RESET, iCLK, oCLK);
	input RESET;
	input iCLK;

	output oCLK; reg oCLK;

	reg [7:0] aCOUNT; //=D1=F7=E5=F2=F7=E8=EA
	reg [4:0] bCOUNT; //=D1=F7=E5=F2=F7=E8=EA =E8=ED=F2=E5=F0=E2=E0=EB=E0 9 =
=E8=EB=E8 10 CLK

always @(posedge iCLK) begin
	if (!RESET) begin
		oCLK =3D 0;
		aCOUNT =3D 0;
		bCOUNT =3D 0;
	end //if
	else begin
		if (aCOUNT <=3D 63 || (aCOUNT >=3D 128 && aCOUNT <=3D 191)) begin
			if (aCOUNT =3D=3D 0 || aCOUNT =3D=3D 128 || aCOUNT[0] =3D=3D 1) begin
				if (bCOUNT < 17) begin
					if (bCOUNT =3D=3D 8) oCLK =3D 1;
					bCOUNT =3D bCOUNT + 1;
				end
				else begin
					oCLK =3D 0;
					bCOUNT =3D 0;
					aCOUNT =3D aCOUNT + 1;
				end
			end //if
			else if (aCOUNT[0] =3D=3D 0) begin
				if (bCOUNT < 19) begin
					if (bCOUNT =3D=3D 9) oCLK =3D 1;
					bCOUNT =3D bCOUNT + 1;
				end
				else begin
					oCLK =3D 0;
					bCOUNT =3D 0;
					aCOUNT =3D aCOUNT + 1;
				end
			end //else if
		end //if
		else begin
			if (aCOUNT[0] =3D=3D 1) begin
				if (bCOUNT < 19) begin
					if (bCOUNT =3D=3D 9) oCLK =3D 1;
					bCOUNT =3D bCOUNT + 1;
				end
				else begin
					oCLK =3D 0;
					bCOUNT =3D 0;
					aCOUNT =3D aCOUNT + 1;
				end
			end //if
			else begin
				if (bCOUNT < 17) begin
					if (bCOUNT =3D=3D 8) oCLK =3D 1;
					bCOUNT =3D bCOUNT + 1;
				end
				else begin
					oCLK =3D 0;
					bCOUNT =3D 0;
					aCOUNT =3D aCOUNT + 1;
				end
			end //else
		end //else
	end //else
end //always

endmodule //divide_clk


Article: 114448
Subject: Re: small, free simple state machine processor suggestions?
From: Herbert Kleebauer <klee@unibwm.de>
Date: Tue, 16 Jan 2007 17:44:06 +0200
Links: << >>  << T >>  << A >>
jonas@mit.edu wrote:
 
> Has anyone found or could recommend a small(ish) processor for more
> complex state machine tasks that is:
> 
> 1. ~1000 LUTs or so (smaller is better)

If you want a real small 16 bit processor (65 Flip Flops and about 250 gates):
ftp://137.193.64.130/pub/mproz/

> 2. available under a free license (say, GPL, LPGL, BSD)

Don't think that 65 FF can have a license at all.

> 3. available in vhdl?

No, but shouldn't be a big problem to implement it in VHDL.


Article: 114449
Subject: Re: small, free simple state machine processor suggestions?
From: jonas@mit.edu
Date: 16 Jan 2007 08:43:15 -0800
Links: << >>  << T >>  << A >>
> that it's not under any of the available licenses, and pacoblaze is
> vhdl (and potentially an IP nightmare). I've found a bunch of small

By which I meant "pacoblaze is verilog". Alas. Of course, the synthesis
tools can interoperate, but the low-budget simulators (such as symphony
eda) cannot.




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