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On Feb 8, 10:16 am, "pomer...@hotmail.com" <pomer...@hotmail.com> wrote: > On Feb 8, 2:40 am, "vlsi_learner" <baj...@gmail.com> wrote: > > > On Feb 8, 3:38 pm, "vlsi_learner" <baj...@gmail.com> wrote: > > > > Hi, > > > > I have an DPRAM which has writes taking place at a certain freq on > > > port A (100 Mhz) & reads with a gated clock which is derived from the > > > 100 Mhz clock(from port B) . The signal generating the gated clock > > > does not follow a uniform pattern. How can I calculate the size of > > > DPRAM reqd? > > > > Thanks in advance > > > Sorry had to repost it.There is a correction . The enable signal for > > the clock does not follow a uniform pattern > > If I understand your problem correctly, you have data coming in faster > that it is going out. To answer your question, I need to know how > long the DPRAM will be running. No dpram depth can handle such situation without losing the data when incoming sustain rate is faster than its going out, don't read other guys posts, they seem having a party going on :)). Anyway can you tell more about how your in/out data behave? How many incoming bytes are there, per 1) 1 us 2) 1 ms 3) 1 sec 4) 1 minute 5) 1 hour 6) 1 day 7) 1 month 8) 1 year ... Same question for out going data. When you answer these two questions you would also figure out the requirement depthArticle: 115376
hi i am implementing DCT and IDCT on FPGA can any body give me some specific Block diagram you can send me the details on the mail id prakash.akkasali@gmail.comArticle: 115377
sudheer wrote: > To declare and initialise a one-bit register in verilog we use the > following statement > reg one_bit_reg=1'b0; > > Similarly, to declare and initialise a one dimension reg (e.g. 8-bit) > we can write > reg [7:0] reg_len_8=8'd0; > > We can declare a two dimensional array (e.g. 16x8-bit) as > reg [7:0] reg_dim_2 [15:0]; > > But how can we initialise this array in the same statement? > or How do we declare the initial state (known non-zero values) of an > array without using extra logic (especially when implementing on > hardware (FPGAs))? > For simulation purposes, you may use an init loop: initeger i; init for (i=0;i<16;i=i+1) reg_dim_2 = 0; For synthesis, the RAM will be initialized automatically to zero in an FPGA. You may initialize to nonzero values using $readmemh: init $readmemh(reg_dim_2,"init_file.txt"); The init file contains hex values with which to load the RAM. This works in Synplify; not sure about other synthesizers. -KevinArticle: 115378
Hi, just search online help for black box attributes: syn_black_box, syn_tsu, syn_tco, syn_tpd. Online Help has appropriate information and also VHDL/Verilog examples. Bye, PhilArticle: 115379
Hi Pablo,
Pablo wrote:
> On 8 feb, 05:00, John Williams <jwilliams@itee.uq.edu.au> wrote:
>
>>Instead of this, I recommend you start using PetaLinux:
>>
>>http://developer.petalogix.com
>>
> I want to implement an application over a FPGA. In the app I need to
> use "Condition Variables" with Pthread, but Xilkernel does not support
> for this. So I have thought in uClinux. Could I compile my app with
> functions such as "pthread_cond_init", "pthread_cond_wait" over
> uClinux??
We are using uClibc, which includes the LinuxThreads library for
pthreads support. Condition variables are included in the linuxthreads
functionality - the full API from the source is below.
I hope this answers your question.
[jwilliams@g512-9423 linuxthreads]$ grep "pthread_cond.*(" condvar.c
int pthread_cond_init(pthread_cond_t *cond,
int pthread_cond_destroy(pthread_cond_t *cond)
int pthread_cond_wait(pthread_cond_t *cond, pthread_mutex_t *mutex)
pthread_cond_timedwait_relative(pthread_cond_t *cond,
int pthread_cond_timedwait(pthread_cond_t *cond, pthread_mutex_t *mutex,
return pthread_cond_timedwait_relative(cond, mutex, abstime);
int pthread_cond_signal(pthread_cond_t *cond)
int pthread_cond_broadcast(pthread_cond_t *cond)
int pthread_condattr_init(pthread_condattr_t *attr)
int pthread_condattr_destroy(pthread_condattr_t *attr)
int pthread_condattr_getpshared (const pthread_condattr_t *attr, int
*pshared)
int pthread_condattr_setpshared (pthread_condattr_t *attr, int pshared)
Regards,
John
Article: 115380Dear all, Do you know how to read CLB information from NCD file to a readable text file ? I"m using Xilinx ISE8.1i to do mapping, I know there is a program called ncdread, i can't find it in ISE8.1i (i found ncdread in ISE6.1i, but this can't convert NCD file to text file for ISE8.1i's output) Could anyone help me ? Thank you very much ! Regards, Chi WaiArticle: 115381
Hi, yuchiwai@gmail.com wrote: > Do you know how to read CLB information from NCD file to a readable > text file ? > I"m using Xilinx ISE8.1i to do mapping, I know there is a program > called ncdread, i can't find it in ISE8.1i (i found ncdread in > ISE6.1i, but this can't convert NCD file to text file for ISE8.1i's > output) passing the '-l' option to bitgen will give you an ASCII logic allocation file, maybe this is what you are after? JohnArticle: 115382
Hello,
I can't meet the following constraint after playing around w/ some
synthesis and implementation settings. Any specific advice as it
relates to this delay path?
I'm also a bit unsure how it's calculating this path. The signals are
connected as follows:
fifo_full -> [combinational logic] -> usr_tx_ack -> next_st
(combinational logic) -> curr_st (register)
Any ideas why it's reporting the path this way?
Thanks,
-Brandon
================================================================================
Timing constraint: TS_clkgen_ifclk200 = PERIOD TIMEGRP
"TG_clkgen_ifclk200" 5 ns HIGH 50%;
9757 items analyzed, 50 timing errors detected. (50 setup errors, 0
hold errors)
Minimum period is 5.630ns.
--------------------------------------------------------------------------------
Slack: -0.630ns (requirement - (data path - clock
path skew + uncertainty))
Source: ctrl_inst/curr_st_FFd4 (FF)
Destination: ctrl_inst/fifo_inst/BU2/U0/gen_as.fgas/
normgen.memblk/mem1nc.coreinst/BU1023 (RAM)
Requirement: 5.000ns
Data Path Delay: 5.435ns (Levels of Logic = 3)
Clock Path Skew: -0.135ns
Source Clock: clkgen_ifclk200 rising at 0.000ns
Destination Clock: clkgen_ifclk200 rising at 5.000ns
Clock Uncertainty: 0.060ns
Timing Improvement Wizard
Data Path: ctrl_inst/curr_st_FFd4 to ctrl_inst/fifo_inst/BU2/U0/
gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU1023
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.360 ctrl_inst/curr_st_FFd4
net (fanout=23) 0.677 ctrl_inst/curr_st_FFd4
Tilo 0.194 ctrl_inst/curr_st_Out391
net (fanout=3) 0.604 ctrl_inst/usr_tx_ack
Tilo 0.195 ctrl_inst/fifo_inst/BU2/U0/
gen_as.fgas/normgen.memblk/tmp_ram_rd_en1
net (fanout=18) 1.052 ctrl_inst/fifo_inst/BU2/U0/
gen_as.fgas/normgen.memblk/tmp_ram_rd_en
Tilo 0.194 ctrl_inst/fifo_inst/BU2/U0/
gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU163
net (fanout=14) 1.641 ctrl_inst/fifo_inst/BU2/U0/
gen_as.fgas/normgen.memblk/mem1nc.coreinst/N1881
Trcck_ENB 0.518 ctrl_inst/fifo_inst/BU2/U0/
gen_as.fgas/normgen.memblk/mem1nc.coreinst/BU1023
---------------------------- ---------------------------
Total 5.435ns (1.461ns logic, 3.974ns route)
(26.9% logic, 73.1% route)
Article: 115383yuchiwai@gmail.com wrote: > Dear all, > Do you know how to read CLB information from NCD file to a readable > text file ? > I"m using Xilinx ISE8.1i to do mapping, I know there is a program > called ncdread, i can't find it in ISE8.1i (i found ncdread in > ISE6.1i, but this can't convert NCD file to text file for ISE8.1i's > output) > > Could anyone help me ? > > Thank you very much ! > > Regards, > Chi Wai > You may use an executable called XDL that comes with ISE. It can convert an NCD to an XDL, which is human-readable. -KevinArticle: 115384
Use xdl: xdl -ncd2xdl design.ncd If you just want the clb info, run it on the ncd that the mapper creates. Steve <yuchiwai@gmail.com> wrote in message news:1170976910.579417.38680@k78g2000cwa.googlegroups.com... > Dear all, > Do you know how to read CLB information from NCD file to a readable > text file ? > I"m using Xilinx ISE8.1i to do mapping, I know there is a program > called ncdread, i can't find it in ISE8.1i (i found ncdread in > ISE6.1i, but this can't convert NCD file to text file for ISE8.1i's > output) > > Could anyone help me ? > > Thank you very much ! > > Regards, > Chi Wai >Article: 115385
Thanks all !!! This is the solution which I wanted !!! Regards, Chi Wai On 2=A4=EB8=A4=E9, =A4U=A4=C811=AE=C959=A4=C0, <steve.l...@xilinx.com> wrot= e: > Use xdl: > xdl -ncd2xdl design.ncd > If you just want the clb info, run it on the ncd that the mapper creates. > > Steve > > <yuchi...@gmail.com> wrote in message > > news:1170976910.579417.38680@k78g2000cwa.googlegroups.com... > > > > > Dear all, > > Do you know how to read CLB information from NCD file to a readable > > text file ? > > I"m using Xilinx ISE8.1i to do mapping, I know there is a program > > called ncdread, i can't find it in ISE8.1i (i found ncdread in > > ISE6.1i, but this can't convert NCD file to text file for ISE8.1i's > > output) > > > Could anyone help me ? > > > Thank you very much ! > > > Regards, > > Chi Wai- =C1=F4=C2=C3=B3Q=A4=DE=A5=CE=A4=E5=A6r - > > - =C5=E3=A5=DC=B3Q=A4=DE=A5=CE=A4=E5=A6r -Article: 115386
On Feb 8, 10:29 am, me_2...@walla.co.il wrote: > unlicensed environment at the 5G band (such as wi-fi). You do realize that "unlicensed" does not mean "no type approval is required", merely "once the product is type approved, the individual user is not required to obtain a license", right? It is not a free for all in the 5GHz band. > This pulse will be connected to an A/D (at the IF band) and will try > to detect the pulses power and also measure their repetition It's not clear why you think an FPGA is required to do this. All that is required is a (very) fast timer.Article: 115387
I have a custom IP module connected to an FSL. I connect the FSL_M_Data and FSL_M_Write to signals in my IP. The data bus is ONLY 8 bits wide. I edited the populated mpd file to take out the slave FSL signals and bus refences (I don't need it in the custom IP), and I changed the bus width on the the data signal to 8 bits. I added an fsl xilinx core to the project and connected the M_Clk, S_Clk, RST, and Has_Data as appropriate. The S_Clk is connected to the OPB clock and the M_Clk is connected to the same clock that the custom logic is clocked with. The bus connections connect the custom IP as the master and the slave side is attached to the microblaze. The custom IP asserts a signal when data is valid. That signal is connected to the M_Write signal. So when that is high, ONE BYTE of data is written on every clock. I am then using a little RS-232 terminal to experiment with reads. When I press the 'r' key, the code issues a 'mb_nbread' command and prints the byte out on the terminal. The problem is that the bytes I read back are not what 'should' be written into the FSL FIFO. I am scoping (via ChipScope) the clocks, M_Write, and M_Data, and FSL_Has_Data. They all appear to be working right. I can hit 'r' as many times as there were bytes written and the FSL_Has_Data goes low as expected. Like I said, the bytes back are incorrect. Once FSL_Has_Data goes low (after 'reading' all the bytes), I can repeatedly hit 'r' and the data returned is 'B8'. I am probably doing something wrong. Does anyone have any advice? My concern is that the Import/Create wizard will not let me specify my specific setup. I have to hack it up to make the data width 8 bits. And I have to hack it up to take the slave link out of the custom IP. Thanks!Article: 115388
Another option is to replace the LUT with an SRL16E. The SRL16E behaves exactly like a LUT when the WE input is low, with the advantage of having the pins inherently locked. Additionally, it can be reloaded without having to use the FPGA configuration logic, i.e. it provides a poor-man's reconfigurability for the logic. I've used this for years for reloading coefficients in DA FIR filters. By keeping the "reconfiguration" within the operational part of the FPGA, you save yourself a ton of heartache. The logic required to reconfigure an SRL16E LUT is pretty simple too.Article: 115389
Is there a standard used for look-up table access time in terms of levels of logic? As an example, if I have a 2^8 x 8 look-up table (8- bit to 8-bit), how many levels of logic are required to perform the look-up operation or is the table considered to be just one level of SRAM? Thanks! AdamArticle: 115390
Hi There! I am designing a digital AM/FM receiver in a Vertex-4 FPGA. I have designed the system blocks but have one question regarding digital filtering. >From a systemic point of view, we are using the DDC approach to convert IF 45MHz down to baseband. After this we are using a 40MSPS A/ D to sample and output parallel 12-bit I, Q data to the FPGA. The FPGA front end has to have a LPF with a cut-off frequency of 5kHz. After the LPF, AM and FM need to be demodulated. I intend to do demodulation as follows FM -> (Q(n)I(n-1) - I(n)Q(n-1))/(I-Sq + Q-Sq) AM -> (I-Sq + Q-Sq) My question is: I need to do some decimation (to make my life easier when it comes to 5kHz LPF design)...what is the best way of doing this? I have read some material and it seems to point towards cascaded CIC filters. Please comment and also let me know if you notice any flaw in my design methodology. Moreover, due to my inexperience in this field, I wanted to know if decimation upstream would affect (adversely) my AM/ FM demodulation process. cheers MorpheusArticle: 115391
Joseph Samson wrote: > Sheesh, How can this guy learn with examples like that? Try this: > > My teammate and I run a race. He runs the mile 5 seconds faster than I > do. What size hat should I buy? Red, obviously, unless there is a full moon.Article: 115392
Tim wrote: > Daniel O'Connor wrote: >> I am also considering taking the 50MHz clock on my board and multiplying >> it up to, say, 150MHz and sychronising/one-shotting all of the signals >> from the other board to that. > > Yep. That's the what you have to do. All other routes lead to madness. > Synchronize the incoming signals and as much of the rest as possible. I > would look hard at making the FIFO synchronous. I guess that explains the pounding headaches then ;) -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 115393
Your example is a 256 x 8 = 2048 bit LUT, which is best implemented in a Xilinx BlockRAM. The BlockRAM is a synchronous device, so it has a specified address set-up time and a specified clock-to-out time. There is only one level of such delays. The multi-level decoding delay is hidden in the BlockRAM access time. If you want to implement such a LUT in 4-input LUTs, you need more than 128 LUTs and probably 5 layers of LUT delays, but a clock is not necessary Virtex-5 has 6-input LUTs,and you need only 40 LUTs total, with a two- LUT combinatorial delay, and no clock. Your choice. Peter Alfke, Xilinx ================== AdamE wrote: > Is there a standard used for look-up table access time in terms of > levels of logic? As an example, if I have a 2^8 x 8 look-up table (8- > bit to 8-bit), how many levels of logic are required to perform the > look-up operation or is the table considered to be just one level of > SRAM? > > Thanks! > > AdamArticle: 115394
Hi, Hard to tell what can be wrong here without all the implementation details. One thing, there is no need to change the data size to a byte. Let it be 32 bit and drive the other 24 bits as '0'. That would remove one possible source of the error. Can you simulate this? Göran "motty" <mottoblatto@yahoo.com> wrote in message news:1170987918.887116.237390@v45g2000cwv.googlegroups.com... >I have a custom IP module connected to an FSL. I connect the > FSL_M_Data and FSL_M_Write to signals in my IP. The data bus is ONLY > 8 bits wide. I edited the populated mpd file to take out the slave > FSL signals and bus refences (I don't need it in the custom IP), and I > changed the bus width on the the data signal to 8 bits. > > I added an fsl xilinx core to the project and connected the M_Clk, > S_Clk, RST, and Has_Data as appropriate. The S_Clk is connected to > the OPB clock and the M_Clk is connected to the same clock that the > custom logic is clocked with. The bus connections connect the custom > IP as the master and the slave side is attached to the microblaze. > > The custom IP asserts a signal when data is valid. That signal is > connected to the M_Write signal. So when that is high, ONE BYTE of > data is written on every clock. I am then using a little RS-232 > terminal to experiment with reads. When I press the 'r' key, the code > issues a 'mb_nbread' command and prints the byte out on the terminal. > > The problem is that the bytes I read back are not what 'should' be > written into the FSL FIFO. I am scoping (via ChipScope) the clocks, > M_Write, and M_Data, and FSL_Has_Data. They all appear to be working > right. I can hit 'r' as many times as there were bytes written and > the FSL_Has_Data goes low as expected. > > Like I said, the bytes back are incorrect. Once FSL_Has_Data goes low > (after 'reading' all the bytes), I can repeatedly hit 'r' and the data > returned is 'B8'. I am probably doing something wrong. Does anyone > have any advice? > > My concern is that the Import/Create wizard will not let me specify my > specific setup. I have to hack it up to make the data width 8 bits. > And I have to hack it up to take the slave link out of the custom IP. > > Thanks! >Article: 115395
morpheus skrev: > Hi There! > I am designing a digital AM/FM receiver in a Vertex-4 FPGA. I have > designed the system blocks but have one question regarding digital > filtering. >>From a systemic point of view, we are using the DDC approach to > convert IF 45MHz down to baseband. After this we are using a 40MSPS A/ > D to sample and output parallel 12-bit I, Q data to the FPGA. > The FPGA front end has to have a LPF with a cut-off frequency of 5kHz. > After the LPF, AM and FM need to be demodulated. I intend to do > demodulation as follows > FM -> (Q(n)I(n-1) - I(n)Q(n-1))/(I-Sq + Q-Sq) > AM -> (I-Sq + Q-Sq) > My question is: > I need to do some decimation (to make my life easier when it comes to > 5kHz LPF design)...what is the best way of doing this? I have read > some material and it seems to point towards cascaded CIC filters. > Please comment and also let me know if you notice any flaw in my > design methodology. Moreover, due to my inexperience in this field, I > wanted to know if decimation upstream would affect (adversely) my AM/ > FM demodulation process. > > cheers > Morpheus > Hi Morpheus, I designed a digital AM/FM receiver on a Virtex-2 FPGA a couple of years ago. Since I had a 210 Msps ADC (12 bits resolution) before the FPGA I did not do any DDC before the device. Instead I used a DDS internally and mixed the desired frequency down to baseband. For the decimation I used CIC filters in two stages and it worked good. I decimated the signal from ~200 MHz to about 128 kHz which was much more convenient for LP filtering. The CIC filters them selves has some LP properties too. To extract the amplitude and phase from the I and Q I used a Cordic. Then it was quite easy to calculate the phase difference, and the amplitude is given. Good luck! /JohanArticle: 115396
Yes, I know how to use the attributes. What I don't know is what value to assign to them. If I put a one nanosecond delay for each of them (tsu, tco and tpd), is that too much or too little for the particular FIFO I need in the particular FPGA I use (APA300)? What I need is the values for the delays. If they are included into a library and I don't need to assign them myself it would be even better (and I don't see why Actel wouldn't provide us with that), but at the very least I hope they provide the values somewhere, since I can't possibly measure them myself. On 8 feb, 21:09, phil <mountaineer...@web.de> wrote: > Hi, > > just search online help for black box attributes: syn_black_box, syn_tsu, syn_tco, syn_tpd. > > Online Help has appropriate information and also VHDL/Verilog examples. > > Bye, PhilArticle: 115397
> fifo_full -> [combinational logic] -> usr_tx_ack -> next_st > (combinational logic) -> curr_st (register) > > Any ideas why it's reporting the path this way? Maybe you're looking at the wrong path. To me it looks as if the report is about doing a FIFO write from one of your states. Regards MarcArticle: 115398
On Feb 8, 3:17 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On 7 Feb 2007 03:34:28 -0800, "Tony Thai" <tony.uniqu...@gmail.com> > wrote: > > >Hi All, > > >Hopefully this is a simple fix... > >I complied Xilinx simulation libraries with COMPXLIB... and it seemed > >to worked fine. > >The modelsim.ini was changed to point to the new libraries. > > Which modelsim.ini? > > Typically modelsim creates one in each working directory; that in force > when you invoked compxlib may NOT be the same as the one in your project > working directory. > > You may need to edit the unisim library mapping into your project's > modelsim.ini, or even delete an incorrect one if you acquired the > project from somebody else... > > - Brian Hi Brian, Thanks for the help. I checked (by doing a search), and I only have 1 modelsim.ini file under the install directory. with the vlog command, do I have to use the "-y" or "-v" or some other option to tell the tool to look for the "Referenced (but uncompiled) modules or primitives" in the library dir? It seems like I have to.. don't I. If someone has used a xilinx modules, do you compile (vlog) with any options? if yes, can you post an example. if not, can you post what directory your unisims_ver libraray in your modelsim.ini points to. I want to compare if it is the same as mine: UNISIMS_VER = C:\Xilinx91i \verilog\mti_se\unisims_ver Thanks, -TonyArticle: 115399
On 8 Feb., 08:26, "Andreas Gauckler" <gauck...@fh-furtwangen.de> wrote: > Hello > > yesterday I ' ve tried to install ISE 9.1 on a openSuSE 10.2 system. > Unfortunately the installation crashs after about 60% without messages. > > I tried a different installation source -- same result. > > Has someone any experience with openSuSE 10.2 and Xilinx ISE 9.1 > installation ? > > Best regards > > Andreas Solved !! Installation succeeded !! I doubled ram to 1GB, I increased swap partition to 5G and I changed openSuSE 10.2 Distribution from easyLinux to Novel Distribution. Andreas
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