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Hello, I would really appreciate if you could give me some insight on the following -Can you guide me to a link/example which runs thru the process of dynamic reconfiguration on Virtex2/4 step by step.I read and understood the paper you guys pointed to. http://www.itee.uq.edu.au/~listarch/partial-reconfig/archive/2006/04/msg00009.html I have also read the documentation on the Xilinx website(userguide etc).I would like to see an example implementation(could be trivial example).Else if you guys could give me some suggestions on a trivial example for me to test and see that partial dynamic reconfig actually works using the ICAP. -Also,from the paper I would assume that the patial bitstreams would be generated using the FPGA editor from Xilinx.Now assuming I want to have a set of bit streams loaded on to the Internal memory buffer of the microblaze,How do I do that i.e how do I store the bit streams on the microblaze(internal memory).I am using an ML310 board. Thanks!Article: 117501
I have an application that is very space limited, and would like to use a Spartan XC3S250E in the VQ100 package. Even this package has more I/O than I need. (I need a lot of logic, but communication is via SPI and RS232 - about 10 I/O total) I can find the 3S100E's in this package from most distributors, but not the 3S250E. I only need four total, and I could probably squeeze a TQ144 package in if I got creative with parts placement, but the PQ208 absolutely won't fit. Also, since these are prototypes, I would like avoid BGA's. The cost to have them fitted is just too high. BTW - if anyone from Xilinx is reading this, this is why it would be nice if your online store was actually a "store", and not just a link to Avnet and Nu Horizons. Thanks!Article: 117502
radarman <jshamlet@gmail.com> wrote: > I have an application that is very space limited, and would like to > use a Spartan XC3S250E in the VQ100 package. Even this package has > more I/O than I need. (I need a lot of logic, but communication is via > SPI and RS232 - about 10 I/O total) > I can find the 3S100E's in this package from most distributors, but > not the 3S250E. > I only need four total, and I could probably squeeze a TQ144 package > in if I got creative with parts placement, but the PQ208 absolutely > won't fit. > Also, since these are prototypes, I would like avoid BGA's. The cost > to have them fitted is just too high. > BTW - if anyone from Xilinx is reading this, this is why it would be > nice if your online store was actually a "store", and not just a link > to Avnet and Nu Horizons. Complain loud and complain often... I did the same for the XC3S500E in PQ208 on Electronica 2006, Embedded World 2007 and in this group and now the forecast on digikey promises the parts to be available on April 21... But probably totaly unrelated... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 117503
I am trying to perform a Post-Translate simulation of a design, but I'm getting a huge number of errorts that are basically a replication of these following 3 erros: # ** Error: netgen/translate/FPGA_translate.vhd(8083): No actual specified for gsr. # ** Error: netgen/translate/FPGA_translate.vhd(29201): (vcom-1142) 'x_obuft' is an unknown component name. # ** Error: netgen/translate/FPGA_translate.vhd(29202): Statement cannot be labeled. Can anybody help resolving these errors? I couldnt find anything on the internet or Xilinx website. I'm using Xilinx 9.1i with ModelSim XE III/Starter 6.0a Thank you!Article: 117504
Honestly I think that if you have no hardware experience, this will be quite a challenge. Not to say that it's impossible but you're certainly going to have a few sleepness nights... In your case, I would rather suggest an all-software solution. One idea would be to use a PS3 and harness the power of the Cell processor (you can run linux on it I believe). The issue is to parallelize your algorithm enough to harness the power of the 9 cores (similar problem than if you were going to an FPGA solution). If one PS3 is not enough, maybe you could use 2, or 4... You could build a smaller cluster for not too much money. My 2 =A2. PatrickArticle: 117505
PS3? I'm sure you haven't tried to code for the PS3 before. Even IBM officials admit that PS3 coding is a very painful experience. In the same vein, I would recommed you look into programming on a video card. NVIDIA teaches a new course here that gives an idea how to take advantage of the massively parallel nature of the video card architecture. The idea of using the video card in this manner is still relatively new (there was a Stanford project a few years ago that worked on this issue) so the software support is still limited, but probably still better than working with the PS3. Also if you baulk at shelling out the money for an FPGA dev board, a PS3 is beyond your price range. But, you may be able to get some high-end SLI video cards if your school teaches a grapghics course. Actually, I bet the video card solution would be much better than any other proposed solution. Good luck, ---Matthew Hicks > Honestly I think that if you have no hardware experience, this will be > quite a challenge. Not to say that it's impossible but you're > certainly going to have a few sleepness nights... > > In your case, I would rather suggest an all-software solution. One > idea would be to use a PS3 and harness the power of the Cell processor > (you can run linux on it I believe). The issue is to parallelize your > algorithm enough to harness the power of the 9 cores (similar problem > than if you were going to an FPGA solution). If one PS3 is not enough, > maybe you could use 2, or 4... You could build a smaller cluster for > not too much money. > > My 2 ¢. > > Patrick >Article: 117506
On Apr 2, 4:27 pm, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > radarman <jsham...@gmail.com> wrote: > > I have an application that is very space limited, and would like to > > use a Spartan XC3S250E in the VQ100 package. Even this package has > > more I/O than I need. (I need a lot of logic, but communication is via > > SPI and RS232 - about 10 I/O total) > > I can find the 3S100E's in this package from most distributors, but > > not the 3S250E. > > I only need four total, and I could probably squeeze a TQ144 package > > in if I got creative with parts placement, but the PQ208 absolutely > > won't fit. > > Also, since these are prototypes, I would like avoid BGA's. The cost > > to have them fitted is just too high. > > BTW - if anyone from Xilinx is reading this, this is why it would be > > nice if your online store was actually a "store", and not just a link > > to Avnet and Nu Horizons. > > Complain loud and complain often... > > I did the same for the XC3S500E in PQ208 on Electronica 2006, Embedded World > 2007 and in this group and now the forecast on digikey promises the parts > to be available on April 21... > > But probably totaly unrelated... > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- looks like xilinx marketing people are doing a horrible job, I have a product with XC3S400 in PQ pakage, but can't get it from anywhere, Altera seems much better, if switching parts is not your concern, altera has plenty of pq144, pq208 pakage to choose from. jetArticle: 117507
"radarman" <jshamlet@gmail.com> wrote in message news:1175547385.428898.143910@o5g2000hsb.googlegroups.com... >I have an application that is very space limited, and would like to > use a Spartan XC3S250E in the VQ100 package. Even this package has > more I/O than I need. (I need a lot of logic, but communication is via > SPI and RS232 - about 10 I/O total) > > I can find the 3S100E's in this package from most distributors, but > not the 3S250E. > > I only need four total, and I could probably squeeze a TQ144 package > in if I got creative with parts placement, but the PQ208 absolutely > won't fit. > > Also, since these are prototypes, I would like avoid BGA's. The cost > to have them fitted is just too high. > > BTW - if anyone from Xilinx is reading this, this is why it would be > nice if your online store was actually a "store", and not just a link > to Avnet and Nu Horizons. > > Thanks! This is where a distributor/sales contact (distributor FAE, for instance) can really help out. Even if you're "small potatoes" for their business, they should be able to tell you about availability. The online store *would* be a tremendous resource if it was in a usable state.Article: 117508
On Apr 2, 6:10 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > PS3? I'm sure you haven't tried to code for the PS3 before. Even IBM officials > admit that PS3 coding is a very painful experience. Really? That's too bad. The Cell seems like a nice processor. I met a guy recently at a conference who was considering using the Cell for an hyperspectral imaging application. I thought it was a good idea but I was not aware of its difficult programming. But programming FPGAs is not easy either... > In the same vein, I > would recommed you look into programming on a video card. NVIDIA teaches > a new course here that gives an idea how to take advantage of the massively > parallel nature of the video card architecture. The idea of using the video > card in this manner is still relatively new (there was a Stanford project > a few years ago that worked on this issue) so the software support is still > limited, but probably still better than working with the PS3. Good idea. One guy in my lab did a summer project to do FFTs in Matlab on a vid card: http://www.mathworks.com/matlabcentral/fileexchange/loadFile.do?objectId=12391 You might also want to check out these links: http://digg.com/hardware/New_NVIDIA_compiler_lets_developers_offload_math_functions_to_GPU_2 http://www.gpgpu.org/ If you still insist on using FPGAs, maybe you could consider using a tool like System Generator. There seems to be an interesting presentation titled "Introduction to the DSP Video Starter Kit and Video Co-processing Kit" here: http://www.demosondemand.com/clients/xilinx/001/page/index_dsp.asp PatrickArticle: 117509
I can't comment on Linux, but I could never get the compilation wizard to work in Windows. What I had to do was compile the ISE libraries using its wizard. That worked fine. Then I had to use the command line interface tool to compile the EDK simulation libraries. I don't know if this will help you, but I spun my wheels trying to get the wizard to work and this is what I ended up doing.Article: 117510
When trying to run the WebPack ISE 9.1i SP3 simulator on Linux (Gentoo,
specifically), it always stops building the simulation executable with
a message such as:
Building counter_tbw_isim_beh.exe
Nothing further happens. This reproducible on uni-core (Pentium M) as
well as dual-core (Core 2 Duo) machines.
Any hints on how to resolve this are appreciated. For reference, this
Gentoo version has both GCC 4.1.1 and 3.3.6 installed, the behavior
does not change when switching between versions (via gcc-config).
Note that the rest of the ISE tools (map, par, xst etc.) work
perfectly. Only the Project Navigator/simulator integration appears flaky.
Andreas Koch
--
Prof. Dr. Andreas Koch koch@esa.informatik.tu-darmstadt.de
Technische Universitaet Darmstadt, FB20 Phone : x49-6151-16-4378
FG Embedded Systems and their Applications (ESA) FAX : x49-6151-16-5472
Hochschulstr. 10, D-64289 Darmstadt, Germany * PGP key available *
From dave@comteck.com Mon Apr 02 20:59:01 2007
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From: Dave <dave@comteck.com>
Subject: Re: Dear Xilinx
Date: Mon, 02 Apr 2007 23:59:01 -0400
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On Mon, 02 Apr 2007 10:54:30 +0200, Benjamin Todd wrote:
> Interesting that...
> http://download.micron.com/pdf/datasheets/dram/ddr/512MBDDRx4x8x16.pdf
>
> If you read the differences between these memories, you see that the -5B is
> DDR400... whereas the -6 is DDR333...
>
> Do you know whether the clock rate is 200M or 133-167M for the starter kit?
The Readme says 133 MHz.
> Actually, which starter kit are you using? I have a pile of kits, want to
> make sure I can't have the same problem...
Spartan-3E Starter Kit (HW-SPAR3E-SK-US)
<http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS>
~Dave~
From invalid@dont.spam Mon Apr 02 21:22:58 2007
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From: Phil Hays <invalid@dont.spam>
Subject: Re: ISE 9.1i SP3 simulator problems on Linux
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Xref: prodigy.net comp.arch.fpga:129117
Andreas Koch wrote:
> When trying to run the WebPack ISE 9.1i SP3 simulator on Linux (Gentoo,
> specifically), it always stops building the simulation executable with a
> message such as:
>
> Building counter_tbw_isim_beh.exe
>
> Nothing further happens. This reproducible on uni-core (Pentium M) as
> well as dual-core (Core 2 Duo) machines.
Is it reproducible on "Red Hat Enterprise Linux"? That is the supported
version.
If it is, you can file a webcase. If not, things get a lot harder.
If not, is there a test case you can post?
--
Phil Hays
Article: 117511Hi Austin, Answers are inline. On Apr 2, 6:55 pm, Austin Lesea <aus...@xilinx.com> wrote: > Mehdi, > > The autocal block should be automatically inserted for all DCM's, used > or unused by the software... 1. I think that autocal is not inserted automatically for STEPPING1. > > At least, that is what I had heard. > > As for the DRP port, if it is listed in the errata for that stepping, > then that is what that device (does not) delivers. Since DRP is used by autocal than it's not accessible by the user! > > Which device? What steppings? > > AustinArticle: 117512
hi people, I'm designing filter system called IIR filter on the FPGA kit, but it doesn't work when I implement on FPGA. When i iput the signals, the output results seem to not get any thing. I do not know whether my source code is wrong or another reason. The FPGA kit operate normally with other sources which i loaded in the past. Can anyone give me some advices to test what parts in my project do not work or give me some idea to test anything. I am in the mess. I hope everyone can show me. I am looking forward hearing from people soon,Article: 117513
Gordon Freeman wrote: > hi people, > > I'm designing filter system called IIR filter on the FPGA kit, but it > doesn't work when I implement on FPGA. When i iput the signals, the > output results seem to not get any thing. I do not know whether my > source code is wrong or another reason. The FPGA kit operate normally > with other sources which i loaded in the past. > > Can anyone give me some advices to test what parts in my project do > not work or give me some idea to test anything. I am in the mess. I > hope everyone can show me. > > I am looking forward hearing from people soon, Simulate your design. Watch the values change in the accumulators as you add and subtract the input values.Article: 117514
Hey Kolja, On 26 Mrz., 12:14, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > Matlab. Antoher one is a recent paper on a GI workshop that show how > easy it is to extend the synthesizable > subset of VHDL. They presented a VHDL to VHDL preprocessor that > allowed you to use more constructs in your > synthesizable code than Synopsys supports. Yet another example are > timing diagram editors for documentation. Can you point me to that paper? If "GI" stands for the german "Gesellschaft f=FCr Informatik", then I am a member and have missed the paper anyway ;-) Thanks, TorstenArticle: 117515
On Apr 3, 9:04 am, "Torsten Landschoff" <t.landsch...@gmx.de> wrote:
> Hey Kolja,
>
It was at "7. GI/ITG/GMM-Workshop Modellierung und Verifikation". I
just picked up the proceedings and was looking for the paper and
realised, that there were multiple papers that were trying to extend
the synthesizable part of the language.
The Paper that I had in mind used XSLT to transform VHDL to VHDL:
* Oetjens, Gerlach, Rosenstiel: "Ein XML-basierter Ansatz zur
flexiblen Darstellung und Transformation von Schaltungsbeschreibungen"
Than there was another paper about a more special case:
* Jan Gutsche, H.-U. Post: "Erh=F6hung der Synthesegenauigkeit durch
Sprachraumerweiterung synthesef=E4higer sequentieller VHDL-
Beschreibungen".
Less practical but especially enlightening was this paper:
* Meinrad Fiedler: "Ein =DCbersetzungsverfahren von Verilog-
Kausalspezifikationen in Signalflankengraph-basierte Spezifikationen
zum Entwurf asynchroner Schaltwerke".
What the author is presenting as a simple example does not look
remotely similar to anything that could be synthesized using Synopsys
DC.
This shows that what is to be considered "synthesizable" is largely in
the eye of the beholder.
always
begin
@(posedge c);
if (s)
begin
y =3D 1;
@(negedge c);
y =3D 0;
end
else
begin
z=3D1;
@(negedge c);
z=3D0;
end
end
> On 26 Mrz., 12:14, "comp.arch.fpga" <ksuli...@googlemail.com> wrote:
>
> > Matlab. Antoher one is a recent paper on a GI workshop that show how
> > easy it is to extend the synthesizable
> > subset of VHDL. They presented a VHDL to VHDL preprocessor that
> > allowed you to use more constructs in your
> > synthesizable code than Synopsys supports. Yet another example are
> > timing diagram editors for documentation.
>
> Can you point me to that paper? If "GI" stands for the german
> "Gesellschaft f=FCr Informatik", then I am a member and have missed the
> paper anyway ;-)
>
> Thanks, Torsten
Article: 117516Hello, I want to recompile the bootloader for the Nios processor. The reason that I want to do this is: - I use an EPCS flash - by default Nios code is situated directly after the FPGA bitstream - I want the Nios code to be in a different sector as the FPGA bitstream I guess that I will have to change boot_loader_epcs_bits.S for that. My first problem is to assemble these files. Has anybody done this before. How should I do use the MakeFile? thanks and best regards, KarelArticle: 117517
> I guess that I will have to change boot_loader_epcs_bits.S for that. > My first problem is to assemble these files. Has anybody done this > before. How should I do use the MakeFile? I did just that to verify the object files I was linking in were correct. And they were. I created a separate directory with the loader source. I used the make file that is located in the Altera boot loader directory. gmArticle: 117518
On a sunny day (2 Apr 2007 14:45:45 -0700) it happened "Patrick Dubois" <prdubois@gmail.com> wrote in <1175550345.009582.122910@y66g2000hsf.googlegroups.com>: >Honestly I think that if you have no hardware experience, this will be >quite a challenge. Not to say that it's impossible but you're >certainly going to have a few sleepness nights... > >In your case, I would rather suggest an all-software solution. One >idea would be to use a PS3 and harness the power of the Cell processor >(you can run linux on it I believe). The issue is to parallelize your >algorithm enough to harness the power of the 9 cores PS3 has only 1 power processor and _6_ SPE cores. http://en.wikipedia.org/wiki/PlayStation_3#Central_processing_unit And it sucks 200W if fully loaded.Article: 117519
Yea... for non-BGA packages - Altera seems to give you more logic. If you're really stuck on Xilinx, I'd pick up the phone and call Avnet (or whoever their equivalent is if you're not in the US) to find out what's actually available. Often, all the configurations listed aren't actually produced unless they have orders for them. If you're not stuck on Xilinx - look into Altera. And don't limit yourself, check out the smaller guys too - lattice semiconductor has a pretty decent non-BGA offering as well. On Apr 2, 6:26 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > "radarman" <jsham...@gmail.com> wrote in message > > news:1175547385.428898.143910@o5g2000hsb.googlegroups.com... > > > > > > >I have an application that is very space limited, and would like to > > use a Spartan XC3S250E in the VQ100 package. Even this package has > > more I/O than I need. (I need a lot of logic, but communication is via > > SPI and RS232 - about 10 I/O total) > > > I can find the 3S100E's in this package from most distributors, but > > not the 3S250E. > > > I only need four total, and I could probably squeeze a TQ144 package > > in if I got creative with parts placement, but the PQ208 absolutely > > won't fit. > > > Also, since these are prototypes, I would like avoid BGA's. The cost > > to have them fitted is just too high. > > > BTW - if anyone from Xilinx is reading this, this is why it would be > > nice if your online store was actually a "store", and not just a link > > to Avnet and Nu Horizons. > > > Thanks! > > This is where a distributor/sales contact (distributor FAE, for instance) > can really help out. Even if you're "small potatoes" for their business, > they should be able to tell you about availability. The online store > *would* be a tremendous resource if it was in a usable state.- Hide quoted text - > > - Show quoted text -Article: 117520
morpheus wrote: > Ray, > Your suggestion makes sense. I had implemented real only multiplier as > my IF is real. > Regarding the output of the envelope detector, I think, due to > truncation at various stages, I have had to drive the ADC, DAC really > high to get some sort of an output. I need to rethink my truncation > strategy at each stage as I am losing tons of dynamic range and this > would be helped if I have a system modeling tool. > Bless the good people at MathWorks. > Thanks for all the comments > -M > You might consider one of the Matlab clones: Octave or I think the other is called Scilab. I don't have experience with either, but from what I understand both will run matlab M files and have pretty good coverage of the matlab function set.Article: 117521
Hi, I am currently working on a project where I have to transmit data from a PC to an FPGA board via Ethernet. For that purpose I use the HTG-V4PCIe evaluation board, which is a Xilinx Virtex-4 PCI Express Development Board from HighTech Global (http://www.hitechglobal.com/boards/v4pcie.htm). It features the Marvell Alaska 88E1111 Gigabit-Ethernet PHY which I use in combination with the Virtex-4 built-in MAC interface. I implemented the TCP/IP stack fully in hardware in VHDL and it works. Fine! :-) Now I have some serious problems with the data transmission and maybe someone could point me to the right direction. For transmitting the data from the PC to the board (in the form of files) I need some sort of application protocoll layer, I guess. First I thought about HTTP which is in my opinion a bit overkill, because all I want to do is transmit files FROM the PC TO the FPGA. I may run a HTTP server on the FPGA's Microblaze but I have the impression that would not satisfy my need of just transmitting data files. Then I thought about Telnet but I am afraid I am not familiar enough with it to estimate if it allows the transfer of files. Is there any simple solution to transmit files from a PC to the FPGA board with a plain application protocoll layer? Any help is highly appreciated. Regards AndreArticle: 117522
On Apr 3, 8:34 am, "Andre Renee" <trauben...@arcor.de> wrote: > Hi, > > I am currently working on a project where I have to transmit data from a PC > to an FPGA board via Ethernet. For that purpose I use the HTG-V4PCIe > evaluation board, which is a Xilinx Virtex-4 PCI Express Development Board > from HighTech Global (http://www.hitechglobal.com/boards/v4pcie.htm). It > features the Marvell Alaska 88E1111 Gigabit-Ethernet PHY which I use in > combination with the Virtex-4 built-in MAC interface. I implemented the > TCP/IP stack fully in hardware in VHDL and it works. Fine! :-) > > Now I have some serious problems with the data transmission and maybe > someone could point me to the right direction. > > For transmitting the data from the PC to the board (in the form of files) I > need some sort of application protocoll layer, I guess. First I thought > about HTTP which is in my opinion a bit overkill, because all I want to do > is transmit files FROM the PC TO the FPGA. I may run a HTTP server on the > FPGA's Microblaze but I have the impression that would not satisfy my need > of just transmitting data files. > Then I thought about Telnet but I am afraid I am not familiar enough with it > to estimate if it allows the transfer of files. Is there any simple solution > to transmit files from a PC to the FPGA board with a plain application > protocoll layer? > > Any help is highly appreciated. > > Regards Andre you could try using socket, it's standard way to tranfer files over tcp/ip jetArticle: 117523
In article <pan.2007.04.03.04.22.57.703686@dont.spam>, Phil Hays <invalid@dont.spam> wrote: >Andreas Koch wrote: > >> When trying to run the WebPack ISE 9.1i SP3 simulator on Linux (Gentoo, >> specifically), it always stops building the simulation executable with a >> message such as: >> >> Building counter_tbw_isim_beh.exe >> >> Nothing further happens. This reproducible on uni-core (Pentium M) as >> well as dual-core (Core 2 Duo) machines. > >Is it reproducible on "Red Hat Enterprise Linux"? That is the supported >version. I know. But we don't have RHEL here. On the other hand, we never had any problems using ISE under Gentoo Linux before (ever since the WINEified initial Linux release) > >If it is, you can file a webcase. If not, things get a lot harder. > >If not, is there a test case you can post? Well, the error message above appears when doing the tutorial from the Quick Start Guide. But the behavior is perfectly reproducible: I cannot simulate any models from within the ProjectNavigator IDE. Interestingly, the simulation executable (counter_tbw_isim_beh.exe in the example) _does_ get generated correctly: I can start it from the command line in interactive mode and then run the simulation manually. So, just the communication between the IDE and the simulation executable appears flawed. Incidentally, the IDE also hangs when trying to quit it. Andreas Koch > > >-- >Phil Hays >Article: 117524
Hi- I have been using the QUIP package and have one question regarding integration with SIS. I have been reading the quip_synthesis_interface.pdf document included with the QUIP documents, and am unable to find the "write_verilog.c" plugin for SIS referred to in the document. Does someone know where this is located? Thanks, Mike
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