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Anyone interested in a truly embedded IrDA infrared software protocol stack should check out: http://www.embednet.com This stack is: . modular and written in "clean" C. . small (<10K bytes) . efficient ( Zero copy buffer management ) . able to support speeds from 9.6Kbps to 4Mbps . RTOS ready . simple to port . well tested. . supported on all popular platforms: MIPS, ARM, Motorola, Intel, Hitachi SH, etc ... . (not to forget) inexpensive (<$6k)Article: 12126
Hi. We went with Intel/Altera's little beasts and have a couple still floating around that I could post to you, if you REALLY wanted (I'm in New Zealand). BUT, might I suggest , if you aren't already aware of them ,Philips Coolrunner CPLD's. The PZ5128 comes in 84 pin PLCC's (and other packages) and has 128 macro cells , are ISP, low power etc. i.e.very similar .Available from Marshall, on a good day. When we bought the necessary software it was US$99. Checkout http://www.coolpld.com Ed Hutchinson. Kevin Horton wrote in message <6undrn$sh9$1@news.iquest.net>... >Is it possible to get the NFX780-series of chips any more? I've looked around >and cannot seem to find these for sale anywhere any more. I would really like >to get my hands on several more of this chips (say, 2-10 or more depending on >price) for my own projects. If I cannot get these any more, is there another >similar part I can use? I already have the "dev system" for these parts >(read: PLDshell and a parallel port :-) and this chip is perfect for my needs >and budget.Article: 12127
Elder V Costa <elder@dixtal.com.br> wrote: :Hello : :I have Foundation 1.4 and have developed a board based on Xilinx XC95108 :to be programmed in system. Foundation JTAG programming tools work only :on Windows 95 or NT so I cannot program the device on DOS. I would not :like to oblige my production personnel to install the Windows based :program (fairly complicated and tricky process) and some test tools we :have work fine only on real mode DOS so they would have to reboot their :computer to switch between programming and testing. Older versions of :Foundation software support DOS (Eztag) but it does not recognize some :commands in the version 1.4's jedec file. : :Does somebody have suggestions or a software to control the parallel :programming cable through DOS? : :Thanks in advance for your help There's a JTAG program for XC4000 on my website: http://www.iinet.net.au/~daveb/tricks/fpga-ldr/loader.html It should be quite straightforward to add a module for XC9500. -- Dave Brooks <http://www.iinet.net.au/~daveb> PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or serversArticle: 12128
Lukas Louw wrote: > > Hi all, > > I have an application where we use a handful of standard CMOS IC's, a 4028 > BCD to decimal, and 3 x 4071 quad OR gates, to generate 10 outputs from a 4 > input BCD switch. Speed is not important, as it controls input selection of > a consumer audio product. 4 in to 10 Out, with some Combo, is a good fit for a 22V10. There are MANY vendors for these - we use the ATF22V10BQL-25, as a good 'balance' between Icc and Price. The 'Z' devices are still a premium. Most mid-range programmers can pgm these 24 Pin devices. If you want more bells, like Up/Down Buttons, look at the ATV750/ATF750 - same package, with 10 more buried registers & multiple clocks. > I would like to use a programmable device of some kind, as the marketing > people drive me nuts with their requests for feature changes/additions. > Every time this happens, the gate routing has to be changed, which means > modifying the PCB layout........ Yikes - sounds very expensive. - jg -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Ask for our Controller, Tools & PLD Libraries selector Guides = mailto:DesignTools@xtra.co.nz Subject : Selc51ToolsArticle: 12129
This is not supposed to be a commercial news group. If everyone reading this group, who was a consultant, posted their ads all the time, the group would only be posts from consultants. Sri Saripalle <sri@spiketech.com> wrote in article <01bdeb29$344eae00$cb4f14cf@spike3.spiketech.com>... > Hello Lothar, > > We offer the following services and have expertise in-house > (a)ASIC/FPGA design, verification & implementation services. > (b) EDA Software solutions > (c) Cell & Library Development > > We have 90 employees world-wide and 50 engineers in our US Design center > and the rest in our engineering center in India. > Please let me know if there are any opportunities we could address and > bring in our expertise in this area. > > Thanks > > - Sri > (408)945.0354 Ext. 105 > > >Article: 12130
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Check at http://www.associatedpro.com
Lukas Louw wrote:
> Hi all,
>
> I have an application where we use a handful of standard CMOS IC's, a 4028
> BCD to decimal, and 3 x 4071 quad OR gates, to generate 10 outputs from a 4
> input BCD switch. Speed is not important, as it controls input selection of
> a consumer audio product.
>
> Any ideas on a simple cost effective programmable device that could replace
> these parts? Something that can implement a simple 12 gate or so equivalent
> lookup table? It seems that most of the devices out there today are much
> more complex, therefore too pricey, for what we need.
>
> I would like to use a programmable device of some kind, as the marketing
> people drive me nuts with their requests for feature changes/additions.
> Every time this happens, the gate routing has to be changed, which means
> modifying the PCB layout........
>
> Thanks,
> Lukas Louw
>
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
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Article: 12131http://www.dejanews.com/home_ps.shtmlArticle: 12132
Wallace TREE's are a form of parallel multiplication composing the tree multiplier family!!!!! The following are ranks for 16-bit adders for area, power, and delay Area Ripple-Carry 2 Majerski Ripple-Carry 1 Constant Carry-Skip 3 Variable Carry-Skip 4 Carry-Lookahead 5 Brett and Kung 6 Hybrid Carry-Select 7 Conditional Sum 8 Delay Ripple-Carry 8 Majerski Ripple-Carry 6 Constant Carry-Skip 7 Variable Carry-Skip 4 Carry-Lookahead 1 Brett and Kung 5 Hybrid Carry-Select 3 Conditional Sum 2 Power Ripple-Carry 1 Majerski Ripple-Carry 2 Constant Carry-Skip 3 Variable Carry-Skip 5 Carry-Lookahead 4 Brett and Kung 6 Hybrid Carry-Select 7 Conditional Sum 8 Of course, these are just some adders, there are many more such as Ling Adders, Carry-Select, Variable-Carry-Select, and more. James Stine Lehigh University jes6@eecs.lehigh.edu Ray Andraka wrote: > John Huang wrote: > > > Hi all: > > I need samples for VHDL, that must add 3 std_logic_vector(9 downto 0); > > what is the fastest mothed? > > Depends on your target. For an ASIC, the fastest method is probably a > wallace tree with some form of fast look-ahead carry. For three inputs, > however, I'm not sure the Wallace tree will buy much. In Xilinx FPGAs, the > ripple carry is much faster than any carry look-ahead schemes for the bit > widths you are looking at (assuming you care about clock latency), so a > simple adder tree is fastest...assuming your HDL code makes use of the carry > logic and places the logic accordingly. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randrakaArticle: 12133
The only thing you will have to worry about is that each cycle may not be run in the same number of steps as in a DSP. If you don't have a very-high order FIR filter, it should be OK. walterb wrote: > Juergen Otterbach wrote: > > > > Dear FPGA and VHDL users, > > please let me know if you heard about problems using the Altera DSP Kit > > to design a FIR filter in FLEX10K. Please let me know from what I have > > to be aware. > Yes. A project I was involved in used this package on a FLEX10K series. > We had two identical parallel 64 tap FIR filters which caused major > headaches. Sometimes they worked, then if you made a change in the > design which had nothing to do with the filter implementation, then they > would stop working. > Altera could not help since they wanted our design to try and repeat the > problem which we were not prepared to do. > Solution: > Write your own FIR filter, its not really that difficult. We did and the > problem vanished. > WaltArticle: 12134
--------------E543732991B9A56EDA0457D1 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit http://www.ejob.com/lucent3.htm --------------E543732991B9A56EDA0457D1 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML> <B><FONT FACE="Arial,Helvetica"><FONT COLOR="#FF6666"><FONT SIZE=+3><A HREF="http://www.ejob.com/lucent3.htm">http://www.ejob.com/lucent3.htm</A></FONT></FONT></FONT></B></HTML> --------------E543732991B9A56EDA0457D1--Article: 12135
No actually, the Wallace tree is not a multiplier. It is an adder tree using carry save adders arranged in an optimal merged tree. A Wallace tree multiplier is one that utilizes such a tree to sum the M 1xN partial products in an MxN multiplier to produce the complete product. A Wallace tree can be used in aother applications that require summing data from a number of sources. For example, an FIR filter could use a Wallace tree to sum the contributions from each tap. The output of the Wallace tree is a sum vector and a carry vector that must be combined using a conventional adder. A Wallace tree has no speed advantage over a ripple carry adder tree if it uses a ripple adder to combine the output vectors. Where the Wallace tree gains is when a fast adder (one using a fast carry scheme) is used in place of a ripple adder for the final sum. There is a little more on Wallace trees as applied to multipliers on my website. That discussion includes some graphics to help with the explanation. In the case of an FPGA design (for FPGAs that have fast carry chains), the ripple carry chain is optimized (in the case of xilinx less than 1/4 the delay to an adjacent CLB on the normal wiring), so it becomes very hard to exceed the performance of the ripple adders. The irregular routing for a wallace tree further degrades its performance when applied to these FPGAs. For this reason, an adder tree comprised of ripple adders is the fastest and smallest adder tree for most modern FPGAs. In the case of an ASIC, you have small blocks to work with and more flexibility in the routing, so there are many more options for optimizing adders for area, power and speed. James E. Stine wrote: > Wallace TREE's are a form of parallel multiplication composing the tree > multiplier family!!!!! < tabulation of adders by power, delay and area deleted> > James Stine > Lehigh University > jes6@eecs.lehigh.edu > > Ray Andraka wrote: > > > John Huang wrote: > > > > > Hi all: > > > I need samples for VHDL, that must add 3 std_logic_vector(9 downto 0); > > > what is the fastest mothed? > > > > Depends on your target. For an ASIC, the fastest method is probably a > > wallace tree with some form of fast look-ahead carry. For three inputs, > > however, I'm not sure the Wallace tree will buy much. In Xilinx FPGAs, the > > ripple carry is much faster than any carry look-ahead schemes for the bit > > widths you are looking at (assuming you care about clock latency), so a > > simple adder tree is fastest...assuming your HDL code makes use of the carry > > logic and places the logic accordingly. > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email randraka@ids.net > > http://users.ids.net/~randraka -- -Ray Andraka, P.E. (a Lehigh grad) President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for signal processing, computing and control applications. Applications designed include radar processors, digital communications, imaging, video and physical systems models.Article: 12136
Huh?? An FIR filter implemented in an FPGA outperforms one implemented in a DSP by a wide margin. The more taps, the higher the performance gain. The FPGA implementations perform the multiplications for all the taps in parallel, where a DSP microprocessor computes the taps sequentially. It is misinformation such as found in James' post that confuses people about the capabilities, advantages and limitations to using FPGAs in signal processing applications. As far as the Altera problems walterb had, that is a classic run out of routing problem in Altera. The Altera filter works fine as long as there is enough resource for it to route. One of the problems with the Altera 10K architecture is that all of the routing (outside of the LABs) is essentially global routing (well, I suppose staying in the same row is only pseudo-global). There is not enough of it if a large number of LE's need to connect to LE's in another LAB, especially if you need to go across rows. In data path type designs, especially ones that have arithmetic functions with more than two inputs (these force logic to two levels) or clock enabled registers, it is fairly common to run out of routing long before you run out of logic. For signal processing applications, the Xilinx 4K architecture is much better (and the routing issue is only one of many reasons for this). On the other hand, the global routing structure in the Altera does make placement considerably less critical and helps make the device more synthesis friendly than the Xilinx 4K. The Altera structure is fairly well suited for random (read non-arithmetic) logic. James E. Stine wrote: > The only thing you will have to worry about is that > each cycle may not be run in the same number of > steps as in a DSP. If you don't have a very-high order > FIR filter, it should be OK. > > walterb wrote: > > > Juergen Otterbach wrote: > > > > > > Dear FPGA and VHDL users, > > > please let me know if you heard about problems using the Altera DSP Kit > > > to design a FIR filter in FLEX10K. Please let me know from what I have > > > to be aware. > > Yes. A project I was involved in used this package on a FLEX10K series. > > We had two identical parallel 64 tap FIR filters which caused major > > headaches. Sometimes they worked, then if you made a change in the > > design which had nothing to do with the filter implementation, then they > > would stop working. > > Altera could not help since they wanted our design to try and repeat the > > problem which we were not prepared to do. > > Solution: > > Write your own FIR filter, its not really that difficult. We did and the > > problem vanished. > > Walt -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12137
In article <36124C3D.65BFACDF@viewlogic.com>, John Willoughby <jww@viewlogic.com> wrote: > Check out www.Viewlogic.com. Great tools (Fusion/SpeedWave for VHDL > simulation, FPGA-Express for synthesis, etc.) integrated under the > Intelliflow manager makes a very easy-to-use package from Viewlogic, the > leader in FPGA design solutions. > > John Huang wrote: > > > I want to buy a FPGA tool, do you recommand which > > one is better, how about Accolade and Aldec? I think every FPGA manufacturer has a tool, atleast place and route tool. So it depends on which FPGA you may like to target your design. Your target FPGA decides the best tool most of the times. For eg : For Altera you have to use MaxplusII,for Xilinx you have to use M1 etc etc.. Rajkumar... > > > > John Huang > > -- > *-------------------------------------------------------* > * John Willoughby W E C r C * > * System Simulation Mktg office: 508-303-5238 * > * Viewlogic Systems mobile: 508-254-9608 * > * 293 Boston Post Rd West fax: 508-460-7826 * > * Marlboro, MA 01752 email: jww@viewlogic.com * > * * > * "Well done is better than well said" - Ben Franklin * > *-------------------------------------------------------* > > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12138
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Yes Lukas you could go with PALs easily with this application, or you could use
CPLDs and or very small FPGAs. Further you could make the part in circuit
programmable. XILINX actually has incircuit programmable CPLDs which I think you
can compile via the web. (check at www.xilinx.com) Also we sell the tools for the
XILINX Foundation software or you can purchase them locally. You can get a real
nice package to support the smaller parts for ~$99.00. Also AMD's website has the
PALASM 5.0 software for free. Another great site is the http://www.optimagic.com
The folllowing are some vendors who do pals/cplds:
XILINX
Cypress
Lattice
Atmel
AMD
The following are some FPGA vendors:
XILINX
Lucent
Actel
Altera
Quicklogic
Atmel
Hope this helps. (ps. All the stuff mentioned above can be seen from our website,
including the links to the sites mentioned, thus the reason for my initial
posting pointing to http://www.associatedpro.com)
Thanks and good Luck :-)
Richard Schwarz wrote:
> Check at http://www.associatedpro.com
>
> Lukas Louw wrote:
>
> > Hi all,
> >
> > I have an application where we use a handful of standard CMOS IC's, a 4028
> > BCD to decimal, and 3 x 4071 quad OR gates, to generate 10 outputs from a 4
> > input BCD switch. Speed is not important, as it controls input selection of
> > a consumer audio product.
> >
> > Any ideas on a simple cost effective programmable device that could replace
> > these parts? Something that can implement a simple 12 gate or so equivalent
> > lookup table? It seems that most of the devices out there today are much
> > more complex, therefore too pricey, for what we need.
> >
> > I would like to use a programmable device of some kind, as the marketing
> > people drive me nuts with their requests for feature changes/additions.
> > Every time this happens, the gate routing has to be changed, which means
> > modifying the PCB layout........
> >
> > Thanks,
> > Lukas Louw
> >
>
> --
> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
>
> Richard Schwarz, President
> Associated Professional Systems Inc. (APS)
> email: richard@associatedpro.com
> web site: http://www.associatedpro.com
> Phone: 410-569-5897
> Fax: 410-661-2760
>
> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
>
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
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Article: 12139Hi, Its great to see another Lehigh grad.... You are correct, however the term is more accepted among mutlipliers than it is among multi-operand array additions. The original aritcle by Wallace was about multiplication using carry-save adder or 3,2 adders which was later extend by Dadda.. Your web site does provide some great information, however I would like to see more. You don't even cover Dadda Multiplier, Trucated Mulipliers, Squarers, Reduced Area Multipliers. More information would be useful, especially to somebody who doesn't know a Carry-Select , Carry-Skip or Conditional Sum Adder from a Booth 3 Multiplier. Israel Koren, who you may have heard of from University of Massachussetts, provides a much better overview of the basics of computer arithmetic from an algorithmic point of view. But, I loved Ray's homepage....Great JOB!!!! Ray Andraka wrote: > No actually, the Wallace tree is not a multiplier. It is an adder tree using carry > save adders arranged in an optimal merged tree. A Wallace tree multiplier is one > that utilizes such a tree to sum the M 1xN partial products in an MxN multiplier to > produce the complete product. A Wallace tree can be used in aother applications > that require summing data from a number of sources. For example, an FIR filter > could use a Wallace tree to sum the contributions from each tap. The output of > the Wallace tree is a sum vector and a carry vector that must be combined using a > conventional adder. A Wallace tree has no speed advantage over a ripple carry > adder tree if it uses a ripple adder to combine the output vectors. Where the > Wallace tree gains is when a fast adder (one using a fast carry scheme) is used in > place of a ripple adder for the final sum. There is a little more on Wallace trees > as applied to multipliers on my website. That discussion includes some graphics to > help with the explanation. > > In the case of an FPGA design (for FPGAs that have fast carry chains), the ripple > carry chain is optimized (in the case of xilinx less than 1/4 the delay to an > adjacent CLB on the normal wiring), so it becomes very hard to exceed the > performance of the ripple adders. The irregular routing for a wallace tree further > degrades its performance when applied to these FPGAs. For this reason, an adder > tree comprised of ripple adders is the fastest and smallest adder tree for most > modern FPGAs. > > In the case of an ASIC, you have small blocks to work with and more flexibility in > the routing, so there are many more options for optimizing adders for area, power > and speed. > > James E. Stine wrote: > > > Wallace TREE's are a form of parallel multiplication composing the tree > > multiplier family!!!!! > > < tabulation of adders by power, delay and area deleted> > > > James Stine > > > Lehigh University > > jes6@eecs.lehigh.edu > > > > Ray Andraka wrote: > > > > > John Huang wrote: > > > > > > > Hi all: > > > > I need samples for VHDL, that must add 3 std_logic_vector(9 downto 0); > > > > what is the fastest mothed? > > > > > > Depends on your target. For an ASIC, the fastest method is probably a > > > wallace tree with some form of fast look-ahead carry. For three inputs, > > > however, I'm not sure the Wallace tree will buy much. In Xilinx FPGAs, the > > > ripple carry is much faster than any carry look-ahead schemes for the bit > > > widths you are looking at (assuming you care about clock latency), so a > > > simple adder tree is fastest...assuming your HDL code makes use of the carry > > > logic and places the logic accordingly. > > > > > > -- > > > -Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email randraka@ids.net > > > http://users.ids.net/~randraka > > -- > -Ray Andraka, P.E. (a Lehigh grad) > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > > Andraka Consulting Group is a digital hardware design firm specializing in high > performance FPGA designs for signal processing, computing and control > applications. Applications designed include radar processors, digital > communications, imaging, video and physical systems models.Article: 12140
You might want to check out an 18v10 - I don't know who makes it but it should be cheaper than a 22v10. Could be ICT. I have a JDR Microdevices programmer. Paid $500 for it. Works good. Handles EPROMs too. And 8751s. And PICs. and ... Simon ======================================================== Richard Schwarz <aps@associatedpro.com> wrote: >This is a multi-part message in MIME format. >--------------788931E03A1E3AD146748A8A >Content-Type: text/plain; charset=us-ascii >Content-Transfer-Encoding: 7bit > >Yes Lukas you could go with PALs easily with this application, or you could use >CPLDs and or very small FPGAs. Further you could make the part in circuit >programmable. XILINX actually has incircuit programmable CPLDs which I think you >can compile via the web. (check at www.xilinx.com) Also we sell the tools for the >XILINX Foundation software or you can purchase them locally. You can get a real >nice package to support the smaller parts for ~$99.00. Also AMD's website has the >PALASM 5.0 software for free. Another great site is the http://www.optimagic.com >The folllowing are some vendors who do pals/cplds: > >XILINX >Cypress >Lattice >Atmel >AMD > >The following are some FPGA vendors: > >XILINX >Lucent >Actel >Altera >Quicklogic >Atmel > >Hope this helps. (ps. All the stuff mentioned above can be seen from our website, >including the links to the sites mentioned, thus the reason for my initial >posting pointing to http://www.associatedpro.com) > >Thanks and good Luck :-) > >Richard Schwarz wrote: > >> Check at http://www.associatedpro.com >> >> Lukas Louw wrote: >> >> > Hi all, >> > >> > I have an application where we use a handful of standard CMOS IC's, a 4028 >> > BCD to decimal, and 3 x 4071 quad OR gates, to generate 10 outputs from a 4 >> > input BCD switch. Speed is not important, as it controls input selection of >> > a consumer audio product. >> > >> > Any ideas on a simple cost effective programmable device that could replace >> > these parts? Something that can implement a simple 12 gate or so equivalent >> > lookup table? It seems that most of the devices out there today are much >> > more complex, therefore too pricey, for what we need. >> > >> > I would like to use a programmable device of some kind, as the marketing >> > people drive me nuts with their requests for feature changes/additions. >> > Every time this happens, the gate routing has to be changed, which means >> > modifying the PCB layout........ >> > >> > Thanks, >> > Lukas Louw >> > >> >> -- >> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ >> >> Richard Schwarz, President >> Associated Professional Systems Inc. (APS) >> email: richard@associatedpro.com >> web site: http://www.associatedpro.com >> Phone: 410-569-5897 >> Fax: 410-661-2760 >> >> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ >> > > > > > >-- >__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > > Richard Schwarz, President > Associated Professional Systems Inc. (APS) > email: richard@associatedpro.com > web site: http://www.associatedpro.com > Phone: 410-569-5897 > Fax: 410-661-2760 > >__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > > >--------------788931E03A1E3AD146748A8A >Content-Type: text/x-vcard; charset=us-ascii; > name="aaps.vcf" >Content-Transfer-Encoding: 7bit >Content-Description: Card for Richard Schwarz >Content-Disposition: attachment; > filename="aaps.vcf" > >begin:vcard >n:Schwarz;Richard >x-mozilla-html:FALSE >org:Associated Professional Systems >adr:;;;Abingdon;MD;21009;USA >version:2.1 >email;internet:aps@associatedpro.com >title:President >tel;fax:410.661.2760 >tel;home:410.515.3883 >tel;work:410.569.5897 >x-mozilla-cpt:;0 >fn:Richard Schwarz >end:vcard > > >--------------788931E03A1E3AD146748A8A-- > Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 12141
I once had to put a big parallel median filter in a XC4010 (which almost fit). I must have tried a thousand schemes. I was really impressed with the rich variety of approaches available for sorting data. Quite a bit more complexity possible than with multiply which is also pretty rich. One thing seems to keep cropping up in these exercises. The best speed/area ratio seems to be associated with fully parallel pipelined approaches. There is a usually a price to pay for running slowly! Best Wishes, Brad Jan Gray wrote: > To recap the thread and add yet another approach, if you have n inputs each > m bits long, some choices are :- > > 1. simple m/2+1 CLB max accumulator in ~n clocks > 2. ~nm/2 CLB max-mux tree in 1 clock > 3. hybrid which takes ~nm/2k CLBs in k clocks > 4. "parallel bit serial max" in ~n CLBs in ~m clocks > 5. "serial bit serial max" in ~lg m + m/16 CLBs in m*n clocks > > About 5: use a bit serial max state machine together with an m-bit FIFO > implemented using dual port RAM, to store the "current max". Operate by > streaming in all the input words, serially, one bit at a time, into the max > machine. Each m clocks it bit serially emits the max of all inputs so far. > > Jan GrayArticle: 12142
On Thu, 01 Oct 1998 01:10:52 -0400, "James E. Stine" <jes6@eecs.lehigh.edu> wrote: >... Israel Koren, >who you may have heard of from University of Massachussetts, provides >a much better overview of the basics of computer arithmetic >from an algorithmic point of view. Could you please give a URL for that page? > >But, I loved Ray's homepage....Great JOB!!!! I agree ;) > thanks in advance Mats -- Matthias Brucke Computer Science Departement VLSI Group University of OldenburgArticle: 12143
www.dejanews.comArticle: 12144
Thank you so must for all of you, I've solved the problem. Actually, there is 3 pins on the chip which are not working. (for some reason, I dunno) After I escape those pins, everything works well. Anyway, thanks a lot for your opinions. OliverArticle: 12145
--------------3C69D4579E410EE399BE5A33 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit er, austin, does this count as advertising? rk _________________________________________________ ejob wrote: > http://www.ejob.com/lucent3.htm --------------3C69D4579E410EE399BE5A33 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> er, austin, does this count as advertising? <P>rk <P>_________________________________________________ <P>ejob wrote: <BLOCKQUOTE TYPE=CITE> <B><FONT FACE="Arial,Helvetica"><FONT COLOR="#FF6666"><FONT SIZE=+3><A HREF="http://www.ejob.com/lucent3.htm">http://www.ejob.com/lucent3.htm</A></FONT></FONT></FONT></B></BLOCKQUOTE> </HTML> --------------3C69D4579E410EE399BE5A33--Article: 12146
Ray Andraka wrote: > > Huh?? > An FIR filter implemented in an FPGA outperforms one implemented in a DSP by a > wide margin. The more taps, the higher the performance gain. The FPGA > implementations perform the multiplications for all the taps in parallel, where > a DSP microprocessor computes the taps sequentially. It is misinformation > such as found in James' post that confuses people about the capabilities, > advantages and limitations to using FPGAs in signal processing applications. > > As far as the Altera problems walterb had, that is a classic run out of routing > problem in Altera. If that is the case, why does the compiler not give any indication of the routing problems. Incidently, All other logic was removed on several of the tests and it still fell over. For now, I am happy to assume there was a flaw in the DSP FIR filter implementation supplied by Altera. Give me a fast DSP anyday. They are far more flexible. Walt The Altera filter works fine as long as there is enough > resource for it to route. One of the problems with the Altera 10K architecture > is that all of the routing (outside of the LABs) is essentially global routing > (well, I suppose staying in the same row is only pseudo-global). There is not > enough of it if a large number of LE's need to connect to LE's in another LAB, > especially if you need to go across rows. In data path type designs, > especially ones that have arithmetic functions with more than two inputs (these > force logic to two levels) or clock enabled registers, it is fairly common to > run out of routing long before you run out of logic. > > For signal processing applications, the Xilinx 4K architecture is much better > (and the routing issue is only one of many reasons for this). On the other > hand, the global routing structure in the Altera does make placement > considerably less critical and helps make the device more synthesis friendly > than the Xilinx 4K. The Altera structure is fairly well suited for random > (read non-arithmetic) logic. >Article: 12147
Howdy all...
I'm wondering what the main differences are between the
Exemplar and Synopsys synthesis tools for FPGAs. I'm not
interested in hearing that "most people use Synopsys."
(Linux is better than Windows, so it is clear the "most people"
make the wrong decision)
Opinions are fine, I'd just like to hear how people chose
between the two. Incidentally, I use Leonardo (Exemplar) and
like it. But I haven't used Synopsys all that much to form
a decision.
Cheers,
Jake
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 12148Jake Janovetz wrote: > > Howdy all... > > I'm wondering what the main differences are between the > Exemplar and Synopsys synthesis tools for FPGAs. I'm not > interested in hearing that "most people use Synopsys." > (Linux is better than Windows, so it is clear the "most people" > make the wrong decision) > Opinions are fine, I'd just like to hear how people chose > between the two. Incidentally, I use Leonardo (Exemplar) and > like it. But I haven't used Synopsys all that much to form > a decision. > > Cheers, > Jake One possibly big difference, depending on whether you have existing code, is that Synopsys does not support VHDL-93. They seem to be pretty stuck in VHDL-87. Otherwise, I can only stay that Synopsys is what comes with Xilinx Foundation, so a lot of Xilinx users have it! ;) -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12149
Hello,
I wrote up the following VHDL code in Altera's MAX+PLUS II 7.21
(student edition):
entity data_out_unit is
port(data, data_out: in std_logic; -- data_out is a
control signal
SDA: out std_logic); -- SDA connects
to a pull-up resistor bus line
end data_out_unit;
architecture behavior of data_out_unit is
signal Q: std_logic := 'Z';
begin
process(data, data_out)
begin
if (data_out = '1') then
if (data = '1') then
Q <= 'Z';
elsif (data = '0') then
Q <= data;
end if;
end if;
end process;
SDA <= Q;
end behavior;
It compiles fine, but when I go on to synthesize it I get the following
message:
Error : TRI or OPNDRN buffer ':67' already drives OUTPUT pin, it cannot
also drive
other types of primitives
I gather that the signal Q is being referred to as the buffer. The help
states that if a TRI
buffer is driving an OUTPUT pin it can only drive other OUTPUT pins and
not
primitives. However, if its driving a BIDIR pin then it can drive other
primitives.
So when I changed the direction of my SDA signal from 'out' to 'inout'
it synthesized OK.
But I feel uneasy because SDA is not supposed to be like that. Any
comments?
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