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This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. ------_=_NextPart_001_01BE1D10.663C02E6 Content-Type: text/plain; charset="iso-8859-1" Hi, I had tried very hard to integrate the Viewlogic EDA tool (Workview office) with the backend PAR for Xilinx alliance series and Altera Maxplus 2 and encountered a lot of problems which I hope you could render some assistance. The questions are as follow: * The steps or installation steps to integrate the above tools * How do we create versioning for different synthesis and device fitting design * How to set up the environment variables for the above tools( you may like to code me the details assuming that my xilinx installation is at c:\xilinx and altera software at c:\maxplus2) * There seems to be 2 set of libraries available, one from Viewlogic another from vendor, which should we use and how to set them? * How do we download the bit file (or configuration file) to initialize the FPGA chip after it is generated at Intelliflow. Your help in solving the above problems would grant me more faith in Viewlogic tool. Hope you can help. If possible, please direct your reply to yeosky@mbox3.singnet.com.sg <mailto:yeosky@mbox3.singnet.com.sg> Thank you Yeo Wee Kwong ------_=_NextPart_001_01BE1D10.663C02E6 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN"> <HTML> <HEAD> <META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; = charset=3Diso-8859-1"> <META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version = 5.5.2232.0"> <TITLE>Viewlogic setup with Xilinx and Altera Backend PAR</TITLE> </HEAD> <BODY> <P><FONT FACE=3D"Arial">Hi,</FONT> </P> <P><FONT FACE=3D"Arial">I had tried very hard to integrate the = Viewlogic EDA tool (Workview office) with the backend PAR for Xilinx = alliance series and Altera Maxplus 2 and encountered a lot of problems = which I hope you could render some assistance. </FONT></P> <P><FONT FACE=3D"Arial">The questions are as follow:</FONT> <UL><LI><FONT FACE=3D"Arial">The steps or installation steps to = integrate the above tools</FONT></LI> <LI><FONT FACE=3D"Arial">How do we create versioning for different = synthesis and device fitting design</FONT></LI> <LI><FONT FACE=3D"Arial">How to set up the environment variables for = the above tools( you may like to code me the details assuming that my = xilinx installation is at c:\xilinx and altera software at = c:\maxplus2)</FONT></LI> <LI><FONT FACE=3D"Arial">There seems to be 2 set of libraries = available, one from Viewlogic another from vendor, which should we use = and how to set them?</FONT></LI> <LI><FONT FACE=3D"Arial">How do we download the bit file (or = configuration file) to initialize the FPGA chip after it is generated = at Intelliflow.</FONT></LI> <BR> </UL> <P><FONT FACE=3D"Arial">Your help in solving the above problems would = grant me more faith in Viewlogic tool. Hope you can help.</FONT> </P> <P><FONT FACE=3D"Arial">If possible, please direct your reply to = </FONT><A HREF=3D"mailto:yeosky@mbox3.singnet.com.sg"><U><FONT = COLOR=3D"#0000FF" = FACE=3D"Arial">yeosky@mbox3.singnet.com.sg</FONT></U></A><FONT = FACE=3D"Arial"> Thank you</FONT> </P> <P><B><I><FONT COLOR=3D"#008080" FACE=3D"Bookman Old Style">Yeo Wee = Kwong</FONT></I></B><B><I></I></B><B><I></I></B> </P> </BODY> </HTML> ------_=_NextPart_001_01BE1D10.663C02E6--Article: 13401
dsaffcvncncncnOn Tue, 24 Nov 1998 23:37:40 GMT, "Steve" <reply.through.newsgroup@paranoid.com> wrote: >I'm interfacing to a Motorola MPC 860 @50Mhz. I need to provide an >acknowledge signal in <10ns after the Clock. To do this my PLD/FPGA >needs to have a (Clk-Q + comb delay + tristate enable) < 10ns. > >So far I haven't found a CPLD to do it. What small FPGA's have the best >crack at it??? ... or prove me wrong on the CPLD issue? > >So far my only practical solution is an XCS05XL-4. > > >Comments? > >Steve > >Article: 13402
Victor the Cleaner <jonathan@canuck.com> wrote: : Tim Tyler (tim@BITS.bris.ac.uk) wrote: : : Bob Sefton <nobody@home.com> wrote: : : : What an absolute crock of shit. Save this crap for : : : misc.invest.stocks where somebody might buy into it. : : Unlikely - it's easy to ignore anonymous posters trying to diss companies : : - they could equally well be from the backers of the competition. : Or from a disenchanted employee wanting to get the "truth" out and fearing : reprisals. Few employees become so disenchanted with their company that they try to back-stab it while still in a position to receive reprisals. Ex-employees would perhaps be more likely to behave in this manner - but they may well have grudges to take into account. I don't know what 'Anonymous' is trying to achieve with its post, but the method used doesn't provide much in the way of credibility. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com ...but officer, I was only going one way!Article: 13403
I am trying to make an informed decision on which FPGA HDL compiler I should purchase. I have evaluated three, FPGA Express (Synopsys), Synplify (Synplicity), and Leonardo Spectrum level 3 (Exemplar). All three tools produce similar results, all have basically the same features, all are priced about the same give or take a few thousand. Any comments, positive or negative, about the tool you are using that you would care to share would be greatly appreciated. If there is a demand I could tabulate and post the summary. Regards Jerry EnglishArticle: 13404
Ellis, We have an AllPro 88, software version 2.90. In our installation the diagnostics are executed through the main program under the utilities menu item. The programs and directories that you referenced are not present in our system. Regards, Paul T. Shultz Chesapeake Sciences Corporation <paul@csciences.com> Ellis Easley wrote: > This question is not exactly FPGA related, but this is the only newsgroup I > can find that deals with programmable logic. I am looking for the diagnostic > programs for the Logical Devices AllPro (40) or AllPro 88 programmer. The > diagnostic programs provided with the AllPro 88 are called DIAG1, DIAG3, and > DIAG4.EXE and are located in directories named DIAG1, 3, and 4, according to > the service manual. > > I am trying to use an AllPro programmer that I found in an internet auction. > Before I bid on it I contacted Logical Devices about support. They told me I > could get a service manual from them that would provide all the information > I would need to verify the machine was working before buying the programming > software. I understood this to mean it would contain either program listings > or programming information which I could use to exercise the hardware. I > ordered the manual and find it does not contain the details I need. It > covers a newer model (AllPro 88) and while the schematics it contains are > similar to the hardware in my unit, there are no PAL equations and no > schematics of the pindriver circuits. I have figured out the circuitry up to > the pindrivers but don't want to go further till I know whether it is > possible to turn on more than one source in a pindriver. I don't want to > accidentally connect 25V at 1A to a TTL output or a FET to ground! > > Logical Devices says the AllPro 88 software recognizes the older AllPro > model and will do all devices up to 40 pins (the 88 has 88 pindrivers, the > old model has 40). > > Ellis Easley Jr. > ehowell.easley@worldnet.att.netArticle: 13405
Steve wrote:
> I just got off the phone with Xilinx support re a problem
> with FPGA Express creating an xnf which generated
> errors in the Xilinx tools.
>
> They said that editing the xnf to fix the error was the best
> solution. Is this normal? There's got to be a better way.
>
> BTW, I was going to try edif output as recommended in
> answer 2866 but neither I (nor support) know how to
> select edif output from Express!
>
> This is getting a little frustrating.
>
> Steve
1) What exactly is the error?
2) To the best of my knowledge, Virtex parts are the only
ones which produce EDIF files. You cannot get EDIF
files for older families.
Todd
Article: 13406Jerry, A client's engineer had a problem with FPGA express (in Xilinx Foundation). He had a large state machine (> 32 states) that was one hot encoded. He decoded states for some output signals and found that the synthesized logic was decoding *all* state bits instead of just the signal for the particular state he wanted. Customer service (at Xilinx I believe) told him to recode his state machine by putting the next state and output decodes into one clocked process. This was going to be a tremendous headache for him (it would change pipeline timing, etc...). After trying the design in Leonardo the CLB count dropped 10-15% I believe. IE a huge difference. I use Leonardo primarily because it purports to work for both ASIC and FPGA technologies. I only have experience using it for Xilinx designs where it works really well. The TCL scripting language is very usefull for getting ones self out of tricky implementation problems. I understand that Synplify recently added TCL support but I don't know how deep it is. IMHO if you are doing FPGA's only stick with Galeleo (Spectrum Level 2 I think) or Synplify. If ASIC's are in your future pick Spectrum Level 3. jerry english wrote: > I am trying to make an informed decision on which FPGA HDL compiler > I should purchase. I have evaluated three, FPGA Express (Synopsys), > Synplify (Synplicity), and Leonardo Spectrum level 3 (Exemplar). > All three tools produce similar results, all have basically the same > features, all are priced about the same give or take a few thousand. > Any comments, positive or negative, about the tool you are using that > you would care to share would be greatly appreciated. If there is a > demand > I could tabulate and post the summary. > > Regards > Jerry English -- Tim Davis Timothy Davis Consulting TimDavis@TDCon.com - +1 (303) 426-0800 - Fax +1 (303) 426-1023 +-------------------------------------------------------------------+ : Engineering is like having an 8 a.m. class and a late afternoon : : lab every day for the rest of your life. : +-------------------------------------------------------------------+Article: 13407
Alternatives: 1. Don't use a tri-state output, use "open collector" instead (assumes that signal is active LOW, that de-assertion time isn't nearly as critical as assertion time). 2. Use combinatorial logic to assert signal, rather than register output. If you need output function to persist for a specific # of clock cycles, the "state machine" output term can be (simply) one of the combinatorial input terms. You have two problems, it seems: A. Assert the uP bus interface quickly. This is done best with comb logic, without waiting for clock edge or skew or clk=>q delay. B. Keeping the signal asserted as long as necessary. This is done best with clocked logic, which feeds into the combinatorial logic. Muxing between the A. and B. logic is usually a straightforward problem. Steve wrote: > I'm interfacing to a Motorola MPC 860 @50Mhz. I need to provide an > acknowledge signal in <10ns after the Clock. To do this my PLD/FPGA > needs to have a (Clk-Q + comb delay + tristate enable) < 10ns. > > So far I haven't found a CPLD to do it. What small FPGA's have the best > crack at it??? ... or prove me wrong on the CPLD issue? > > So far my only practical solution is an XCS05XL-4. > > Comments? > > Steve Bob Elkind (fpga design consulting, etc. etc.) eteam@aracnet.comArticle: 13408
Froilan P Montenegro <froilan+@andrew.cmu.edu> wrote: > What about reconfigurable computing and systems-on-a-chip with >programmable logic on the same die? Something like a processor core and >an FPGA on the same chip with some an interface for the two to >communicate with each other. That way if you need basic general >processing abilities along with some custom logic, this might allow you >to build a smaller, cheaper, faster implementation than current >processor/FPGA combinations. I'm no expert but these are two >possibilities I've heard. > > - Froilan I think you're right...the reconfigurable logic field is going to be quite exciting in the future. From what I've seen, though, it's too small right now to predict what's going to happen. If I really polish my crystal ball (it's a bit rusty sometimes) I can see entire systems made from reconfigurable logic. The hardware would be booted in much the same way as operating systems are now. This is a shear fantasy at this point, but it isn't beyond the realm of possibilities. Wade Peterson Silicore CorporationArticle: 13409
>
>1) What exactly is the error?
>
Support was able to solve it for me. I had instantiated a BUFGTS
on a 9500XL pin and was also trying to use that pin as an output.
This seemed to confuse FPGA Express. The solution was to also
instantiate an OBUF on the pin. ie it looks like once you instantiate
anything on a pin you can't rely on the automatic buffer insertion
for that pin. ... kind of makes sense...
BTW: the 9500XL parts have much faster tristate enable although
the internal feedback is still slower than going out and coming
back in the GTS pin. (like I was trying to do)
>2) To the best of my knowledge, Virtex parts are the only
> ones which produce EDIF files. You cannot get EDIF
> files for older families.
>
You're right. The answer I read seemed to indicate you could
choose your output format but you can't. The rule appears to be
pre-Virtex parts use xnf
Virtex use edf
Steve
Article: 13410"Mike & Jen" <rebane@enter.net> wrote: >I agree with Wade's statement: >>>I cannot see how the continued push towards ever larger FPGAs matches >>>with what people actually design. >What is the difference between a 500k/1M gate FPGA design and an ASIC in >terms of design time and time to market? Not much that I can see. An FPGA >will always be slower and consume more power than the ASIC. Why re-invent >the wheel for 75% of a 1M gate FPGA design that uses common >cores/interfaces/functions in support of, on average 25% of the design for >actual custom IP requiring re-programmable logic? Devices of that size do >not show me any enhanced value from a designer's perspective. I agree from a totally technical perspective. However, the FPGA parts are more viable in smaller quantities. A lot of ASIC vendors won't even talk with you unless you want to buy 10,000 - 20,000 parts. The majority of design wins out there are much smaller. That's where the FPGAs fit in. The FPGAs also cut time-to-market. We've discovered that in the core business, the time-to-market is much faster...usually 4-12 weeks (or more) than an ASIC. >>2) The system-on-a-chip market (which is in it's infancy now, at least >>for FPGAs) will grow at a faster pace than the market at large. These >>parts require very large densities. >I agree. The densities will need to be very large to implement standard >cores in FPGA logic and still have programmable logic left over to do >something custom with. That is why I believe that the only vendor who, to >date, has actually displayed the ability to merge ASIC cores (dedicated >silicon) with surrounding FPGA logic is Lucent Technologies (ORCA). That is >what I would define as true "systems on a chip"; not just a bigger array >block. They seem to have the designers in mind. I kind of like those ORCA parts. The Lucent place and route tools arn't very glitzy, but they seem to be pretty rock solid (as compared to other vendors). >>4) FPGA and ASIC vendors will, at some point, become commodity >>producers of gates. These companies will complete on delivery, price >>and (to a smaller extent) performance, but not so much on tools (which >>will become the realm of third party EDA vendors). >If just producing larger arrays of the same ( although renamed) architecture >is the direction X and A are going to take, then FPGAs will become as you >put it "... become commodity producers of gates." However, I do not >believe it will be reduced to quite that simplistic a level (e.g.. DRAMS). >Just because a lot of gates fill a device does not qualify it as ASICish >(forgive my new word). I feel it would be a mistake for the marketing >departments of the FPGA vendors to promote their larger devices as ASIC >like. To do so would insult the intelligence of most designers (I hope). >FPGAs are used to implement specific system capabilities as do ASICs. >I believe we are in store for the usual ASIC bidding wars with an FPGA >twist. The vendors that can successfully merge the technologies will offer >true value and will set themselves apart from the traditional FPGA/ASIC >vendors. >Mike. The true commodity FPGA (similar to DRAMs) probabably will never entirely happen unless somebody standardizes on the guts. DRAMs are true commodity parts, but there are some pretty good JEDEC pinout and timing standards. FPGAs are becoming more similar, but there is no true standard architecture yet. My Christmas wish list this year includes an ANSI/IEEE standard for standard FPGA arcitectures. That way all of the application and tool developers could get some of their sanity back. That would also really push FPGAs into the commodity realm. Imagine 5-10 vendors of FPGAs all with a similar architecture! Wade Peterson Silicore Corporation http://www.silicore.net/Article: 13411
On 30 Nov 1998 21:57:44 GMT, "Austin Franklin" <dark4room@ix.netcom.com> wrote: >Valid point, but, er, cough, cough, isn't VHDL supposed to give you that It does, within reason. >ability today? I believe you still needed to buy the vendors tool set for >each architecture.... If you want to give the sales droid money for a back end P&R tool that is useless unless you are buying his FPGAs, then that is your choice, I suppose :-) I'm sure the nice friendly FAE will be only too happy to sort you out with P&R tools when you say magic phrases like "I have a Vendor Independent toolset" and "Actually I could use brand Y for this project, and they just gave me the P&R" Stuart For Email remove "NOSPAM" from the addressArticle: 13412
On Mon, 30 Nov 1998 15:25:12 GMT, thor@sm.luth.se.NoSpam (Jonas Thor) wrote: >It should be possible to drive a global signal in VHDL testbench...? >Any ideas? I think (but I haven't tested it)... >From the M1.5 Design Manager menu: Design -> Implement Options Now set the Simulation Template to "ModelSim VHDL" and Edit the associated template. Select the VHDL/Verilog tab and check the tick box to bring the GSR out as a port. I imagine that should do the trick. Cheers Stuart For Email remove "NOSPAM" from the addressArticle: 13413
Wade D. Peterson wrote: > My Christmas wish list this year includes an ANSI/IEEE standard for > standard FPGA arcitectures. That way all of the application and tool > developers could get some of their sanity back. That would also > really push FPGAs into the commodity realm. Imagine 5-10 vendors of > FPGAs all with a similar architecture! > Don't hold your breath. It worked for DRAMs because they really have a simple, narrowly defined function, ( at least until recently ). And their business has turned into a disaster. FPGAs must stay more diverse, and we need competitive innovation to advance the state of the art. If that leads to some confusion and even chaos, so be it. Just look at the battle between Altera and Xilinx. It has been the driving force that brought you better, bigger and faster devices at an incredibly fast pace. Americans like competition, and everybody wants to win. Standardization would kill innovation and turn these FPGA houses into drab commodity factories that compete on nothing but price. Not my idea of fun. Peter AlfkeArticle: 13414
The last time I looked at FPGA Express it was not very good. I got faster and better out of the box performance from Synplicity, but Exemplar is better if you like tinkering under the hood. You can't go wrong with either product. Exemplar got out first with their ASIC support, but its coming soon from Synplicity. jerry english wrote in message <36640165.A3CCB901@planetc.com>... >I am trying to make an informed decision on which FPGA HDL compiler >I should purchase. I have evaluated three, FPGA Express (Synopsys), >Synplify (Synplicity), and Leonardo Spectrum level 3 (Exemplar). >All three tools produce similar results, all have basically the same >features, all are priced about the same give or take a few thousand. >Any comments, positive or negative, about the tool you are using that >you would care to share would be greatly appreciated. If there is a >demand >I could tabulate and post the summary. > >Regards >Jerry English > > >Article: 13415
> 2) To the best of my knowledge, Virtex parts are the only > ones which produce EDIF files. You cannot get EDIF > files for older families. I believe I'm using EDIF for my Spartan parts now..... AustinArticle: 13416
ELECTRONIC ENGINEERING TIMES via NewsEdge Corporation : San Jose, Calif. - Xilinx Inc. claims to have reached GHz speeds with a prototype FPGA, attributing the feat to the power of pure-play foundries. http://www.eet.com/story/OEG19981130S0011 -EKCArticle: 13417
In article <741uk7$oia@dfw-ixnews9.ix.netcom.com>,
EKC <alpha3.1@ix.netcom.com> wrote:
>ELECTRONIC ENGINEERING TIMES via NewsEdge Corporation : San Jose, Calif. -
>Xilinx Inc. claims to have reached GHz speeds with a prototype FPGA,
>attributing the feat to the power of pure-play foundries.
>
>http://www.eet.com/story/OEG19981130S0011
And are they planning on releasing the GHz speed existing 4000-series FPGA?
No! Instead they are going to release a large, but much slower new FPGA
with this technology. Oh well.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 13418
Hi,
We are try to build an Xilinx FPGA to read and write to an asynchronous
SRAM (due to the design requirement, we can only use asynchronous SRAM,
not synchronous SRAM nor ZBT SRAM)
The problem of the asynchronous SRAM is with its write operation, where
the write enable (R/Wn) has to be asserted ('0') "shortly" after the
address (and data) is stable, and deasserted ('1') "shortly" before the
address (and data) changes. In other words, R/Wn has to be deasserted
('1') when address or data change.
The desired waveform looks like this:
CLK= 30MHz
_______ _______ ________ ________
CLK | | | | | | | |
____| |_______| |_______| |______| |_____
R/Wn _______ ______ _______________________________
| | | |
|__________| |_________|
Addr -------------------------------------------------------------------
RA0 | WA0 | WA1 | RA1 | RA2
| | | |
-------------------------------------------------------------------
A programmable clock can be used to "mask" the original R/Wn (coming out
of a flip flop) to form the above desired waveform. Unfortunately,
programmable clock is also not an option for us right now, even though our
CLK is only 30MHz .
I was wondering if we can just use ONE clock (which is the system clock for
Address, Data, etc.) to work around with the strict write requirement of the
asynchronous SRAM.
Thanks for your help in advance.
-----------------------
Louis Zhang
lzhang@eecg.toronto.edu
Article: 13419On Tue, 01 Dec 1998 19:38:35 GMT, s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb) wrote: >From the M1.5 Design Manager menu: > >Design -> Implement > >Options > >Now set the Simulation Template to "ModelSim VHDL" and Edit the >associated template. > >Select the VHDL/Verilog tab and check the tick box to bring the GSR >out as a port. > >I imagine that should do the trick. Yep, for a back-end timing simulation it would. But I really don't like timing simulation since I beleive the static timing analysis for a synchronous design will cover the timing. What I am doing here is a front-end simulation with the unisim library, so I don't think this will help. Thanks, Jonas ThorArticle: 13420
>They said that editing the xnf to fix the error was the best >solution. Is this normal? There's got to be a better way. > At least Xilinx is consistent! We have been told exactly the same thing. The busses that FPGA Express outputs use the A<i> syntax, now, if we want to instantiate this from a Viewlogic schematics, this simply does not work together! Their option to change the output format still doesn't work in v2.0.3. It would take me 30 secs to fix this in their code, I don't know what they're waiting for, but we had to write our own script to patch their mess. Well,we have been writing scripts for some time now to patch whatever simple things Xilinx tools screw up. On the same track, I am still wondering why I have to click 9 things to create an .XNF file. 1) Click design source tree to expand tree 2) Click to select 'checked?' design 3) Click to create implementation 4) Click OK to accept settings 5) Click implemented design in chips tree to select 6) Click to optimise 7) Click optimised design in chips tree to select 8) Click to export netlist 9) Click to accept the default directory Did the people that created FPGA Express ever used their own tools ????? It seems they like to click their mouse all the time, yes, when updating a design that contains errors, you have to click another design first and then click the updated design to see the errors. Oh, well, meanwhile you can always entertain yourself watching their beautiful 'Internet Explorer copy' flashing lamp to keep yourself from getting nervous.Article: 13421
Please visit and comment on my Electronics and Electrical Engineering pages located at: http://www.users.globalnet.co.uk/~metad/eee.htm Containing: Introduction to EEE Resources (over 100 web links) Employment Statistics and newspaper excerpts Engineering Poems, Quotations and Jokes EEE at Glasgow University In addition my homepage (http://www.users.globalnet.co.uk/~metad/) contains: A section about me My CV A James Bond Section A guestbook Humour 500+ cool links in the "new look" bookpage Cool background MIDI and graphics Literary quotations Photo Album Student Resources Awards Page Poems... Basically, something for everyone! PLEASE VISIT VIA MY MAIN HOMEPAGE ADDRESS! Please send you comments via the guestbook or by Email (containing your full name and Email and webpage addresses) and visit via http://www.users.globalnet.co.uk/~metad/. Thanks Scott Johnston metad@globalnet.co.ukArticle: 13422
Let's see ... if that's an XC4000 ...
I guess it would have to be a -001
or would that be a -0001?
EKC wrote in message <741uk7$oia@dfw-ixnews9.ix.netcom.com>...
>ELECTRONIC ENGINEERING TIMES via NewsEdge Corporation : San Jose, Calif. -
>Xilinx Inc. claims to have reached GHz speeds with a prototype FPGA,
>attributing the feat to the power of pure-play foundries.
>
>http://www.eet.com/story/OEG19981130S0011
>
>
>-EKC
>
>
Article: 13423ez wrote in message <7430d0$8l3@miura.gent.bg.barco.com>... >>They said that editing the xnf to fix the error was the best >>solution. Is this normal? There's got to be a better way. >> >At least Xilinx is consistent! A small point here. I think you're complaining about the wrong company (this time). My understanding is that Synopsis still controls the code and Xilinx only resells it. Granted the FPGA Express user interface is kludgey ... especially their editor, but for me I live with that because the quality of the synthesis for the price (base VHDL) is unrivalled. I do CPLD's and small FPGA's and I use the Altera and Xilinx tools. FPGA Express does a much better job than the Altera VHDL, and some day when they let Xilinx sell the newer version we'll even get VHDL 93 compliance :) SteveArticle: 13424
Austin Franklin wrote: > (nipping the "problem" > > company Neocad in the bud) > > I disagree that NeoCAD was a problem. They (again) created a perception of > making a better router. Well, it really was only better under certain > circumstances....but when used with a design that was floorplanned, it was > NO better, in fact, sometimes worse. They designed it to handle regular > structures, and the Xilinx router did not handle them at all. > > All the rest of the NeoCAD tools were not really very good (say, the EPIC > editor.....). The NeoCAD 'vision' was to make a universal set of tools for > all programmable logic, NOT just 'another' tool for the Xilinx parts. I > don't believe their 'vision' was ever going to materialize, and the > acquisition of NeoCAD by Xilinx was most fortunate for NeoCAD. > Perhaps. But the NeoCAD tools also became the basis for the Lucent tools. I have done several Lucent designs in the past (and present), and when I had to do a full Xilinx 4028 design this summer in only 2 months, the commonality of the Lucent tools I was used to and the Xilinx M1.4 tools was a big factor in the successfull completion. Never having used to old Xilinx tools, I cannot argue any points/opinions people have about new vs. old. However, the common interface was a godsend for me. Also, it has been my case (having to complete designs for people who left) that how good the tools operate for you is directly related to how well you design the circuitry you want to fit. Poor design practices makes for poor routing/timing in the final design. Last, as buggy as Epic is at times (both the Lucent and Xilinx versions), the capability to go in and make tweaks during debug/integration is very helpful. The key is to save after every change. I worked with Altera MaxPlus+ for two years and this was something of a sore point with their tools (at least up to version 8.3, I don't know what they have now). > I believe it was a most unfortunate move for the Xilinx users, since, now, > we are stuck with this set of inferior tools, at least for the foreseeable > future.... > -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>
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