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That's how I hooked mine up (an XCS10-3) and the download works fine. As far as I can tell, the cable draws Vcc from the target system, so you'll have to provide power to your target ; don't expect to get power from your PC through the cable. jamie morken wrote in message <365CC162.3ED3E2F7@uvic.ca>... >Hi, >I need help hooking up my parallel cable III to a Spartan XCS10 device. >Here is what I haveso far: > >Parallel Cable Spartan Pin >1. VCC all vcc pins >2. GND all gnd pins >3. CCLK cclk >4. D/P done >5. DIN din >6. PROG program' > >Is that all I need? Thanks. > >Jamie Morken >Article: 13476
hello i need VHDL or AHDL program , for programing state machine for 28f010 or compable flash memory thank uArticle: 13477
Only the anonymous have somthing to hide, makes you wonder doesn't it. Anonymous (nobody@replay.com) wrote: : This thought should be worrying not only XILINX shareholders, : but also, - XILINX users, who have invested a lot of efforts : and money into mastering XILINX tools. Im not worried, xilinx is working on all kinds of new projects all the time. : Why should we expect XILINX shutdown in the foreseeable future? : 1) XILINX has started as successful innovative company and won : essential part of the market. But that's in the past ... : Recent history of XILINX is a sequence of disastrous failures : to deliver satisfactory quality at reasonable price. : Remind heart-breaking stories with 8000, 6200, 5200 series! : Lacking new ideas, XILINX is trying to sell their old 4000 : series wrapped into Spartan envelope. And now Virtex becomes : too late answer on Altera designs. For a person who tries to sound like they know somthing, you dont, the 4000 series and the spartan are 2 diffent devices, while the 4000 series is an FPGA, spartan is a CPLD. If you ever even looked at these devices you would see that there only similarity is the logic they use(there are probably others but i cant think of any right now). As for virtex coming to late, hardly it coudnt have come at a better time when FPGA designs are getting larger and the need for bigger devices is greater than ever. No, virtex is not to late and it isnt the end its just the begining. : 2) XILINX applies tremendous efforts to reduce the price and ... : the quality of its development tools. : It was reported by many customers in this particular newsgroup : that XILINX Foundation is worse than XACT, and each subsequent : version of Foundation is worse than previous. : Currently the quality of development tools is so bad that XILINX : almost gave up any attempts to fix endless stream of bugs. : The bugs are just stored until next version of Foundation : I know much about these bugs you talk about, as for this ' almost gave up ' garbage, xilinx didnt even flinch. If the bugs were just stored there would be no product for the application wouldnt even start, but this is how all programs start out. So not only does this person know nothing about hardware they know nothing about software. Just remember nothing is bug free, and if you dont tell them about the bugs they will probably never be fixed. : 3) XILINX support service became some sort of psychoanalyst to : keep users calm and to avoid bodily damage (and chip damage) : caused by desperate customers. XILINX is afraid to reveal : an obvious thing: there is no support for ALDEC software : that constitutes the principal part of Foundation (design flow, : schematics and simulation). Well he got the analyst part right, as for supporting ALDEC is supported but in the way other CAE vendors( like mentor, viewlogic ) are supported, we answer to the best of our ability what we can and if we dont know we ask the person who wrote it. We do not know everything and anyone who pretends they do is only fooling themselves. : 4) And now the last news: : MARSHALL does not sell XILINX chips any more. : Obviously, they are feeling where the things go. So be it and let it be done, for i am only but a small piece of the greater picture. I know nothing of this subject, nor do i pretend to know. : Good bye XILINX ... Yes, Good bye, but not to XILINX but to you. For as you say good bye there are many who would like to say Hello. Altera has a good product of that i will not deny, but as for me as, for all to see, it is XILINX that i buy. Eric H., Poet(I try to be at least), Student, SV Engineer and Avid user of xilinx products.Article: 13478
This is a multi-part message in MIME format. ------=_NextPart_000_00AB_01BE1F87.AEA5CCA0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Senior ASIC Design Engineer - Torrance, CA - Permanent Position We are looking for a Senior ASIC Design Engineer to work with a team = through all phases of VLSI microcircuit design. This includes gathering = detailed design requirements, schematic capture, VHDL coding, VHDL = synthesis, circuit simulation using various EDA tools, floor planning, = place and route, post-route simulation, static timing analysis, factory = test vector generation, test vector fault grading and final ASIC = sign-off. Responsibilities also include performing timing analysis, = creating design review documentation and ASIC product specifications, = proto-type testing, characterization and evaluation. Knowledge of = encryption, RISC processor, Smart Card system also a plus. Additional responsibilities include meeting with and presenting = information to customers, evaluating new technologies, evaluating = foundries, leading IRAD projects, leading development teams, writing = white papers and writing proposals. BSEE minimum, MSEE preferred=20 Qualified candidates will also demonstrate exceptional written and = verbal communication, documentation and presentation skills. Please = forward your resume in Word.DOC form promptly for immediate = consideration to SubmitResume@GOVJOBS.COM=20 We look forward to hearing from you soon! Jason P. Whitley Sr. Technology Specialist GOVJOBS.COM V: 714 444=B7 3562 / F: 714 444=B7 3513 Jwhitley@GOVJOBS.COM http://www.GOVJOBS.COM ------=_NextPart_000_00AB_01BE1F87.AEA5CCA0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN"> <HTML> <HEAD> <META content=3Dtext/html;charset=3Diso-8859-1 = http-equiv=3DContent-Type> <META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR> </HEAD> <BODY bgColor=3D#ffffff> <DIV><B><FONT face=3DArial size=3D2> <P>Senior ASIC Design Engineer - Torrance, CA - Permanent = Position<BR></B>We are=20 looking for a Senior ASIC Design Engineer to work with a team through = all phases=20 of VLSI microcircuit design. This includes gathering detailed design=20 requirements, schematic capture, VHDL coding, VHDL synthesis, circuit = simulation=20 using various EDA tools, floor planning, place and route, post-route = simulation,=20 static timing analysis, factory test vector generation, test vector = fault=20 grading and final ASIC sign-off. Responsibilities also include = performing timing=20 analysis, creating design review documentation and ASIC product = specifications,=20 proto-type testing, characterization and evaluation. Knowledge of = encryption,=20 RISC processor, Smart Card system also a plus.</P> <P>Additional responsibilities include meeting with and presenting = information=20 to customers, evaluating new technologies, evaluating foundries, leading = IRAD=20 projects, leading development teams, writing white papers and writing = proposals.=20 BSEE minimum, MSEE preferred </P> <P>Qualified candidates will also demonstrate exceptional written and = verbal=20 communication, documentation and presentation skills. Please forward = your resume=20 in Word.DOC form promptly for immediate consideration to <A=20 href=3D"mailto:SubmitResume@GOVJOBS.COM">SubmitResume@GOVJOBS.COM</A>&nbs= p;</P> <P>We look forward to hearing from you soon!</P><B><FONT face=3D"Arial = Narrow"=20 size=3D5> <P>Jason P. Whitley<BR></FONT><FONT color=3D#808080 face=3D"News Gothic = MT"=20 size=3D1>Sr. Technology Specialist</FONT><FONT color=3D#808000=20 size=3D5><BR></FONT><FONT color=3D#808000 size=3D6>GOV</FONT><FONT = color=3D#000080=20 size=3D6>JOBS.COM<BR></B></FONT><FONT face=3D"Arial Narrow" size=3D2>V: = 714=20 444· 3562 / F: 714 444· 3513</FONT><FONT=20 face=3D"Arial Narrow"><BR></FONT><A = href=3D"mailto:Sirius@deltanet.com"><FONT=20 face=3DArial>Jwhitley@GOVJOBS.COM</FONT></A><FONT = face=3DArial><BR></FONT><A=20 href=3D"http://users.deltanet.com/~sirius"><FONT=20 face=3DArial>http://www.GOVJOBS.COM</FONT></A><FONT=20 face=3DArial><BR></FONT></FONT></P></DIV></BODY></HTML> ------=_NextPart_000_00AB_01BE1F87.AEA5CCA0--Article: 13479
--------------813877A9443A3D1E08BAC111 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi all ! I am a user of Xilinx`s Foundation 1.5 beta . When i try to make large macros (small macro ok !) with the schematic editor i received the following error : 64k segment limitation exceeded : try to decompose sheet or project netlist creation error Can you help me ?? Thanks ! --------------813877A9443A3D1E08BAC111 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> Hi all ! <BR>I am a user of Xilinx`s Foundation 1.5 beta . <BR>When i try to make<U> large </U>macros (small macro ok !) <BR>with the schematic editor i received the following error : <BR> <BR>64k segment limitation exceeded : try to decompose sheet or project <BR>netlist creation error <P>Can you help me ?? Thanks !</HTML> --------------813877A9443A3D1E08BAC111--Article: 13480
Brian Boorman wrote:
> FPGA Express comes from Synopsis and is bundled by Xilinx. I agree it
> sucks! Fortunately, the only thing I use it for is my grad course in
> Verilog. At work we use a "real man's" synthesizer... Exemplar's
> Leonardo.
>
> Just in case Synopsis is listening, here are a few suggestions...
>
> 1) TCL scripting. Let the designers make a script that they can use over
> and over instead of click, click, click, click..... click!
> 2) How about better reporting? Give us a clue as to how well the tool is
> optimizing the design. How many levels of logic did the tool make?
> 3) A way to run everything from NT command line, so that synth and
> back-end can all be run from batch file w/o user interaction.
Well, items 1 and 3 should now be taken care of.
Express 3.0 has a TCL based command line interface, but I can't
comment on its completeness. I'm still waiting for Viewlogic to update
my license file. (Pity the person who buys his or her software from
one company, only to have responsibility for that software transferred to
another! Today I just learned that Viewlogic can't even generate a license
file for the old Synopsys hardware key I've been using for over a year!)
As for item 2, if you open the constraints editor on the optimized design
("View Results"), you can get full detail about any path in the design
including levels of logic. This feature is present in version 2.x (and
above,
I assume). The delay times it gives are totally bogus, but can still be
used
to get an idea about your potential critical paths.
Did the copy of express you used for school have the constraint editor
license?
Todd
Article: 13481Joseph H Allen wrote: > In article <741uk7$oia@dfw-ixnews9.ix.netcom.com>, > EKC <alpha3.1@ix.netcom.com> wrote: > >ELECTRONIC ENGINEERING TIMES via NewsEdge Corporation : San Jose, Calif. - > >Xilinx Inc. claims to have reached GHz speeds with a prototype FPGA, > >attributing the feat to the power of pure-play foundries. > > > >http://www.eet.com/story/OEG19981130S0011 > > And are they planning on releasing the GHz speed existing 4000-series FPGA? > No! Instead they are going to release a large, but much slower new FPGA > with this technology. Oh well. Actually, the Virtex parts are surprising me. On my current design, I am using two XC4044XL-1's, one XC4044XL-09, and two XC4036XL-09's. I was forced to use several "small" devices rather then just a few big devices (4062, 4085) because I couldn't get the speed I needed in the big parts. For my design and a given speed grade, the bigger parts are slower because routing delays begin to dominate. Based on my benchmarks, the XCV300-4 is slightly smaller then an XC4085-1 (NOT counting the block SRAM!) but is as fast as an XC4036XL-09! The fact that it is less then 1/4 the price of the 4085XL-1 also makes my boss very happy. While I do have the Virtex parts on my desk (they just showed up today!) , I haven't actually fired them up yet, so all of my results are based on the static timing from M1.5. Xilinx must produce bigger/faster/cheaper devices or cease to exist. Bigger/same-speed/cheaper devices will not cut it! So far, I'm cautiously optimistic about the Virtex parts, which I was not 6 months ago. ToddArticle: 13482
Just making a correction, there are so many devices out there that i get mixed up in what type of devices they are. In reply to that first question i noted that spartan was a CPLD when it is not. DOH! I make mistakes im only human. Eric, Eric Hammervold (ehammerv@tricity.wsu.edu) wrote: : Only the anonymous have somthing to hide, makes you wonder doesn't it. : Anonymous (nobody@replay.com) wrote: : : This thought should be worrying not only XILINX shareholders, : : but also, - XILINX users, who have invested a lot of efforts : : and money into mastering XILINX tools. : Im not worried, xilinx is working on all kinds of new projects all the time. : : Why should we expect XILINX shutdown in the foreseeable future? : : 1) XILINX has started as successful innovative company and won : : essential part of the market. But that's in the past ... : : Recent history of XILINX is a sequence of disastrous failures : : to deliver satisfactory quality at reasonable price. : : Remind heart-breaking stories with 8000, 6200, 5200 series! : : Lacking new ideas, XILINX is trying to sell their old 4000 : : series wrapped into Spartan envelope. And now Virtex becomes : : too late answer on Altera designs. : For a person who tries to sound like they know somthing, you dont, the 4000 series and the spartan are 2 : diffent devices, while the 4000 series is an FPGA, spartan is a CPLD. If you ever even looked at these : devices you would see that there only similarity is the logic they use(there are probably others but i cant : think of any right now). : As for virtex coming to late, hardly it coudnt have come at a better time when FPGA designs are getting : larger and the need for bigger devices is greater than ever. No, virtex is not to late and it isnt the end : its just the begining. : : 2) XILINX applies tremendous efforts to reduce the price and ... : : the quality of its development tools. : : It was reported by many customers in this particular newsgroup : : that XILINX Foundation is worse than XACT, and each subsequent : : version of Foundation is worse than previous. : : Currently the quality of development tools is so bad that XILINX : : almost gave up any attempts to fix endless stream of bugs. : : The bugs are just stored until next version of Foundation : : I know much about these bugs you talk about, as for this ' almost gave up ' garbage, xilinx didnt even flinch. : If the bugs were just stored there would be no product for the application wouldnt even start, but this is how : all programs start out. So not only does this person know nothing about hardware they know nothing about : software. Just remember nothing is bug free, and if you dont tell them about the bugs they will probably : never be fixed. : : 3) XILINX support service became some sort of psychoanalyst to : : keep users calm and to avoid bodily damage (and chip damage) : : caused by desperate customers. XILINX is afraid to reveal : : an obvious thing: there is no support for ALDEC software : : that constitutes the principal part of Foundation (design flow, : : schematics and simulation). : Well he got the analyst part right, as for supporting ALDEC is supported but in the way other CAE vendors( like : mentor, viewlogic ) are supported, we answer to the best of our ability what we can and if we dont know we ask : the person who wrote it. We do not know everything and anyone who pretends they do is only : fooling themselves. : : 4) And now the last news: : : MARSHALL does not sell XILINX chips any more. : : Obviously, they are feeling where the things go. : So be it and let it be done, for i am only but a small piece of the greater picture. : I know nothing of this subject, nor do i pretend to know. : : Good bye XILINX ... : Yes, Good bye, but not to XILINX but to you. For as you say good bye there are many who would like to say : Hello. : Altera has a good product of that i will not deny, but as for me as, for all to see, it is XILINX that : i buy. : Eric H., : Poet(I try to be at least), Student, SV Engineer : and Avid user of xilinx products.Article: 13483
hi,
is the following code legal vhdl, with the starting and ending index the
same?
ZData : Out Std_Logic_Vector(0 downto 0)
it's the output of vhdl-generating software and normally is a
multiple-bit bus - however, the architecture permits single bit
outputs. is this ok or does it need to be recoded to be a Std_Logic
signal.
thanks a bunch
rk
Article: 13484This is a multi-part message in MIME format. --------------0DF5F7E56D779B876A929F88 Content-Type: multipart/alternative; boundary="------------9318AA4EC4267EB2E927539B" --------------9318AA4EC4267EB2E927539B Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit This should be legal however you must refer to ZData as ZData(0) since it is now indexed. -- Brian rich katz wrote: > hi, > > is the following code legal vhdl, with the starting and ending index the > same? > > ZData : Out Std_Logic_Vector(0 downto 0) > > it's the output of vhdl-generating software and normally is a > multiple-bit bus - however, the architecture permits single bit > outputs. is this ok or does it need to be recoded to be a Std_Logic > signal. > > thanks a bunch > > rk -- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 ------------------------------------------------------------------- --------------9318AA4EC4267EB2E927539B Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>This should be legal however you must refer to ZData as ZData(0) since it is now indexed. <br> <p>-- Brian <br> <p>rich katz wrote: <blockquote TYPE=CITE>hi, <p>is the following code legal vhdl, with the starting and ending index the <br>same? <p> ZData : Out Std_Logic_Vector(0 downto 0) <p>it's the output of vhdl-generating software and normally is a <br>multiple-bit bus - however, the architecture permits single bit <br>outputs. is this ok or does it need to be recoded to be a Std_Logic <br>signal. <p>thanks a bunch <p>rk</blockquote> <pre>-- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 -------------------------------------------------------------------</pre> </html> --------------9318AA4EC4267EB2E927539B-- --------------0DF5F7E56D779B876A929F88 Content-Type: text/x-vcard; charset=us-ascii; name="brianp.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brianp.vcf" begin:vcard n:Philofsky;Brian x-mozilla-html:TRUE org:<br><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx"> version:2.1 email;internet:brianp@xilinx.com title:Product Applications Engineer tel;fax:(408) 879-4442 tel;work:1-800-255-7778 adr;quoted-printable:;;2100 Logic Drive=0D=0ADept. 2530;San Jose;CA;95124-3450;USA x-mozilla-cpt:;0 fn:Brian Philofsky end:vcard --------------0DF5F7E56D779B876A929F88--Article: 13485
I agree with you. I wish many more manufacturers had usenet presence. >I disagree. I think proper net-etiquette can accomodate a mentioning of >devices made by your employer. Otherwise I would have to sign off from >this group. :-(We who work for an FPGA vendor have something to >contribute - and a hell of a lot to learn. >But we must tread lightly, and be constructive, honest, and fair. >Just my $0.02 worth. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 13486
You have in the past maintained availability of old parts mainly with the backwards compatibility of bitstreams, e.g. a XC3064A can load the config of a XC3064, and provided nothing had been bodged too much, it should still run. I don't expect you to maintain availability of old *slow* parts, but it would worry me if the above principle was abandoned wholesale; specifically there being no upgrade path from the old XC4k devices. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 13487
In article <36636fd5.0@news3.enter.net>, Mike & Jen <rebane@enter.net> writes >That is why I believe that the only vendor who, to >date, has actually displayed the ability to merge ASIC cores (dedicated >silicon) with surrounding FPGA logic is Lucent Technologies (ORCA). Actually Plessey advertised a DSP device incorporating dedicated silicon in the form of multipliers together with some FPGA logic about 10 years ago - but I lost track of what happened to that development. -- Richard Cant Senior Lecturer Simulation and Modelling Research Group Department of Computing The Nottingham Trent UniversityArticle: 13488
Tom Burgess <tom.burgess@hia.nrc.ca> writes:
> Peter Alfke wrote:
> >
> <snipped>
> > All our devices are getting much faster. Don't worry, be happy.
> >
>
> Assuming that the power dissipation problems can be solved, the
> other major barrier to high-speed FPGA operation is I/O limitations.
> Any chance of getting differential I/O with LVPECL or LVDS levels from
> FPGAs this century? I could really use an FPGA or even CPLD with
> LVDS I/O options right now. Low power, so much easier to terminate,
> and ground bounce becomes a virtual non-issue.
Isn't the new Altera Apex supposed to have LVDS options? Due out this spring?
Big mistake of Xilinx not to include any differential I/Os on the Virtex.
Homann
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 13489Austin, Maybe you can help me with a problem I am having. I have a speed critical path which is not quite making timing to an output pin. The path starts at the LSBs of an 8 bit counter, progresses up the carry chain, out the top through an extra CLB to the routing nets and then through a second CLB to do some logic before being output on a pin. The counter is created by Logiblox and is instantiated in VHDL for this module. I have tried asking Xilinx about how to merge the two CLBs to allow me to eliminate one CLB delay and one net. But it would appear that this can't be done while using the Logiblox symbol. It appears that I need to create my own special counter with the needed logic at the top of the carry chain. My question to you is; how would you do this using your library? Would you need to add a "special" counter, or do you have some sort of "universal" counter which allows you to add some custom logic in the CLB which brings out the carry chain? I'm not necessarily looking for a solution to my problem. I am just curious about how you would do this in your method. Austin Franklin wrote: > I have a different way of doing 'universal' development. I create my > designs using hierarchical symbols from my own library (er, Viewlogic). It > contains all variants of registers, muxes etc, and all I need to create for > a new technology is a new lowest order element (say, for a 32 bit register, > I need to create a 1 bit register). Now I understand there are some items > that are quite architecture dependant....so that takes a bit to do for each > technology. This has worked fine for me for the past 8 years... > > Austin > -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13490
Peter Alfke wrote: > > Wade D. Peterson wrote: > > > My Christmas wish list this year includes an ANSI/IEEE standard for > > standard FPGA arcitectures. That way all of the application and tool > > developers could get some of their sanity back. That would also > > really push FPGAs into the commodity realm. Imagine 5-10 vendors of > > FPGAs all with a similar architecture! > > > > Don't hold your breath. It worked for DRAMs because they really have a > simple, narrowly defined function, ( at least until recently ). And > their business has turned into a disaster. > FPGAs must stay more diverse, and we need competitive innovation to > advance the state of the art. If that leads to some confusion and even > chaos, so be it. > > Just look at the battle between Altera and Xilinx. It has been the > driving force that brought you better, bigger and faster devices at an > incredibly fast pace. > > Americans like competition, and everybody wants to win. > > Standardization would kill innovation and turn these FPGA houses into > drab commodity factories that compete on nothing but price. > > Not my idea of fun. > > Peter Alfke I am a little confused by your reply. You first state that standardization is bad because it would stifle inovation, but then you claim the advantage of competition is "better, bigger and faster" parts. The last two are just the qualities that will improve the most as parts are standardized. DRAMS have become bigger and faster primarily because they are standardized and can be consumed in large quantities without having to design in a manufacturer. So the manufacturers must compete on speed, size and price. As for innovation, although the parts have changed somewhat, I don't see how they have shown "innovation" to any great degree. Can you explain what you meant by this? I am most familiar with the Xilinx families. The variations of the 4K series seem to me to have changed very little over the years. As the parts have gotten bigger, more and different routing has been added, but the basic architecture has remained the same. In fact you could call the 4K family something of a "standard". -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13491
I have two questions: 1. I own Foundation 1.4, is there a way to upgrade it to 1.5 online? 2. Anyone had any experience using Aldec's Active-VHDL as a design-entry tool and call (from within the software) to Metamor/M1 to synthesize/implement his design? Thanks -- Yours, -- Ido Kleinman. kleinn@REMOVETHIS.mail.biu.ac.il ** Please delete the "REMOVETHIS." substring to EMail me.Article: 13492
I'm not sure how Austin's library is set up. My library has 1 and 2 bit slices of many different flavors of counters. All use the carry chain and have the fmaps in the schematic. I use special versions of a specific counter for the msb(s) and lsb(s) to handle the carry chain. To create an arbitrary counter I just plunck down the needed number of 2 bit slices and RLOC each slice. No need for any more FMAPs. The MSB slice (0 or 1 bit) has a TC output that is essentially the carry chain buffered. For that buffer, I do not use an FMAP. That way, If I need to combine the TC with other logic and am concerned about the mapping I can FMAP it at the counter level. Of course, FMAPing like that loses some of the portability (it is one more thing that needs to be changed) Often, only the 2 bit macros need to be changed to change device families. I have done this several times to port designs between altera and xilinx (the designs were done with my library). Rickman wrote: > Austin, > > Maybe you can help me with a problem I am having. I have a speed > critical path which is not quite making timing to an output pin. The > path starts at the LSBs of an 8 bit counter, progresses up the carry > chain, out the top through an extra CLB to the routing nets and then > through a second CLB to do some logic before being output on a pin. > > The counter is created by Logiblox and is instantiated in VHDL for this > module. I have tried asking Xilinx about how to merge the two CLBs to > allow me to eliminate one CLB delay and one net. But it would appear > that this can't be done while using the Logiblox symbol. It appears that > I need to create my own special counter with the needed logic at the top > of the carry chain. > > My question to you is; how would you do this using your library? Would > you need to add a "special" counter, or do you have some sort of > "universal" counter which allows you to add some custom logic in the CLB > which brings out the carry chain? > > I'm not necessarily looking for a solution to my problem. I am just > curious about how you would do this in your method. > > Austin Franklin wrote: > > I have a different way of doing 'universal' development. I create my > > designs using hierarchical symbols from my own library (er, Viewlogic). It > > contains all variants of registers, muxes etc, and all I need to create for > > a new technology is a new lowest order element (say, for a 32 bit register, > > I need to create a 1 bit register). Now I understand there are some items > > that are quite architecture dependant....so that takes a bit to do for each > > technology. This has worked fine for me for the past 8 years... > > > > Austin > > > > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 13493
I've just been trying to install F1.5 on our new Windows NT machine. Installation is o.k. but when I try to open a project I get the message: Inavlid hostid (-9,57). It looks like a bad license file except: (1) I've tried it with 2 license files. (2) The message appears 42 sec after starting ``Synopsys initialisation''. I have replaced the Flexlm program ``lmutil'' with the new version 6.1, the old one always came back with all 0's for the Ethernet address. Anybody else had a similar problem ? Or understands NT better than I do ?Article: 13494
Hi there, I believe it is OK to do so. I've used it once in simulation & synthesis, and it did not give any problems. Suttinan.... rich katz <rich.katz@gsfc.nasa.gov> wrote in article <36687FA3.A8A81595@gsfc.nasa.gov>... > hi, > > is the following code legal vhdl, with the starting and ending index the > same? > > ZData : Out Std_Logic_Vector(0 downto 0) > > it's the output of vhdl-generating software and normally is a > multiple-bit bus - however, the architecture permits single bit > outputs. is this ok or does it need to be recoded to be a Std_Logic > signal. > > thanks a bunch > > rk > >Article: 13495
Steve, I think it is normal for Xilinx to suggest it before they take the responsibility themselves. This past spring I worked on some changes to a 4 year old design. It was originally done using XACT 5.1 and Xilinx told us to load 5.2.1 because it was newer and better. Eventually we fount that the RAM library macros had a Xilinx design error (ie, new feature) which caused XNFmerge to fail. Instead of offering revised libraries, the whole Xilinx chain of command said we should edit the offending statements out of the XNF. After my calls several times a day looking for a sane solution, our Director of Engineering called with me one time. That was about the time we got elevated beyond the entry level tech support, and Xilinx started to fix the library. Sadly, they refused to make an official patch. They made a private library for us and won't really document the problem. This was while they said XACT was still supported. I wonder what its like once support ends? Best wishes, John Steve wrote: > I just got off the phone with Xilinx support re a problem > with FPGA Express creating an xnf which generated > errors in the Xilinx tools. > > They said that editing the xnf to fix the error was the best > solution. Is this normal? There's got to be a better way. > > BTW, I was going to try edif output as recommended in > answer 2866 but neither I (nor support) know how to > select edif output from Express! > > This is getting a little frustrating. > > SteveArticle: 13496
> My question to you is; how would you do this using your library? Would > you need to add a "special" counter, or do you have some sort of > "universal" counter which allows you to add some custom logic in the CLB > which brings out the carry chain? Ray's method is pretty much the same as what I do. You do have to realize that taking the carry out of a 1 bit in the CLB vs a 2 bit in the CLB requires a different 'function' block be hooked to the 2 bit slice counter symbol.... Obviously, the starting bit can be different too...you might use only one of the bits of the start CLB too......and also, what type of a counter, loadable, up/down, up or down etc....makes the building blocks different... If you use Viewlogic, and tell me how many bits you need, what the starting bit is, whether you want it to count up/down etc. I can send you one in a few minutes..... AustinArticle: 13497
Hello, I am looking for suggestions. I want to upgrade a replacement for a design which previously used a Cypress CY7C341 CPLD. Of course we want: More I/O (about 96 to 128 I/O) Logic is not an issue - same # of macrocells as I/O is plenty In System Programming Reasonably fast logic propogation (10 to 15 nS over temperature - see below) A [preferably] surface mount package Package size less than one inch square (or is that one square inch? (sorry, couldn't resist)). Unfortunately, we also want operating temperature from -55 to 105 degrees C and we need a part which will be available for at least ten more years. This is the big hurdle that stops most popular parts. Does anyone have a favorite? What do you designers at Lockheed, Northrop, Raytheon, and Boeing use under the hood? I realize that a few manufacturers rate their Industrial Plastic over the wider temperature range, but I surveyed Altera, Cypress, and Xilinx and only Cypress seems to offer this category of part in mil temp range. Sadly, the Cypress package options for mil temp are either a (large-ish) QFP or a (through-hole) PGA. I was hoping for one of the tiny PLCC equivalents or a BGA. I guess Vantis is out of the ceramic package business, leaving Atmel and Actel in the reasonably big names. I've never used either of their unique architecture parts, only 22V10 and jelly-bean memory. Any thoughts about customer support, realistic gatecounts and speed, etc? Any other insight about proprietary VHDL tools for these parts or third party support? Thanks. If I get a lot of response, I'll summarize. Can someone help? -- To reply, take out the trash.Article: 13498
--------------2B04591DF17C0C8B51450030
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
ok, here's the score so far:
internet experts: 3 legal, 0 illegal
synthesizers: 1 crashed and burned
1 ran, but output didn't match port definition
Y_0_ instead of Y(0)
1 ran perfectly
rk
-----------------------------------------------------------
Suttinan Chattong wrote:
> Hi there,
>
> I believe it is OK to do so. I've used it once in simulation & synthesis,
> and
> it did not give any problems.
>
> Suttinan....
>
> rich katz <rich.katz@gsfc.nasa.gov> wrote in article
> <36687FA3.A8A81595@gsfc.nasa.gov>...
> > hi,
> >
> > is the following code legal vhdl, with the starting and ending index the
> > same?
> >
> > ZData : Out Std_Logic_Vector(0 downto 0)
> >
> > it's the output of vhdl-generating software and normally is a
> > multiple-bit bus - however, the architecture permits single bit
> > outputs. is this ok or does it need to be recoded to be a Std_Logic
> > signal.
> >
> > thanks a bunch
> >
> > rk
> >
> >
--------------2B04591DF17C0C8B51450030
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<HTML>
<TT>ok, here's the score so far:</TT><TT></TT>
<P><TT>internet experts: 3 legal, 0 illegal</TT><TT></TT>
<P><TT>synthesizers: 1 crashed and burned</TT><TT></TT>
<P><TT>
1 ran, but output didn't match port definition</TT>
<BR><TT>
Y_0_ instead of Y(0)</TT><TT></TT>
<P><TT>
1 ran perfectly</TT><TT></TT>
<P><TT>rk</TT><TT></TT>
<P><TT>-----------------------------------------------------------</TT>
<P>Suttinan Chattong wrote:
<BLOCKQUOTE TYPE=CITE>Hi there,
<P>I believe it is OK to do so. I've used it once in simulation &
synthesis,
<BR>and
<BR>it did not give any problems.
<P>Suttinan....
<P>rich katz <rich.katz@gsfc.nasa.gov> wrote in article
<BR><36687FA3.A8A81595@gsfc.nasa.gov>...
<BR>> hi,
<BR>>
<BR>> is the following code legal vhdl, with the starting and ending index
the
<BR>> same?
<BR>>
<BR>> ZData : Out Std_Logic_Vector(0
downto 0)
<BR>>
<BR>> it's the output of vhdl-generating software and normally is a
<BR>> multiple-bit bus - however, the architecture permits single bit
<BR>> outputs. is this ok or does it need to be recoded to be a Std_Logic
<BR>> signal.
<BR>>
<BR>> thanks a bunch
<BR>>
<BR>> rk
<BR>>
<BR>></BLOCKQUOTE>
</HTML>
--------------2B04591DF17C0C8B51450030--
Article: 13499I also have 1 and 2 bit lsb blocks and 0 and 1 bit msb blocks (2 bit msb case is done by using a middle 2 bits stacked with a 0 bit msb block). It only takes about 2-3 minutes to build any arbitrary counter in viewlogic with this method, even oddball counters such as one that gets reset in the low 5 bits when the upper 11 bits are parallel loaded. All the FMAPs (which are required to work with the carry chain) are buried in the 2 bit slices from the library, so you just need to put RLOCs on the symbols. Using the viewlogic array command, the construction takes very little time. The same method is extended to arithmetic elements (adders/subtractors, limiters, 2's complements, comparators etc.) and other relatively place macros. Austin Franklin wrote: > > My question to you is; how would you do this using your library? Would > > you need to add a "special" counter, or do you have some sort of > > "universal" counter which allows you to add some custom logic in the CLB > > which brings out the carry chain? > > Ray's method is pretty much the same as what I do. You do have to realize > that taking the carry out of a 1 bit in the CLB vs a 2 bit in the CLB > requires a different 'function' block be hooked to the 2 bit slice counter > symbol.... Obviously, the starting bit can be different too...you might > use only one of the bits of the start CLB too......and also, what type of a > counter, loadable, up/down, up or down etc....makes the building blocks > different... > > If you use Viewlogic, and tell me how many bits you need, what the starting > bit is, whether you want it to count up/down etc. I can send you one in a > few minutes..... > > Austin -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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