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On Jan 13, 8:20 pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Tue, 13 Jan 2009 14:18:16 -0800 (PST), jleslie48 > > > > <j...@jonathanleslie.com> wrote: > >On Jan 10, 8:54 pm, rickman <gnu...@gmail.com> wrote: > > >I don't see why the IF statement translates any different than the > >while/for loop. both should > >translate to static sizes independent of the number of interations > >that are completed: > > >an IF translates to: > > ><conditional jump> to else_part > >-- then code goes here > ><unconditional jump> to endif_xyz > >label else_part: > >--else code goes here > >label endif_xyz: > > >and the WHILE would be: > > >label topofwhile_xyz: > ><conditional jump> to end_of_while_xyz > >---stuff to do > ><unconditional jump> to topofwhile_xyz > >label end_of_while_xyz: > > >I was expecting the synth do work similarly. > > The big difference between the two is this: > in the While loop, the jump is _backwards_. > > A more CS-oriented view would be that the difference between IF and > WHILE is exactly that between a directed acyclic and a cyclic graph. > Unrolling the loop is then transforming the cyclic graph into acyclic > form. > > If you are decomposing the operation into machine instructions, and > executing them sequentially, that is no problem; it merely takes a very > long time. > > But you aren't decomposing into anything sequential, unless you can > _force_ a serialisation, e.g. with a "wait until rising_edge(clk)" > in the loop. (Which is unrecognised by XST. Incidentally I tried it in > the Altera synthesis tool. It fails too, interestingly the error is > "More than one Wait in Process" - therefore Altera is explicitly > unrolling the loop even before examining its contents!) > > Therefore the ONLY ways are: (a) to force that serialisation (either as > above but in a better synthesis tool, if one exists), or explicitly in > the pattern you suggested (and criticise) > or (b) unroll the loop (e.g. use ten multipliers in prev example) > > >The data value of the number of iterations is swallowed up by the > ><conditional jump> and thus the sizing of the "circuit" is > >independent of the number of interations. > > I hope the above shows why it doesn't work that way. > > - Brian AHHHH!!!!! so what you and Gabor are saying is that the synth is trying to make my while loop work all within one clock tick, rather than have the n (in the example, 10) iterations occur once per clock tick as my re-written version version does (see post Jan 7, 12:36 pm, the looper10_proc.) So in my bad code, the 'do something' to all occur in the one clock cycle, has to be repeated n times IN HARDWARE , thus allowing all to occur at the same time. Correct?Article: 137401
Try something like..........
use ieee.numeric_std.all;
signal counter : unsigned(big_enough_for_max_value downto 0);
signal irq : std_logic_vector;
process(clk,rst)
begin
if(rst = '1') then
counter <= max_value;
irq <= '0';
elsif(rising_edge(clk)) then
if(counter = x"00..0") then
counter <= max_value;
irq <= '1';
else
counter <= counter - 1;
irq <= '0';
end if;
end if;
end process;
......simple, compact, synchronous.
Should work (barring typos). Don't forget if you need a count of
X then load the counter with X-1 if you're counting to 0.
Nial
Article: 137402Hi, I would like to boost the performance of my Xilinx Virtex-5 designs. I'm interested in "Achritecture Tuning" and in "Timining Contraints usage". Does someone know a book that deals with these topics? Regards, Michael.Article: 137403
On Jan 14, 8:16=A0am, jleslie48 <j...@jonathanleslie.com> wrote: > On Jan 13, 8:20 pm, Brian Drummond <brian_drumm...@btconnect.com> > wrote: > > > > > On Tue, 13 Jan 2009 14:18:16 -0800 (PST), jleslie48 > > > <j...@jonathanleslie.com> wrote: > > >On Jan 10, 8:54 pm, rickman <gnu...@gmail.com> wrote: > > > >I don't see why the IF statement translates any different than the > > >while/for loop. =A0both should > > >translate to static sizes independent of =A0the number of interations > > >that are completed: > > > >an IF translates to: > > > ><conditional jump> to else_part > > >-- then code goes here > > ><unconditional jump> to endif_xyz > > >label else_part: > > >--else code goes here > > >label endif_xyz: > > > >and the WHILE would be: > > > >label topofwhile_xyz: > > ><conditional jump> to end_of_while_xyz > > >---stuff to do > > ><unconditional jump> to topofwhile_xyz > > >label end_of_while_xyz: > > > >I was expecting the synth do work similarly. > > > The big difference between the two is this: > > in the While loop, the jump is _backwards_. > > > A more CS-oriented view would be that the difference between IF and > > WHILE is exactly that between a directed acyclic and a cyclic graph. > > Unrolling the loop is then transforming the cyclic graph into acyclic > > form. > > > If you are decomposing the operation into machine instructions, and > > executing them sequentially, that is no problem; it merely takes a very > > long time. > > > But you aren't decomposing into anything sequential, unless you can > > _force_ a serialisation, e.g. with a "wait until rising_edge(clk)" > > in the loop. (Which is unrecognised by XST. Incidentally I tried it in > > the Altera synthesis tool. It fails too, interestingly the error is > > "More than one Wait in Process" - therefore Altera is explicitly > > unrolling the loop even before examining its contents!) > > > Therefore the ONLY ways are: (a) to force that serialisation (either as > > above but in a better synthesis tool, if one exists), or explicitly in > > the pattern you suggested (and criticise) > > or (b) unroll the loop (e.g. use ten multipliers in prev example) > > > >The data value of the number of iterations is swallowed up by the > > ><conditional jump> and =A0thus the sizing of the "circuit" is > > >independent of the number of interations. > > > I hope the above shows why it doesn't work that way. > > > - Brian > > AHHHH!!!!! =A0 so what you and Gabor are saying is that the synth is > trying to make my while loop work all within one clock tick, rather > than have the n (in the example, 10) iterations occur once per clock > tick as my re-written version version does (see post =A0Jan 7, 12:36 pm, > the looper10_proc.) =A0So in my bad code, the 'do something' to all > occur in the one clock cycle, has to be repeated n times IN HARDWARE , > thus allowing all to occur at the same time. =A0Correct? By Jove I think you've got it! :-)Article: 137404
I have previous design experience with this part. The Spartan-3AN is compatible with TTL logic levels but it is not 5V tolerant. The inputs can be directly connected to a low-voltage LVTTL signal (high logic voltage of 3.3V maximum). For connecting to 5V TTL outputs, a series resistor must be placed at the input of the FPGA. The value of the series resistor must limit the input current to 10mA to prevent physical damage to the input protect diodes internal to the device. 200 ohms would be sufficient. Regards, John LeVieuxArticle: 137405
On Jan 14, 9:05 am, Gabor <ga...@alacron.com> wrote: > > AHHHH!!!!! so what you and Gabor are saying is that the synth is > > trying to make my while loop work all within one clock tick, rather > > than have the n (in the example, 10) iterations occur once per clock > > tick as my re-written version version does (see post Jan 7, 12:36 pm, > > the looper10_proc.) So in my bad code, the 'do something' to all > > occur in the one clock cycle, has to be repeated n times IN HARDWARE , > > thus allowing all to occur at the same time. Correct? > > By Jove I think you've got it! :-) That is a very important mis-understanding to have cleared up. I would of been programming the ~do something~ to calcuate an average or a summation, and the looping nature of the while loop would of been completely wrong. This aint' no C compiler.Article: 137406
I am still learning VHDL and need some help please! This is what i have clk: in std_logic; data : in std_logic_vector ( 3 downto 0); data_out: out std_logic_vector (3 downto 0); clock is running at 20 MHz and data is synchronized with the clock. if data is in this order "1111", "1010" "1111", "xxxx" than, data out is "xxxx". So basically I have to look at the data pattern back to back and then activate my output..if pattern matches, "1111", "0xa" and "0xb", output is good to go, else have just wait... I was thinking to have data stored in FIFO and the have some sort of state machine to look for test pattern..but not sure if that's the best of doing this...any advice???Article: 137407
"John LeVieux" <jlavie@yahoo.com> schrieb im Newsbeitrag news:cd4050ba-cb68-4bdf-b796-c552ac7cba0f@x16g2000prn.googlegroups.com... >I have previous design experience with this part. The Spartan-3AN is > compatible with TTL logic levels but it is not 5V tolerant. The inputs > can be directly connected to a low-voltage LVTTL signal (high logic > voltage of 3.3V maximum). For connecting to 5V TTL outputs, a series > resistor must be placed at the input of the FPGA. The value of the > series resistor must limit the input current to 10mA to prevent > physical damage to the input protect diodes internal to the device. > 200 ohms would be sufficient. > > Regards, > John LeVieux A series resistor will be not enough on the S3AN, since there are no internal diodes to VCC. Although the maximum input voltage is rather high (4.6V) you must insure, that there are no overshots. A voltage divider could be a cheap solution (with all it's disadvantages like low input resistance, bad dynamic behaviour etc.etc.). Better use some level shifters, which are available in thousands of flavours... MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho ! Kontakt: Tel: 08131 339230 mr@oho-elektronik.de Usst.ID: DE130097310 From rgaddi@technologyhighland.com Wed Jan 14 08:59:09 2009 Path: flpi142.ffdc.sbc.com!flph199.ffdc.sbc.com!prodigy.com!flph200.ffdc.sbc.com!prodigy.net!newshub.sdsu.edu!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 14 Jan 2009 10:59:09 -0600 Date: Wed, 14 Jan 2009 08:59:09 -0800 From: Rob Gaddi <rgaddi@technologyhighland.com> Newsgroups: comp.arch.fpga Subject: Re: beginner synthesize question - my debounce process won't synthesize. Message-Id: <20090114085909.7a47d41c.rgaddi@technologyhighland.com> References: <f6m7m4pqcj4ghk3ipmsn6k3dv5qcf9cjsc@4ax.com> <79ed8507-f871-4446-8e58-db1f00dc6aa1@r13g2000vbp.googlegroups.com> <iuu7m4d1hio8b4drb0nmvn5vhpe1i7qs55@4ax.com> <5762b2b5-253e-4aeb-b812-cdb068323ea4@p2g2000prf.googlegroups.com> <9olcm41ke9nk2qsig231jo7u5qcthuao21@4ax.com> <ede7f1a0-3da0-4b46-a07f-adb558838fac@s24g2000vbp.googlegroups.com> <398c6f49-6e7c-4bd8-9545-92753ae64237@m2g2000vbp.googlegroups.com> <c5bd2fde-c8e8-457a-a008-4852fb501472@q36g2000vbn.googlegroups.com> <95eqm4dr1ceg435uaoh4s2ss1tom9nvt1a@4ax.com> <91ef58ff-eef6-4495-a8e0-f2d61dea1658@j35g2000yqh.googlegroups.com> <920d1962-1fe6-444c-a264-58b96db7c7db@v18g2000pro.googlegroups.com> <b1ef68d2-4fb4-4c9f-a7c9-8d4fcd07b438@v42g2000yqv.googlegroups.com> Organization: Highland Technology, Inc. X-Newsreader: Sylpheed 2.5.0 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 15 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-Hl3CqBWm04jUsR0hX+edhBuYp5fVnk8PnIW0ESCvvU5yc/z7oVxuidC/33/z/4seeXn+AQtvQxJMRxQ!IDlfzOF16i+UaAyUUN4eBVosIF4S+2QwK1g8bUeFRWFBkbngbLSDnNNCUtyqFo8JxX5fwzleu1Mf!snxGVms5fEE3BzjI8k8= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: prodigy.net comp.arch.fpga:150478 X-Received-Date: Wed, 14 Jan 2009 11:59:18 EST (flpi142.ffdc.sbc.com) On Wed, 14 Jan 2009 06:26:27 -0800 (PST) jleslie48 <jon@jonathanleslie.com> wrote: > On Jan 14, 9:05 am, Gabor <ga...@alacron.com> wrote: > [snip] > > This aint' no C compiler. > And there's the moral of the story. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 137408
Something Like this:
ir reset=3D'1' then
data_delay1<=3D'0';
data_delay2<=3D'0';
data_delay3<=3D'0';
good<=3D'0;
elsif clk'event and clk=3D'1' then
data_delay1<=3Ddata;
data_delay2<=3Ddata_delay1;
data_delay3<=3Ddata_delay2;
if data_delay1=3Dx"F" and data_delay2=3Dx"A" and data_delay3=3Dx"B" then
good<=3D'1';
else
good<=3D'0';
end if;
end if;
On Jan 14, 4:29=A0pm, marts...@gmail.com wrote:
> I am still learning VHDL and need some help please! This is what i
> have
>
> clk: in std_logic;
> data : in std_logic_vector ( 3 downto 0);
> data_out: out std_logic_vector (3 downto 0);
>
> clock is running at 20 MHz and data is synchronized with the clock.
>
> if data is in this order "1111", "1010" "1111", "xxxx" than, data out
> is "xxxx". So basically I have to look at the data pattern =A0back to
> back and then activate my output..if pattern matches, "1111", "0xa"
> and "0xb", output is good to go, else have just wait...
>
> I was thinking to have data stored in FIFO and the have some sort of
> state machine to look for test pattern..but not sure if that's the
> best of doing this...any advice???
Article: 137409On Jan 14, 7:36=A0am, "M.Randelzhofer" <techsel...@gmx.de> wrote: > "John LeVieux" <jla...@yahoo.com> schrieb im Newsbeitragnews:cd4050ba-cb6= 8-4bdf-b796-c552ac7cba0f@x16g2000prn.googlegroups.com... > > >I have previous design experience with this part. The Spartan-3AN is > > compatible with TTL logic levels but it is not 5V tolerant. The inputs > > can be directly connected to a low-voltage LVTTL signal (high logic > > voltage of 3.3V maximum). For connecting to 5V TTL outputs, a series > > resistor must be placed at the input of the FPGA. The value of the > > series resistor must limit the input current to 10mA to prevent > > physical damage to the input protect diodes internal to the device. > > 200 ohms would be sufficient. > > > Regards, > > John LeVieux > > A series resistor will be not enough on the S3AN, since there are no > internal diodes to VCC. > > Although the maximum input voltage is rather high (4.6V) you must insure, > that there are no overshots. > > A voltage divider could be a cheap solution (with all it's disadvantages > like low input resistance, bad dynamic behaviour etc.etc.). > > Better use some level shifters, which are available in thousands of > flavours... > > MIKE > > --www.oho-elektronik.de > OHO-Elektronik > Michael Randelzhofer > FPGA und CPLD Mini Module > Klein aber oho ! > Kontakt: > Tel: 08131 339230 > m...@oho-elektronik.de > Usst.ID: DE130097310 Thanks Guys! I have just ordered the following part: http://focus.ti.com/lit/ds/symlink/cd4504b.pdf . Will this work ? I read somewhere that I do not have to worry about the current damaging the FPGA. Is this correct due to the high impedance of the S3AN board ? I have two devices that will use the above level shifter and supply square waves/pulses to the FPGA. Will the S3AN be able to handel those devices without crapping out ? Is the S3AN hardware capable to sample one of the device, which is a pulse generator running at max 50Mhz pulse rate ... (note: pulses are not constant) ?Article: 137410
On Jan 14, 3:19=A0pm, uraniumore...@gmail.com wrote: > On Jan 14, 7:36=A0am, "M.Randelzhofer" <techsel...@gmx.de> wrote: > > > > > "John LeVieux" <jla...@yahoo.com> schrieb im Newsbeitragnews:cd4050ba-c= b68-4bdf-b796-c552ac7cba0f@x16g2000prn.googlegroups.com... > > > >I have previous design experience with this part. The Spartan-3AN is > > > compatible with TTL logic levels but it is not 5V tolerant. The input= s > > > can be directly connected to a low-voltage LVTTL signal (high logic > > > voltage of 3.3V maximum). For connecting to 5V TTL outputs, a series > > > resistor must be placed at the input of the FPGA. The value of the > > > series resistor must limit the input current to 10mA to prevent > > > physical damage to the input protect diodes internal to the device. > > > 200 ohms would be sufficient. > > > > Regards, > > > John LeVieux > > > A series resistor will be not enough on the S3AN, since there are no > > internal diodes to VCC. > > > Although the maximum input voltage is rather high (4.6V) you must insur= e, > > that there are no overshots. > > > A voltage divider could be a cheap solution (with all it's disadvantage= s > > like low input resistance, bad dynamic behaviour etc.etc.). > > > Better use some level shifters, which are available in thousands of > > flavours... > > > MIKE > > > --www.oho-elektronik.de > > OHO-Elektronik > > Michael Randelzhofer > > FPGA und CPLD Mini Module > > Klein aber oho ! > > Kontakt: > > Tel: 08131 339230 > > m...@oho-elektronik.de > > Usst.ID: DE130097310 > > Thanks Guys! I have just ordered the following part:http://focus.ti.com/l= it/ds/symlink/cd4504b.pdf. Will this work ? > > I read somewhere that I do not have to worry about the current > damaging the FPGA. Is this correct due to the high impedance of the > S3AN board ? > > I have two devices that will use the above level shifter and supply > square waves/pulses to the FPGA. Will the S3AN be able to handel those > devices without crapping out ? > > Is the S3AN hardware capable to sample one of the device, which is a > pulse generator running at max 50Mhz pulse rate ... (note: pulses are > not constant) ? Umm... The CD4000 series is 5V CMOS, not TTL. The outputs of this part will drive very close to the power rail, and the part is not specified for operation below 5V. However the part is very slow at 5V so the resistor divider approach may not make any difference to your system timing. You may have some problems with slow rise and fall times causing the FPGA to trigger on noise during transition if you intend to use the CMOS signals as a clock. Even if you only use the CMOS signals as sampled data, you may need to add some glitch filtering in the FPGA. From rgaddi@technologyhighland.com Wed Jan 14 14:31:14 2009 Path: flpi142.ffdc.sbc.com!flph199.ffdc.sbc.com!prodigy.com!flph200.ffdc.sbc.com!prodigy.net!bigfeed.bellsouth.net!bigfeed2.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 14 Jan 2009 16:31:14 -0600 Date: Wed, 14 Jan 2009 14:31:14 -0800 From: Rob Gaddi <rgaddi@technologyhighland.com> Newsgroups: comp.arch.fpga Subject: Re: ttl compatible Message-Id: <20090114143114.e049d767.rgaddi@technologyhighland.com> References: <90c0972a-f976-4c03-bb0a-5965b72985fe@v15g2000yqn.googlegroups.com> <bfGdnaqgmLEwP_DUnZ2dnUVZ_vninZ2d@megapath.net> <cd4050ba-cb68-4bdf-b796-c552ac7cba0f@x16g2000prn.googlegroups.com> <6t6f6vF9bef0U1@mid.individual.net> <34ec4a1f-59c8-4b88-8c0a-5c5423654ca4@a29g2000pra.googlegroups.com> Organization: Highland Technology, Inc. X-Newsreader: Sylpheed 2.5.0 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 30 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-Vc2u15f377pqBx6XEkmrW9rPS+3JBswongWdII59VfBAOtBOmYBcHfnLh3o22UMBMmWhiW6PI5qe/5F!/vM91yfNbls1gqCzGuRU8HRv6Hrdws3PzxDQ/+b8B124paPEW6ZeOqHgx4CGSICg6Vk19krm5hoC!yhw0Tq7PrMcTqNuNg6A= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Bytes: 2532 X-Original-Bytes: 2468 Xref: prodigy.net comp.arch.fpga:150482 X-Received-Date: Wed, 14 Jan 2009 17:31:15 EST (flpi142.ffdc.sbc.com) On Wed, 14 Jan 2009 12:19:08 -0800 (PST) uraniumore238@gmail.com wrote: > [snip] > Thanks Guys! I have just ordered the following part: > http://focus.ti.com/lit/ds/symlink/cd4504b.pdf . Will this work ? > > I read somewhere that I do not have to worry about the current > damaging the FPGA. Is this correct due to the high impedance of the > S3AN board ? > > I have two devices that will use the above level shifter and supply > square waves/pulses to the FPGA. Will the S3AN be able to handel those > devices without crapping out ? > > Is the S3AN hardware capable to sample one of the device, which is a > pulse generator running at max 50Mhz pulse rate ... (note: pulses are > not constant) ? > > That's a pretty slow level shifter for a 50 MHz input signal. You'd probably be better off using some of the LVC series tiny logic gates. A +3.3V non-inverting buffer would cover you, and they're all 5V input compliant. You can get a dual in a 6 pin SOT-23 or SC70 for about 15 cents. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 137411
On Jan 14, 2:31=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > On Wed, 14 Jan 2009 12:19:08 -0800 (PST) > > > > > > uraniumore...@gmail.com wrote: > > [snip] > > Thanks Guys! I have just ordered the following part: > >http://focus.ti.com/lit/ds/symlink/cd4504b.pdf. Will this work ? > > > I read somewhere that I do not have to worry about the current > > damaging the FPGA. Is this correct due to the high impedance of the > > S3AN board ? > > > I have two devices that will use the above level shifter and supply > > square waves/pulses to the FPGA. Will the S3AN be able to handel those > > devices without crapping out ? > > > Is the S3AN hardware capable to sample one of the device, which is a > > pulse generator running at max 50Mhz pulse rate ... (note: pulses are > > not constant) ? > > That's a pretty slow level shifter for a 50 MHz input signal. =A0You'd > probably be better off using some of the LVC series tiny logic gates. > A +3.3V non-inverting buffer would cover you, and they're all 5V input > compliant. =A0You can get a dual in a 6 pin SOT-23 or SC70 for about 15 > cents. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order- Hide quoted text - > > - Show quoted text - Guys, I took a look at the datasheet for the chip that I proposed and found out that the chip itself is quite slow (thanks for Rob). I did some extra research and found this other chip that has a faster switching characterstic: http://focus.ti.com/lit/ds/symlink/sn74lvc16244a-q= 1.pdf Please let me know if this will run with the application that I intend on developing....Article: 137412
On Jan 14, 2:37=A0pm, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> Try something like..........
>
> use ieee.numeric_std.all;
>
> signal counter : unsigned(big_enough_for_max_value downto 0);
> signal irq =A0 =A0 : std_logic_vector;
>
> process(clk,rst)
> begin
> =A0 if(rst =3D '1') then
> =A0 =A0 counter <=3D max_value;
> =A0 =A0 irq =A0 =A0 <=3D '0';
> =A0 elsif(rising_edge(clk)) then
> =A0 =A0 if(counter =3D x"00..0") then
> =A0 =A0 =A0 =A0 counter <=3D max_value;
> =A0 =A0 =A0 =A0 irq =A0 =A0 <=3D '1';
> =A0 =A0 else
> =A0 =A0 =A0 =A0 counter <=3D counter - 1;
> =A0 =A0 =A0 =A0 irq =A0 =A0 <=3D '0';
> =A0 =A0 end if;
> =A0 end if;
> end process;
>
> ......simple, compact, synchronous.
>
> Should work (barring typos). Don't forget if you need a count of
> X then load the counter with X-1 if you're counting to 0.
>
> Nial
That is how I started, but didn't know how to finish it.
(how to generate several IRQs on one pin)
I've added two checks in my IRQ routine:
1. read status reg and check if at least one flag is set.
(check for glitch - never happened)
2. after servicing each IRQ, issue ACK and re-check if flag still set.
That happened (the flag was set even though I've issued ACK) so I've
reorganized everything like this:
TIMER : process (CLKMAIN)
begin
-- toggle count-flag when zero
if falling_edge(CLKMAIN) then
if counterA=3D0 then cIRQA <=3D not cIRQA; counterA <=3D reloadA;
else counterA <=3D counterA -1; end if;
if counterB=3D0 then cIRQB <=3D not cIRQB; counterB <=3D reloadB;
else counterB <=3D counterB -1; end if;
if counterC=3D0 then cIRQC <=3D not cIRQC; counterC <=3D reloadC;
else counterC <=3D counterC -1; end if;
end if;
end process TIMER;
IRQFLAGS : process (CLKMAIN, RD)
begin
-- check if count-flag & ack-flag differ
if falling_edge(CLKMAIN) then
if cIRQA /=3D aIRQA then fIRQA <=3D '1'; else fIRQA <=3D '0'; end
if;
if cIRQB /=3D aIRQB then fIRQB <=3D '1'; else fIRQB <=3D '0'; end
if;
if cIRQC /=3D aIRQC then fIRQC <=3D '1'; else fIRQC <=3D '0'; end
if;
end if;
-- SYNCHRONIZE ack flags
if rising_edge(CLKMAIN) then
aIRQA <=3D aIRQA0;
aIRQB <=3D aIRQB0;
aIRQC <=3D aIRQC0;
end if;
-- ACK
if rising_edge(RD) and ADDR=3DADRA then aIRQA0 <=3D not aIRQA0; end
if;
if rising_edge(RD) and ADDR=3DADRB then aIRQB0 <=3D not aIRQB0; end
if;
if rising_edge(RD) and ADDR=3DADRC then aIRQC0 <=3D not aIRQC0; end
if;
end process IRQFLAGS;
IRQPROC : process (CLKMAIN) begin
-- synchro flagIRQ and last_flagIRQ
if rising_edge(CLKMAIN) then
fIRQANY <=3D fIRQA or fIRQB or fIRQC;
lfIRQANY <=3D fIRQANY;
end if;
-- the IRQ output is connected to a 8259, level sensitive channel.
-- keep at least 400nS LOW (inactive) signal.
if falling_edge(CLKMAIN) then
if fIRQANY=3D'1' and nIRQALLOWED=3D'0' then irqA <=3D '1'; else irq=
A
<=3D '0'; end if;
if lfIRQANY=3D'1' and fIRQANY=3D'0' then nIRQALLOWED <=3D '1';
elsif IRQCOUNTER=3D7 then nIRQALLOWED <=3D '0';
end if;
if nIRQALLOWED=3D'1' then IRQCOUNTER <=3D IRQCOUNTER +1; end if;
end if;
end process IRQPROC;
Now the ACK problem is gone, I never see a flag after ACKing it.
If all 3 timers are set to 20000, all of them generate
exactly the same number of IRQs.
If, however, timerA is set to 10000, timerB=3D20000
and timerC=3D30000, then, after 10 minutes,
timerA generates 1200115 IRQs,
timerB generates 600087 IRQs,
timerC generates 400065 IRQs.
400065*3=3D1200195 (80 IRQs diff, should be 1200115)
600087*2=3D1200174 (59 IRQs diff, should be 1200115)
The sequence is started/stopped with keyboard
and using the hand-watch as a timer for 10 mins,
but there should be no more the 1-2 IRQs diff.
What can I do to correct this?
Article: 137413> 1. Have you simulated your design, and does it work? Yes, I've simulated it, and I think it works. > 2. Have you run static timing analysis and does it pass? No, don't know how... > 3. As I alluded to in my first post, Irq coming out of combinatorial logi= c > can be a problem since it could easily glitch and thereby cause a false > interrupt to occur. =A0If your processor has an internal timer you can lo= g the > times when your FPGA interrupts occur. =A0If there are some that differ > significantly from 1ms than you'll be hot on the trail. The problem was that my ACKing didn't cleared the IRQflag. I've fixed that, please read my reply to Nial Stewart.Article: 137414
On Jan 14, 6:11=A0pm, uraniumore...@gmail.com wrote: > On Jan 14, 2:31=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > > > > > On Wed, 14 Jan 2009 12:19:08 -0800 (PST) > > > uraniumore...@gmail.com wrote: > > > [snip] > > > Thanks Guys! I have just ordered the following part: > > >http://focus.ti.com/lit/ds/symlink/cd4504b.pdf. Will this work ? > > > > I read somewhere that I do not have to worry about the current > > > damaging the FPGA. Is this correct due to the high impedance of the > > > S3AN board ? > > > > I have two devices that will use the above level shifter and supply > > > square waves/pulses to the FPGA. Will the S3AN be able to handel thos= e > > > devices without crapping out ? > > > > Is the S3AN hardware capable to sample one of the device, which is a > > > pulse generator running at max 50Mhz pulse rate ... (note: pulses are > > > not constant) ? > > > That's a pretty slow level shifter for a 50 MHz input signal. =A0You'd > > probably be better off using some of the LVC series tiny logic gates. > > A +3.3V non-inverting buffer would cover you, and they're all 5V input > > compliant. =A0You can get a dual in a 6 pin SOT-23 or SC70 for about 15 > > cents. > > > -- > > Rob Gaddi, Highland Technology > > Email address is currently out of order- Hide quoted text - > > > - Show quoted text - > > Guys, > > I took a look at the datasheet for the chip that I proposed and found > out that the chip itself is quite slow (thanks for Rob). > > I did some extra research and found this other chip that has a faster > switching characterstic:http://focus.ti.com/lit/ds/symlink/sn74lvc16244a-= q1.pdf > Please let me know if this will run with the application that I intend > on developing.... If you only need a few signals, the 74LVC125 has 4 independent 3-state buffers. It runs on 1.65v ~ 3.6v, and its inputs accept up to 5.5v. -Dave PollumArticle: 137415
Same with me. A staff member from Digilent emailed me with that same link, good as gold now. ReganArticle: 137416
On Dec 15 2008, 11:39=A0am, Peter Alfke <al...@sbcglobal.net> wrote: > In a conventional design (single clock, distributed over global clock > nets, all flip-flops triggered on the same, usually rising, clock > edge, clock frequency not at the max data-sheet limit)dutycycleis irrelev= ant, as long as you do not violate any clock-High > or clock-Low timing. > More exotic designs that use both clock edges or use latches instead > of flip-flops, are (or might be) sensitive to clockdutycycle. > Distributing clocks on non-global lines can seriously affectdutycycle, an= d also cause uncontrolled clock skew and other bad problems. > Don't do that! > Peter Alfke Hi peter, thanks for your response, i am still not configuring my doubt on this (duty Cycle). Here is my clear query: I have requirement saying that "The test case is to test the output signal rcom_tx when fpga_clk is 50 MHz with 40% and 60% duty cycles", and before that i had a test case for same signals on 50% duty cycle. so when i did test on 50% duty cycle i got normal results without any problems, and i am not able to figure out if i change to 40% and 60% duty cycles than what to expect on output line. As of my knowledge within duty cycle boundary limit the output doesn't affect, but out of boundary change in duty cycle is the only expectancy. If possible could you please give me any example in explaining this concept. ThanksArticle: 137417
I read a paper called "Death of the RLOC?" a long time ago where the performance of floorplanned designs was compared with the performance of the same designs where no floorplanning was used. The conclusion of the paper was that floorplanning was still very useful. However, this paper is from 2000 and much has obviously happened in the area of place and route algorithms since then. I am not myself aware of any newer investigation into this area even though a lot has happened in the area of automatic placement and routing. Is anyone aware of a newer comparison than this one? Or for that matter an investigation of how much you can gain by using manual routing in addition to manual floorplanning. /AndreasArticle: 137418
Hi getting really desperate, I have to get MPMC2 v 1.9 based V4 sytem working this week. but it has ethernet crash in maximum 10 hours. the problem has been found: in the MPMC2 ip core = mpmc2_cdmac_ll_cntl.v there are timeouts I assume they are not correct, or there is something around the timeout processing when the error comes (once in about 10 hours) then descriptors in memory are ALL 100% curr_desc pointer regs are are OK but the next_desc values fetched from RAM are bad (wrong address or old fifo content maybe) my assumption is that the descriptor read process timeouts. in the ll_ctrl.v are 3 timeout counters increasing their timeout values DID NOT solve the problem. i am close to belive the problem is V4 FIFO hardware errata but, even if the hardware problem can not be fixed, there is obvious software workaround after the crash, all i need is to restart the DMA ! but after one restart attempt of the DMA it does restart.. it does start to process the RX descriptors. and RX interrupts come but.. the DMA does not writre any data to memory and does not set completed bit. so here are rewards: 500EUR for the IP core fix (other then increase the timeouts what didnt fix the problem) 250EUR for the fix to properly restart the DMA engine so that it can continue after being stopped by software the rewards are valid as long as i have not solved the problem. if i get it working myself i will immediatly post tat c.a.f. the solution has to be applicable for MPMC2 v 1.9 upgrade of the complete system to MPMC3 is not an option (we do not have the time) Antti Lukats who does want to move on, and not to fight with Xilinx bugs any more.Article: 137419
> That is how I started, but didn't know how to finish it. > (how to generate several IRQs on one pin) You haven't defined what you want properly, your first post said.... "I need a 1kHz IRQ in my project. My main clock is 20MHz." You haven't defined what other interrupts you need, what your 'ack' mechanism is etc. One comment... "rising_edge(RD)" You probably don't want to do this, use your master 20MHz clock to synchronise all your external signals and use the re-timed signals to drive the internal logic. Do a bit of googling on synchronous FPGA design and how to handle asynchronous inputs. Nial.Article: 137420
On Jan 14, 6:34=A0pm, aleksa <aleks...@gmail.com> wrote: > > I've added two checks in my IRQ routine: > > 1. read status reg and check if at least one flag is set. > =A0 (check for glitch - never happened) > > 2. after servicing each IRQ, issue ACK and re-check if flag still set. > That happened (the flag was set even though I've issued ACK) so I've > reorganized everything like this: > You're attacking the symptom and not getting to the root cause of the problem. Whenever you come across some behaviour like "the flag was set even though I've issued ACK" the root cause, with nearly 100% certainty, is failing timing which is caught by performing timing analysis...and in this case, I'm suspecting the particular source of failure will be either in clock domain crossing problems or incorrectly handling asynchronous inputs. > > What can I do to correct this? > Perform static timing analysis, paying particular attention to - Places where you a signal is generated by one clock signal but used by logic that is clocked by some other signal. - Input signals to the design that you have no guarantee of when they might switch relative to the clock signal that samples them. Kevin JenningsArticle: 137421
I'm trying to find a 64-point FFT/IFFT core. Target is Actel IGLOO family. Needs to run fast enough to complete in 3.2us, which is tough in an IGLOO. Actel has a free FFT core but it is not quite fast enough. It's a radix-2 core, which is not optimal for this application. Radix-4 would be better. I've looked at the cfft core on Opencores and it may work for us, but also want to check commercial options. Thanks, RobArticle: 137422
I have Windows XP with SP3. Can I install Webpack on this OS? The Webpage states that i would need XP Pro. I care not to upgrade at this point but this is getting rediculus with Xilinx. They offer products but very limited scope of OS's. Right now I have 9.2 SP4. jamesArticle: 137423
On Thu, 15 Jan 2009 13:52:12 -0500, james <george@washington.edu> wrote: >I have Windows XP with SP3. Can I install Webpack on this OS? The >Webpage states that i would need XP Pro. I care not to upgrade at this >point but this is getting rediculus with Xilinx. They offer products >but very limited scope of OS's. Right now I have 9.2 SP4. Check over on the Xilinx forums. A couple of threads from Xilinx tech support confirm that XP Home is not a tested or supported OS *but* ISE 10.1 will install and run okay. E.g., <http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=1713> -- Rich Webb Norfolk, VAArticle: 137424
Hi, I wrote some code in VHDL and I would like to create a core targeting Xilinx Spartan-3E devices. I am clueless of how to proceed with that. 1) I can synthesize the code using XST with an XCF timing constraint file which will create an NGC file. Is that considered a CORE? 2) Will the NGC file contain the timing information from the XCF timing constraint file? 3) Is there a way to actually area constrain it during synthesis? Thanks for the help, Amish
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