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Messages from 137725

Article: 137725
Subject: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
From: "HT-Lab" <hans64@ht-lab.com>
Date: Wed, 28 Jan 2009 12:43:48 -0000
Links: << >>  << T >>  << A >>

"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message 
news:0tg0o4tt9prmne7ggbudf427o8cqhc1rld@4ax.com...
> On Wed, 28 Jan 2009 11:29:23 -0000, "HT-Lab" wrote:
>
>>The human brain is not that
>>well suited to think concurrently
>
> I absolutely, fundamentally disagree.
>
> If you're stuck in a purely-sequential straitjacket,
> you are forced to jump through absurd hoops to
> express concurrent activity.

That is not the point, all I am saying is that writing sequential code is 
easier than concurrent code. If you were asked to develop say an IP stack 
and the choice of language would be yours (ignore end application 
performance etc), would you go for VHDL/Verilog or for C/C++? (fill in any 
sequential language you prefer).

> What could be more
> natural than to say (or think) "Do XYZ; but while
> you're doing it, do as much of ABC as you can do
> without knowing the results of XYZ"?

OK, if you have this information than fine, pass it on to the tool. However, 
I believe that in most cases you just want to give the tool some 
performance/area constraints and let it rip on your code.

Hans
www.ht-lab.com


> The widespread
> public distaste for concurrent descriptions simply
> reflects the fact that our tools for writing those
> descriptions are poorly matched to people's
> expectations.  Above all else, what's needed is
> flexible composition of parallel and sequential
> descriptions, together with clear and intuitive
> ways to express synchronisation.  CSP works for
> me, but not (it seems) for everyone.  Typical
> real-time operating systems seem to me to make
> a truly lousy job of it, being designed for
> convenience of implementation rather than for
> expressive power.
>
> Just my $0.02.
> -- 
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.bromley@MYCOMPANY.com
> http://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated. 



Article: 137726
Subject: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 28 Jan 2009 12:58:30 +0000
Links: << >>  << T >>  << A >>
On Tue, 27 Jan 2009 18:17:41 -0800 (PST), jleslie48
<jon@jonathanleslie.com> wrote:

>On Jan 27, 7:08 pm, Brian Drummond <brian_drumm...@btconnect.com>
>wrote:

>~Seriously; if you can treat this "bbfifo.vhd" as a black box, go
>ahead
>~ and use it.
>
>you're the second person today to tell me that.  That's actually a bit
>of a
>comfort.  So any throttling of the 16 bit buffer will have to be done
>outside of
>the bbfifo.vhd.  I can live with that.

That's what the "half full" and "full" flags are for: 
if it's full, stop writing!

If you need a bigger FIFO, or one with different features, (e.g. 16 bits
in, 8 bits out) fire up Coregen and you'll have one in a few minutes,
with a template to help you use it.

Good luck

- Brian

Article: 137727
Subject: Re: What software do you use for PCB with FPGA ?
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 28 Jan 2009 13:20:18 +0000
Links: << >>  << T >>  << A >>
On Wed, 28 Jan 2009 00:49:17 -0800 (PST), rickman <gnuarm@gmail.com>
wrote:

>On Jan 28, 3:01 am, secure...@gmail.com wrote:
>> Hi Brian Drummond
>>
>> > It may be worth looking athttp://www.freepcb.com/
>> > I tried this last year and it looked OK for a 676 pin 1mm BGA.
>> > (If you cross-check the Gerber output carefully!) I didn't get as far as
>> > finishing the board though.
>>
>> But with CS486, the pins are very close, 0.8 mm ...
>
>That doesn't really affect a choice of design software.  0.8 mm is
>actually fairly large in terms of the layout tools and PCB
>technology.  It will be the via sizes and track widths that challenge
>the board makers (although there are plenty who can makes these
>boards).  The PCB tools are selected more on ease of use and "special"
>features you may need.  A 0.8 mm BGA does not require any "special"
>features from the software.

It does matter in PCB123 software because that's tied to a specific
low-cost PCB manufacturing flow where small holes aren't available.
Otherwise Rickman is correct.

>Be sure to check with the chip maker for the details of the pads and
>included vias.  They want your design to work and have lots of info on
>how to do that.

And THAT's the important point. With 0.8mm BGA you will have to get a
via between 4 adjacent balls, with a pad large enough to maintain a
recommended annular ring around the smallest hole they can drill
(usually around 0.3mm) yet small enough to maintain a recommended
clearance from the pads.  Inner layers can be harder - you might need to
get a track out between adjacent vias.

Draw it out on paper, add up the manuf's recommended sizes, and see if
it'll all fit.

http://www.sunstone.com/pcb-capabilities/manufacturing-capabilities.aspx
is one example; talk to your own local guys too.

From memory, 1mm BGA would JUST fit their full featured flow; I think
0.8mm would be well into their "custom quote" regime...

Xilinx also have app notes on PCB layout.

(FWIW I started out looking at CS484 but backed off to 1mm FG676.)

- Brian

Article: 137728
Subject: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Wed, 28 Jan 2009 13:45:12 +0000
Links: << >>  << T >>  << A >>
On Wed, 28 Jan 2009 11:36:45 +0000, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

>On Wed, 28 Jan 2009 00:35:26 +0000, Brian Drummond wrote:
>
>>In one sense, signals are already very similar to occam's
>>channels, in that their events communicate synchronisation. 
>
>For sure, but there's a big difference: signals are 
>broadcast and non-negotiated.  occam channels handshake 
>(rendezvous) between a single source and a single sink.

Thanks for an excellent summary of stuff I was hazy on.

>To do that in HDL requires at least two signals, one in
>each direction, with all the fuss and poor encapsulation
>that entails. 

Signals in both directions again...

>Of course, the Ada task entry rendezvous does all that
>occam channels do, and more; it's something I sorely
>miss in HDLs, especially when writing testbenches.

Heh, maybe we need Ada2Hardware rather than C2Hardware.
VHDL might give us something of a head start there...

> I'm just saying that
>we could move on a little further, but there doesn't 
>seem to be any collective appetite for doing so.

I'm not so sure there's no appetite, but the path isn't exactly clear.

We can identify a few shortcomings in the language, but then what? 

I'm sure bidirectional elements in record ports (and the reason it can't
be done) has been discussed at length while I was taking a nap... 

Another missing feature is "out" generics; I would like an "out" mode
generic on my divider to say its latency is 8 clock cycles (versus 12
for another architecture) and let instantiating blocks adjust their
pipelines automatically. 
There are other approaches but I still find myself adjusting pipelines
by hand.

But these two won't get us very far...

>Handshake Solutions offer a CSP-like language "Haste"
>that can be synthesised to asynchronous hardware (using 
>Muller C-elements and various other tricks, I believe) 
>but it seems far-fetched to imagine FPGAs being a viable 
>target any time soon.

Thanks for the pointer in any case.

- Brian

Article: 137729
Subject: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Wed, 28 Jan 2009 14:05:44 +0000
Links: << >>  << T >>  << A >>
"HT-Lab" <hans64@ht-lab.com> writes:

> "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message 
>> What could be more
>> natural than to say (or think) "Do XYZ; but while
>> you're doing it, do as much of ABC as you can do
>> without knowing the results of XYZ"?
>
> OK, if you have this information than fine, pass it on to the tool. However, 
> I believe that in most cases you just want to give the tool some 
> performance/area constraints and let it rip on your code.
>

Which is exactly the point - if you do know things about parallelism,
the tools need the let you express that to them in an easy and
intuitive fashion.  I also agree with Jonathan that CSP feels a
good way to do it (but maybe we're both weird :).

Sure - we all *want* to the the tools rip and have it do a good job,
but I think that many algorithms will make better use of parallelism
with some hints given to the tools about how to do it.

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 137730
Subject: Re: Replace MAC block with SGMII
From: Antti <Antti.Lukats@googlemail.com>
Date: Wed, 28 Jan 2009 06:06:30 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 27, 6:13=A0pm, sundar <sundar....@gmail.com> wrote:
> Hi All,
>
> I have a MII interface with 10/100 support in which MAC block is used
> as IP in my design.
> I am doing feasibility study of removinf MAC block to external L2
> component and use SGMII to support 10/100/1000.
> Is this possible? Also please let me know how are SerDes Channels
> listed in FPGA datasheets related to SGMII.
>
> Thanks,
> Sundar

just look the gigbabit ref design www.xilinx.com
there is example with SGMII

Antti

Article: 137731
Subject: Re: What software do you use for PCB with FPGA ?
From: David Brown <david@westcontrol.removethisbit.com>
Date: Wed, 28 Jan 2009 15:26:14 +0100
Links: << >>  << T >>  << A >>
Hal Murray wrote:
>> Even when autorouting, you normally want to do *some* manual routing. 
>> Things like switched mode supplies and fine analogue parts often benefit 
>>from manual routing.
> 
> A lot of that sort of stuff "just works" with an autorouter
> if you have a decent placement.
> 

Certainly it will often work fine with the autorouter.  But sometimes it 
will not - you have to check (and perhaps correct) manually.  It is also 
possible to use the autorouter setup to make it much more likely to be 
correct - but it can be easier to pre-route manually.  For example, in a 
switched mode supply you probably want the tracks between the regulator, 
the inductor, and the output capacitor to be short and wide.  If you've 
told the autorouter to use, say, 60 mil tracks, then it will place the 
tracks as requested.  But even with good layout, it might happen to use 
a roundabout route, or vias, to let a different track through the space. 
  Rather than specify autorouter rules tightly enough to force good 
autorouting, it can be easier to manually place the tracks you want and 
let the autorouter do everything else.



Article: 137732
Subject: Re: What software do you use for PCB with FPGA ?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Wed, 28 Jan 2009 15:05:56 +0000
Links: << >>  << T >>  << A >>
secureasm@gmail.com writes:

> Hi,
>
> I have to make a PCB using BGA pinout for FPGA.
>
> What brand of software do you use ?
>
> Place Route manually or automatically ?
>

Manual placement. It's usually the placement that messes things up.

Automatic routing, with timing constraints, and in some cases some
"guidance": a routing scheme which made the router do the hard bits
first.  The benefit (for me) is that I can rip the whole board up and
have it rerouted within a couple of hours. Which is useful when
someone says "can you add ethernet to that board?" when I've just
"finished"...

An autorouter won't be as pretty as a manually routed board, and it
*may* use more layers (but that's not a given), so if you are planning
high-volumes the trade-off might be worth it.  But think carefully
about what you gain from a good autoroute setup in terms of design
flexibility.  Of course, if your designs are all well specced up front
and no-one ever changes their mind, it's no problem :)

But, as someone else said - you need a *good* autorouter

> Which plans to use and how ?
>
> For the width of the tracks ?
>

That depends on all sorts of things - do you want controlled impedance
tracks?  How many are you making - what yield do you want?

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 137733
Subject: Re: What software do you use for PCB with FPGA ?
From: DJ Delorie <dj@delorie.com>
Date: 28 Jan 2009 11:33:34 -0500
Links: << >>  << T >>  << A >>

rickman <gnuarm@gmail.com> writes:
> > But with CS486, the pins are very close, 0.8 mm ...
> 
> That doesn't really affect a choice of design software.

Agreed.  Even PCB can do down to 0.01 mil traces, holes, etc - but
finding a FAB house who can *make* such a board would be tricky.

Article: 137734
Subject: Re: What software do you use for PCB with FPGA ?
From: Antti <Antti.Lukats@googlemail.com>
Date: Wed, 28 Jan 2009 08:53:38 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 28, 6:33=A0pm, DJ Delorie <d...@delorie.com> wrote:
> rickman <gnu...@gmail.com> writes:
> > > But with CS486, the pins are very close, 0.8 mm ...
>
> > That doesn't really affect a choice of design software.
>
> Agreed. =A0Even PCB can do down to 0.01 mil traces, holes, etc - but
> finding a FAB house who can *make* such a board would be tricky.

0.01 mil??

i would not that call it PCB any more

below 100micro yes, but 0.01 mil =3D=3D 0.00025 mm !!

one PCB that i have here needs little modifications has 0.09 mm
tracks, that is ok
somewhat below that too, but 0.00025 ?

Antti


Article: 137735
Subject: Re: What software do you use for PCB with FPGA ?
From: rickman <gnuarm@gmail.com>
Date: Wed, 28 Jan 2009 09:05:04 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 28, 5:34=A0am, Alex Freed <alex_n...@mirrow.com> wrote:
> secure...@gmail.com wrote:
> > Hi Alex,
>
> >> Even the best autorouters make ugly boards.
>
> > It seems that all producers of software pcb, pointing to this
> > "Autoroute" are all lies ?
>
> They are not. Autorouters do automatic routing as advertised.
> The only problem is that the results can not be compared
> with manual routing. Maybe I just don't know how to use them
> right, but nobody I know uses autorouting for serious work.
> Sometimes you can let an autorouter do part of the job.

I think it is a bit extreme to say that "nobody" uses autorouting for
"serious" work.  Autorouting is a very useful tool to get a layout in
a short amount of time.  Like any tool, you need to know how and when
to use it best.  I can assure you that considering the money spent on
the high end autorouters, that ***somebody*** must be using them for
"serious" work.

I tried to use an autorouter with one of the open source packages, but
got nowhere with it and rather than spend time trying to figure it
out, I just did the route manually.  The other "serious" design I laid
out myself I did by hand because of it was a ***very*** tough board to
design and I didn't expect the tool to be able to complete it at all,
much less give a "good" result.

Regardless of whether you use an autorouter or do the routing
manually, it is essential to have a set of design rules and to make
sure to correctly set up the software to enforce those rules.

Rick

Article: 137736
Subject: Re: Problems when I download and install Xilinx ISE 10.1. Help please.
From: james <george@washington.edu>
Date: Wed, 28 Jan 2009 12:20:18 -0500
Links: << >>  << T >>  << A >>
On Thu, 22 Jan 2009 09:49:59 -0800 (PST), fl <rxjwg98@gmail.com>
wrote:

|Hi,
|I encount problems when I download Xilinx ISE 10.1. When I go through
|with its default selection, it choses proxy mode (The 2nd of the three
|options). The error is:
|
|Read Operation Failed
|
|
|
|If I select direct Internet connection, the following error pops up:
|
|The following error was encounted during installation:
|11:Archive could not be allocated..
|
|
|I don't know how to deal with it. Could you help me? Thanks a lot.
|-------------

I had issues with an extrememly slow connection when using the
webinstaller. It would just hang for minutes and look as if it was
doing nothing. Yes I have 3.0 Megabit ADSL. I ended up downloading the
whole install file of 2.4 Gig. It installed and am very happy with it
on  Windows XP SP3 32bit. 

james

Article: 137737
Subject: Re: XST Makes Odd Choice
From: Muzaffer Kal <kal@dspia.com>
Date: Wed, 28 Jan 2009 09:41:33 -0800
Links: << >>  << T >>  << A >>
On Wed, 28 Jan 2009 09:33:51 +0100, "Jan Bruns"
<testzugang_janbruns@arcor.de> wrote:

>
>"Muzaffer Kal":
>> An integer is a signed entity so if you're decrementing it, the first
>> time n-1 becomes less than zero is when n == 0. I think the idea was
>> that divider reg would get a decrement operator generator by carry
>> chain and then the final carry being set would indicate n-1 becoming
>> negative. It's a cute idea but synthesizer probably is not smart
>> enough to do operator sharing at the output of the decrementer and
>> instead builds a zero decoder at the output of the register.
>
>Ah, ok. Would this still apply if n was an array of signals?

If you mean a bit vector, that would be interpreted as unsigned so n-1
would wrap around to a positive value so '(n-1) <0' would always
evaluate to false. Hopefully the simulator would tell you that or you
would catch it in simulation.
--

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

Article: 137738
Subject: Re: fpga mac controller with tcp/ip/dhcp
From: "nitinbabukm" <nitinbabukm@gmail.com>
Date: Wed, 28 Jan 2009 11:48:59 -0600
Links: << >>  << T >>  << A >>
>On 9 Gen, 16:20, sundeep <sundeep.bhan...@gmail.com> wrote:
>> On Jan 8, 5:26=A0pm, Mike Treseler <mtrese...@gmail.com> wrote:
>>
>> > sundeep wrote:
>> > > hello,
>>
>> > > I am looking to create amaccontroller which includes tcp/ip/dhcp.
>> > > Where can I get information on how to do this?
>>
>> >http://groups.google.com/groups/search?q=3Dfpga+arp+udp+dhcp
>>
>> so it seems tcp/ip/dhcpwould take up too many resources using anfpga
>> and a microcontroller would be a better approach for this.
>>
>> I wasn't able to find information on how to simulate a mac controller.
>> Where can I find flow charts/block diagrams for this?
>
>Hi,
>
>I have develop a UDP sender and Receive core in VHDL.
>I have a spartan3e and ths core uses only 8 % of resources...but with
>some tuning it can be lower.
>
>The main problem (now) is ARP management.
>if you are interested contact me at alexgiul@hotmail.com.
>
Actually Cyclone 3 has provision to add a mac layer +Niche tcp stack also
can be put with a nios processor, altera people have done it...
so try altera website for app notes..
Regards
Nitin Babu K.M.




Article: 137739
Subject: Re: What software do you use for PCB with FPGA ?
From: james <george@washington.edu>
Date: Wed, 28 Jan 2009 12:49:26 -0500
Links: << >>  << T >>  << A >>
On Tue, 27 Jan 2009 00:50:07 -0800 (PST), secureasm@gmail.com wrote:

|Hi,
|
|I have to make a PCB using BGA pinout for FPGA.
|
|What brand of software do you use ?
|
|=============

That will eventually be your choice. Since you are using a BGA package
and an FPGA I can assume you are in the range of 256 or more pads. In
that case you are going to need a layout program that supports at
least 8 routing layers. In the $1000 range there is Eagle without the
autorouter. $1500 with autorouter. Eagle Pro will do 16 route planes.
The Eagle autorouter is functional in my opinion. 

Altium, Cadence/Mentor are other choices but they are going to set you
back more. I have used Cadence tools and like them. It has been about
9 years ago that I used Mentor Graphics and hated it. Too much lilke
Cads 4X and older obsolete layout program.  
 
|Place Route manually or automatically ?
|
|================

I personally do not like autorouters. Spectra is about the best
autorouter and it is not cheap. Autorouters are good for test boards
where you have large area and no RF or low frequency RF signals.
Personally manual is better but takes longer. If you do something for
feasability check then maybe an autorouter is okay.  

|Which plans to use and how ?
|
|+++++++++++++++

Depending on which FPGA and how many voltages. Figure at least one
power plane and two ground planes.   


|For the width of the tracks ?
|
|-------------------------

That depends on the fab house you use. They vary. Figure at least 6
mil tracks and 6 mil spacing.

james


Article: 137740
Subject: Re: What software do you use for PCB with FPGA ?
From: DJ Delorie <dj@delorie.com>
Date: 28 Jan 2009 13:03:00 -0500
Links: << >>  << T >>  << A >>

james <george@washington.edu> writes:
> In that case you are going to need a layout program that supports at
> least 8 routing layers. In the $1000 range there is Eagle without
> the autorouter. $1500 with autorouter. Eagle Pro will do 16 route
> planes.

You forgot about the $0 range - most free software EDA programs don't
put arbitrary limits on board layouts.  PCB, for example, supports 16
layers as-is, but can be recompiled for as many as you need, and has
no limits on number of pins/pads or size of board.  It comes with a
free autorouter too.  I don't know what KiCad's limits are, but I'm
guessing it can do all that also.

While the commercially-supported packages have thier place, you don't
have to *assume* that you need one if it's not appropriate for your
project.  I know of commercial projects done with PCB that include
very large fine pitch BGAs, I've done 01005's and 0.4mm pitch TSSOPs
myself.

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Subject: Re: XST Makes Odd Choice
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On Wed, 28 Jan 2009 00:41:42 -0800 (PST)
rickman <gnuarm@gmail.com> wrote:

> On Jan 27, 9:50 pm, General Schvantzkoph <schvantzk...@yahoo.com>
> wrote:
> >
> > > ----------------------------------------------------------------------
> >
> > > MAKE_DC_DC: process(clk)
> >
> > > variable toggle     : std_logic := '0';
> >
> > > constant TICKS_CYC  : integer := 32_000_000 / 128_000; constant
> > > TICKS_HALF : integer := TICKS_CYC / 2;
> >
> > > variable divider    : integer
> > >     range 0 to TICKS_HALF-1 := TICKS_HALF-1;
> >
> > > begin
> > >     if rising_edge(clk) then
> > >         DCLK    <= toggle;
> >
> > >         if ( (divider - 1) < 0 ) then
> > >             divider := (TICKS_HALF-1);
> > >             toggle  := not toggle;
> >
> > >         else
> > >             divider := divider - 1;
> > >         end if;
> > >     end if;
> > > end process MAKE_DC_DC;
> >
> > > ----------------------------------------------------------------------
> >
> > I always add 1 bit to my counters and the use the MSB to do the
> > reset, for example if I wanted to divide by 256 I'd do,
> >
> > reg [8:0] cntr;
> >
> > always@(posedge clk) begin
> > if(sync_rst || cntr[8]) begin
> >   cntr <= 1;
> > end
> > else begin
> >  cntr <= cntr + 1;
> > end
> >
> > This forces the synthesizer to use the sync set/reset inputs and the
> > reset path will only have 1 LUT delay in it.
> 
> I tend to think in terms of hardware and once I know exactly what I
> want from the hardware, I "describe" this in the HDL.  In this case,
> the carry out is not registered, so it can't really be described
> inside the clocked process.  I hedge with the word "really" because
> this may be possible with the right coding style using variables.  But
> I prefer not to bother too much with "tricky" coding styles and to use
> templates I have the most confidence in.
> 
> So I would code the counter logic as combinatorial logic and then
> assign it to a register.  Of course I can't say for sure this will
> give you what you want, but I think it has a good chance.
> 
> constant TICKS_CYC  : integer := 32_000_000 / 128_000;
> constant TICKS_HALF : integer := TICKS_CYC / 2;
> 
> signal downcntr    : integer
>     range -1 to TICKS_HALF-1 := TICKS_HALF-1;
> signal divider... toggle... togglecntr...
> 
> MAKE_DC_DC: process(divider, toggle)
> begin
>   if rising_edge(clk) then
>         DCLK    <= toggle;
>     downcntr <= divider - 1;
>     if (downcntr < 0) then
>       divider := (TICKS_HALF-1);
>       togglecntr := not toggle;
>     else
>       divider := divider - 1;
>     end if;
>   end if;
> end process MAKE_DC_DC;
> 
> MAKE_DC_DC: process(clk)
> begin
>   if rising_edge(clk) then
>     divider := mod(downcntr, TICKS_HALF);
>     toggle  := togglecntr;
>   end if;
> end process MAKE_DC_DC;
> 
> If this form gives you the carry test that you are looking for, then
> maybe you can combine the two processes into one and get the same
> logic.  The trick will be to use variable assignments to set the
> variable and compared to -1 before the final assignment that is
> latched into the register.  I haven't tested any of this, so I may be
> all washed up.  I don't typically use variables.
> 
> I'm actually more interested in the fact that you consider
> "spelunking" in the FPGA editor to be "fun"...  ;^)
> 
> Rick

Short of a good spelunk, your two choices in knowing whether your code
rendered out the way you want are a) write the code at such a low
abstraction level that the synthesizer can't help but give you what
you're asking for, or b) decide you just don't care that much.

Interestingly enough, sometimes even low-leveling the code doesn't
help.  Now that it's become a matter of personal vendetta, I'm a little
mortified to find out that not even this renders using the carry-out.

----------------------------------------------------------------------

-- Generation of 128 kHz from 32 MHz takes 125 cycles high, 125 low;
-- We'll count 124 downto 0, then repeat.
--

subtype t_clk_div is signed(7 downto 0);
constant CLK_DIV_MAX    : t_clk_div := TO_SIGNED(124, t_clk_div'length);

signal toggle           : std_logic := '0';
signal divider          : t_clk_div := CLK_DIV_MAX;
signal next_divider     : t_clk_div := CLK_DIV_MAX;

begin

next_divider <= divider-1;

MAKE_DC_DC: process(clk)
begin
    if rising_edge(clk) then
        DCLK    <= toggle;
        
        if ( next_divider(next_divider'high) = '1' ) then
            divider <= CLK_DIV_MAX;
            toggle  <= not toggle;
            
        else
            divider <= next_divider;
            
        end if;
    end if;
end process MAKE_DC_DC;

end architecture;

----------------------------------------------------------------------

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 137741
Subject: UART RS232 "hello world" program trial and terror.
From: jleslie48 <jon@jonathanleslie.com>
Date: Wed, 28 Jan 2009 11:56:48 -0800 (PST)
Links: << >>  << T >>  << A >>
Ok,

continuing with the RS232 and Ricks pseudo code for sending out a 16
character message:
--------------------------------------------------------------------------------
constant TstData : string(0 to 15) := "Testing 1, 2, 3!";
signal TxCntr : integer range 0 to 16;

TxNxtData <= TstData (TxCntr);

-- Data source control, provide string data to the UART, repeat every
16 chars
process SelectCntr ( clk, reset ) is
begin
  if (reset = '1') then
    TxCntr <= 0;
  elsif ( rising_edge (clk) ) then
    if ( TxRdy = '0' ) then
      TxWrite <= '0';
    else
      if ( TxWrite = '0' and TxCntr <> 16 ) then
        TxWrite <= '1';
        TxCntr <= TxCntr + 1;
      end if;
    end if;
  end if;
end process;

---------------------------------------------------------------------------------


I cleaned this up a bit, used my variable names,  to get a synth to
work:
----------------------------------------------------------------------


  function to_slv(c: character) return std_logic_vector  is
  begin
    return std_logic_vector(to_unsigned(character'pos(c), 8));
  end;



  SIGNAL system_startup  : STD_LOGIC  := '1';
  SIGNAL txwrite         : STD_LOGIC  := '1';
  SIGNAL txrdy           : STD_LOGIC  := '0';
  SIGNAL TxNxtData       : STD_LOGIC_VECTOR( 7 downto 0 );
  SIGNAL init_done       : STD_LOGIC  := '0';
  signal TxCntr          : integer range 0 to 17;

  constant TstData : string(1 to 16) := "Testing 1, 2, 3!";


    TxNxtData <= to_slv(TstData(TxCntr));



-- Initialize01
--
-- Lets put out a hello world message once when the system first
starts up,
--
-- system_startup, init_done are flags to start the run and signal th
end.
-- txrdy and txwrite, do some ping_pong thing to get the chars out I
think.
-- lets see.
--
initialize01: process ( CLK_16_6MHZ, system_startup )
begin
  if (system_startup = '1') then --1{
    TxCntr         <= 1;
    system_startup <= '0';
    init_done      <= '0';
    TxRdy          <= '0';
  elsif ( rising_edge (CLK_16_6MHZ) ) then    --1
    if ( TxRdy = '0' ) then   --5{
      TxWrite <= '0';
    else
      if ( TxWrite = '0' and TxCntr /= 17 ) then --4{
        TxWrite <= '1';
        TxRdy <= '0';
        TxCntr <= TxCntr + 1;
        if (init_done = '0') then  --3{
          TX_DATA_IN <= TxNxtData  ;
          end if;  --3}
      elsif (TxCntr = 17) then  --4
         init_done <= '1';
      end if; --4}
    end if;   --5}
  end if; --1}
end process initialize01 ;
----------------------------------------------------------------------

the act of getting through the syntax errors was very useful,
particularly since
when I added the >>>TX_DATA_IN <= TxNxtData  ;<<< line
I got 8 errors relating to "multiple line drive" or something to that
effect.

Well you guys beat it into my head enough times, and instantly
realized that and I had
two wires hooked up to TX_DATA_IN that could both send in signals at
the same time, and
that would be a no-no.  That is when I added the "init_done" boolean
both here and in the
regular transmission producer, process p7 which I renamed to the more
appropriate, uart_echo:
________________________

--p7
uart_echo:  PROCESS ( CLK_16_6MHZ, UART_RESET_BUFFER,
RX_READ_BUFFER_STB, RX_DATA_OUT( 7 DOWNTO 0 )  )
BEGIN
     IF ( CLK_16_6MHZ = '1' AND CLK_16_6MHZ'EVENT ) THEN
          IF ( UART_RESET_BUFFER = '0' ) THEN
               IF ( RX_READ_BUFFER_STB  = '1' ) THEN
                    if ( init_done = '1') then
                         TX_DATA_IN  <= RX_DATA_OUT;
                         end if;
               END IF;
          END IF;
     END IF;
END PROCESS uart_echo;
__________________________

note the TX_DATA_IN line is now dependent on the init_done flag.

well then after being all proud of my synth coming up clean (well no
errors, and 23 warnings, I didn't say spotless...) I actually took the
plunge and loaded up my board and ran it.

Yuck.

no hello world message, and even the uart_echo is now broken.

So, taking the advise I was given here, its time to testbench this
puppy and see what all my system_startup, init_done, etc are doing.
Lets see if I can make up a good testbench to this thing,


Article: 137742
Subject: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 28 Jan 2009 20:54:49 +0000 (UTC)
Links: << >>  << T >>  << A >>
HT-Lab <hans64@ht-lab.com> wrote:
 
> It is less likely since Mentor is not the only company that is trying to 
> crack the panacea of hardware design using a sequential language. Cadence 
> recently announced their C to Silicon compiler and only a few days ago 
> Synfora announced a 250% revenue growth. All I can say is *great*, I am a 
> strong believer that this is the way forward. The human brain is not that 
> well suited to think concurrently and hence engineers tend to write many 
> more correct lines of code in a sequential language than in an 
> HDL language. 

Unfortunately computers aren't very good at abstract thinking, such
as is required to turn a sequential algorithm into a non-sequential
algorithm.  

> Unfortunately as far as I know all these tools still only work on datapath 
> and sorting out the control part is a very difficult nut to crack.

For the easy cases I can imagine it, or it may just result in a
huge block of hardware where each sub-block is used only once.
That doesn't really help much.

-- glen

Article: 137743
Subject: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 28 Jan 2009 21:02:29 +0000 (UTC)
Links: << >>  << T >>  << A >>
Martin Thompson <martin.j.thompson@trw.com> wrote:
(snip)
 
> Which is exactly the point - if you do know things about parallelism,
> the tools need the let you express that to them in an easy and
> intuitive fashion.  I also agree with Jonathan that CSP feels a
> good way to do it (but maybe we're both weird :).

I have worked with systolic array implementations of
dynamic programming algorithms, and they look completely
different from software implementations.  

If you want an example, look at the software and hardware
implementations of CRC32.  In software it can be very
easily done a byte at a time with a 256 word lookup table.

The hardware (high speed) implementations are completely
different because what is available and fast is completely
different.
 
> Sure - we all *want* to the the tools rip and have it do a good job,
> but I think that many algorithms will make better use of parallelism
> with some hints given to the tools about how to do it.

-- glen

Article: 137744
Subject: Microblaze and NAND flash
From: m <martin.usenet@gmail.com>
Date: Wed, 28 Jan 2009 13:13:28 -0800 (PST)
Links: << >>  << T >>  << A >>
I am working on a V5 project that requires uClinux running on
Microblaze to have nonvolatile storage.  I would like to use a large
NAND flash, such as

http://www.numonyx.com/Documents/Datasheets/NAND08GW3C2B.pdf

I can't seem to find an interface in platform studio to install this
type of an interface.  I need an 8 bit bus with ALE as opposed to
large separate address and data busses.

Does such a thing actually exist for MB?  Anyone know how uClinux
might handle this or the best approach to making it all work?

Thanks,

-Martin

Article: 137745
Subject: new source wizard doesn't seem to work.
From: jleslie48 <jon@jonathanleslie.com>
Date: Wed, 28 Jan 2009 13:26:20 -0800 (PST)
Links: << >>  << T >>  << A >>
OS: windows XP PRO
ISE version: 10.1.103

project properties:
cat:         All
Family:    Virtex2P
Device:    XC2VP30
Package: FF896
Speed:     -7

Top-level source type :  HDL
synt tool:                  :  XST
simulator                  :   ISE Simulator
Prefferd language:     :   VHDL

Enable enhance design summary : <check>
Enable Message Filtering:             <         >
display incremental messges:       <check>


synth, implement, and genearate all work successfully.

I switch 'sources for' from  implementation to 'behavioral
simulation'

I right click on xc2vp30-7ff896
  pick 'new source'

select 'vhdl test bench'
 enter a filename 'abcd'
add to project <check>
click next,

new screen,
select a source with which to associate the new source,
the main process is already in blue,
click next,

new screen,
Project Navigator will create a new skeleton source with the following
spec:
Add to Project: Yes
Source Directory: C:\jon
\fpga_uarted_01\2009_01_26\LOKI_New_H_Project_VHDL\Code_Versions\10 -
New_Xilinx_Wrap_Data\LOKI_Top
Source Type: VHDL Test Bench
Source Name: abcd.vhd

Association: LOKI_TOP

I click finish, new screens all disappear, and the only thing under
xc2vp30-7ff896 is the same as before.

no abcd.vhd added, and I searched the whole C: drive no abcd.vhd.

what am I doing wrong?


Article: 137746
Subject: Re: new source wizard doesn't seem to work.
From: Alan Fitch <apfitch@invalid.invalid>
Date: Wed, 28 Jan 2009 22:01:21 +0000
Links: << >>  << T >>  << A >>
jleslie48 wrote:
> OS: windows XP PRO
> ISE version: 10.1.103
> 
> project properties:
> cat:         All
> Family:    Virtex2P
> Device:    XC2VP30
> Package: FF896
> Speed:     -7
> 
> Top-level source type :  HDL
> synt tool:                  :  XST
> simulator                  :   ISE Simulator
> Prefferd language:     :   VHDL
> 
> Enable enhance design summary : <check>
> Enable Message Filtering:             <         >
> display incremental messges:       <check>
> 
> 
> synth, implement, and genearate all work successfully.
> 
> I switch 'sources for' from  implementation to 'behavioral
> simulation'
> 
> I right click on xc2vp30-7ff896
>   pick 'new source'
> 
> select 'vhdl test bench'
>  enter a filename 'abcd'
> add to project <check>
> click next,
> 
> new screen,
> select a source with which to associate the new source,
> the main process is already in blue,
> click next,
> 
> new screen,
> Project Navigator will create a new skeleton source with the following
> spec:
> Add to Project: Yes
> Source Directory: C:\jon
> \fpga_uarted_01\2009_01_26\LOKI_New_H_Project_VHDL\Code_Versions\10 -
> New_Xilinx_Wrap_Data\LOKI_Top
> Source Type: VHDL Test Bench
> Source Name: abcd.vhd
> 
> Association: LOKI_TOP
> 
> I click finish, new screens all disappear, and the only thing under
> xc2vp30-7ff896 is the same as before.
> 
> no abcd.vhd added, and I searched the whole C: drive no abcd.vhd.
> 
> what am I doing wrong?
> 

Try removing spaces from any paths (i.e. move your project from 10 -
New_Xilinx_Wrap_Data to 10_New...)

regards
Alan

P.S. I'm just guessing - generally spaces in paths and ISE don't mix...

-- 
Alan Fitch
apfitch at ieee
dot org

Article: 137747
Subject: Re: What software do you use for PCB with FPGA ?
From: vladitx <vladitx@nucleusys.com>
Date: Wed, 28 Jan 2009 14:05:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 28, 5:05=A0pm, Martin Thompson <martin.j.thomp...@trw.com> wrote:

> But, as someone else said - you need a *good* autorouter

Or an *excellent* one. ;-)

Autorouters, just like HDL synthesizers and HLL compilers are useful,
but as with any sharp tool you've got to be careful and know where and
how to use it properly.

For the sake of completeness, here's one more CAE choice:
http://bartels.de/bae/bae_en.htm

Article: 137748
Subject: Re: Spartan chip expulses an extrange substance
From: nnadal@terra.es
Date: Wed, 28 Jan 2009 14:15:33 -0800 (PST)
Links: << >>  << T >>  << A >>
On 25 ene, 21:32, nna...@terra.es wrote:
> On 24 ene, 19:38, Gabor <ga...@alacron.com> wrote:
>
>
>
>
>
> > On Jan 23, 5:57=A0am, "Symon" <symon_bre...@hotmail.com> wrote:
>
> > > <nna...@terra.es> wrote in message
>
> > >news:ab3f226a-9695-456d-b60b-fcd08cda835a@35g2000pry.googlegroups.com.=
..>Ihavea new design with a XCS05 based on a well proved design where
> > > > the fpga runs during few minutes and then fails while expulses an
> > > >extrangesubstance from inside the VCC and GND pins, in some pads is
> > > > like spounge-white in other is black, the chip runs cold, never war=
ms
> > > > up. I have a lot of experience on this chip and I have never seen
> > > > that. Then the chip appears to have a few inputs crossed to GND and
> > > > worked never more. We crossed all the VCC pads with wire-wrapping w=
ith
> > > > no results, no current loops. The prototype worked well (this is th=
e
> > > > first series PCB). Any Idea?
>
> > > Did you buy the parts off Ebay?
> > > Syms.
>
> > It doesn't necessarily have to be eBay. =A0There are a number of
> > non-franchised distributors who are not very careful about
> > the source of their chips. =A0If you have the working prototype,
> > check to see if there are obvious differences in the part
> > markings that might indicate that the new part is
> > counterfeit. =A0If you have more parts from the new batch
> > you could also use an ohm-meter to check if the VCC
> > and ground pins are in the right place. =A0One standard
> > counterfeiting method is to take some much cheaper
> > chip in the same package and re-mark it.
>
> > Regards,
> > Gabor
>
> No, I don't have any photo now and extrangelly there was no smoke,
> never in a lot of tests we did, holding my finger over the chip during
> the process I cannot dectect any temperature increment. Yesterday we
> tried to do an "incremental insertion" by inserting the fewest numbrer
> of chips and the problems came before inserting the XCS05. The cpu
> H83003 stops working in few minutes and a +1.5V -1V glitch appeared
> every 4ms in one of the 5V VCC lines lasting 40ns.
> One hypothesis is there were a current loop witch destroyed the
> weakest part, but for me is difficult to accept the idea of destroying
> a chip with this so little glitch. I am in the process of eliminating
> that glitch, not easy.
>
> Thanks to all
> Narcis Nadal- Ocultar texto de la cita -
>
> - Mostrar texto de la cita -

INCREDIBLE!!
the problem was originated by the PCB. There was some resistance or
short circuit in the bus lines wich hangued the cpu and possibly
destroyed the XCS05.
With a 5V supply between the line and GND we eliminated the shorts but
appeared after few minutes. We try to measure the resistance of the
lines with a tester and found to be lower and lower, accelerating the
decrease if we heated the PCB. Anybody knows the explanation of that ?
thank you

Article: 137749
Subject: Re: What software do you use for PCB with FPGA ?
From: james <george@washington.edu>
Date: Wed, 28 Jan 2009 17:17:56 -0500
Links: << >>  << T >>  << A >>
On 28 Jan 2009 13:03:00 -0500, DJ Delorie <dj@delorie.com> wrote:

|
|james <george@washington.edu> writes:
|> In that case you are going to need a layout program that supports at
|> least 8 routing layers. In the $1000 range there is Eagle without
|> the autorouter. $1500 with autorouter. Eagle Pro will do 16 route
|> planes.
|
|You forgot about the $0 range - most free software EDA programs don't
|put arbitrary limits on board layouts.  PCB, for example, supports 16
|layers as-is, but can be recompiled for as many as you need, and has
|no limits on number of pins/pads or size of board.  It comes with a
|free autorouter too.  I don't know what KiCad's limits are, but I'm
|guessing it can do all that also.
|
|While the commercially-supported packages have thier place, you don't
|have to *assume* that you need one if it's not appropriate for your
|project.  I know of commercial projects done with PCB that include
|very large fine pitch BGAs, I've done 01005's and 0.4mm pitch TSSOPs
|myself.
|============

I have working knowledge of some so called "free" software. The likes
of PCB123 and ExpressPCB are good for hobbyist who need only one or
two boards that are two layers and small. Also if they don't care for
soldermask and silkscreen. They are in truth not free. You are paying
for usage of the software in board prices. These houses tend to be
higher in cost for their laminates than others. 

As for Linux based software, I have no knowledge of and therefore
refused to comment on them as I do not run Linux. 

james



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