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If it's a PCI version of the PC104 stack usually the biggest limitation it is the grant/request signals and only 4 available for bus mastering negotiation that are usually the problem. For the money they are spending they could have had a custom board, or boards, with all the features smaller, lighter and cheaper and so on from us. It's not particularly well known but a major part of of our business is either custom derivatives of development boards an/or full custom boards. We actually design and build several times the amount of development boards as customer boards and if it's based on FPGAs we use and parts we can get quickly we can do boards on very short timescales. Our record for a whole new board being designed, manufactured, tested and delivered to the customer is 18 days and that's not a particular unique event not that I would want to that every week. John Adair Enterpoint Ltd. On 22 Mar, 14:59, jleslie48 <j...@jonathanleslie.com> wrote: > On Mar 22, 10:23 am, Brian Drummond <brian_drumm...@btconnect.com> > wrote: > > > > > > > On Sat, 21 Mar 2009 19:19:09 -0700 (PDT), jleslie48 <j...@jonathanlesli= e.com> > > wrote: > > > >On Mar 21, 8:39 pm, Brian Drummond <brian_drumm...@btconnect.com> > > >wrote: > > >> On Sat, 21 Mar 2009 08:10:07 -0700 (PDT), jleslie48 <j...@jonathanle= slie.com> > > >> Otherwise given the cost constraints you mentioned, I'd say you shou= ldn't be > > >> wasting time trying to fit a too-small device. Is your software team= trying to > > >> keep their executable below 4K? > > > >> - Brian > > > >"Is your software team trying to =A0keep their executable below 4K?" > > > >first off the software team is me. =A0For 20 years now I keep getting > > >suckered into these solo missions into [the companies] no man land... > > > >I'm sorry are you referring to $4k or some size requirement of 4k??? > > > I meant 4k bytes. As in, I was trying to find the SW equivalent of sque= ezing a > > hardware design into a Coolrunner... > > > It's a valid thing to do ... sometimes. If it's easy to eliminate the l= arge > > storage that is currently causing problems, and that avoids a board re-= spin for > > example. > > > But often it's a waste of time to conserve a low value resource. > > > I'm sorry I was unclear. > > > > I'm assuming I can load the program > > >into the enterpoint solutions and on powerup they start to > > >function... > > > Look for configuration storage, such as... > > "Drigmorn1 have a M25P40 (4 Mbit) serial flash that is used for both > > configuration of the FPGA and ..." so I'd have to say yes for that one. > > > >The guys on this project have blown their budget for hardware already, > > >at least for this next deliverable, so any $$$ I spend (not counting > > >labor) are being watched carefully. > > >1) Drigmorn1 has a XC3S500E-4CPG132C spartan-3 chip: > > > Xilinx XC3S500E-4CPG132C > > >FPGA Spartan=AE-3E Family > > >500K Gates > > > =A0 =A0Number of Registers =A0 =A0 9312 > > > =A0 =A0RAM Bits =A0 =A0 =A0 =A0368640 > > >Which of these products will do the job and not be too small like the > > >coolrunner? > > > I would expect any of them to be overkill, quite frankly. > > > It should be a few minutes work to select say the Spartan3-100 (the sma= llest > > available on Drigmorn) and synthesize the current design for that, and = see how > > much space is left over. > > > Alternatively you mentioned a PC104 stack - have you seen the Hollybush= I and II > > PC104 cards from the same site? > > > I don't know how PC104 cards stack but it's possible you may just have = to plug > > one of these straight in. Or a larger one may swallow some of the funct= ionality > > from the rest of the stack. > > > - Brian > > Ok good. this is all falling into place now. That's what I wanted to > hear: > "I would expect any of them to be overkill" > I am sick to death of busting =A0out the resources of a device. =A0I want > from now on 10x capable size growth... It just seems so ridiculous in > a prototyping environment to right-size this low-cost items. These > chips are under $100 and in that price range you can get hundreds of > times the performance from one chip to another. =A0This is not the area > to be worrying about overkill. > > I saw that holly bush too. =A0Those guys (ok there were some other > software guys on the team, but strictly C programmers on the PC 104 > stack) have managed to make that PC104 stack 5+ cards already, I'm > pretty sure they said they were over the limit already. =A0Besides I'm > not going near that stack for what they paid for it. =A0That's the stack > that has the $16,000 1553 card, And I'm pretty sure they paid over > $100,000 for some green hills programing suite. =A0And now my PM is > gonna give me a hard time for $700 worth of FPGA boards. =A0How stupid > is that...- Hide quoted text - > > - Show quoted text -Article: 139176
On Mar 22, 2:04 pm, djj08230 <djj08...@gmail.com> wrote: > On Mar 22, 3:00 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > When you have to a production run of more than 1000 units, then you > > worry about right-sizing. Meantime the spartan would still have been > > way cheaper anyway for all their "right-sizing" effort. Right-sizing > > is only important if it saves you something. > > Please, allow me to point in a completely different direction. As you > are a software guy, you have probably considered implementing the > UARTS in a uC. I think a small AVR (or PIC) could easily handle 10 > serial channels, particullarly at slow baud rates. Is there a reason > why you wouldn't follow this path ? > (I am talking about a complete software implementation here) > > It is not about cost, but about development time. > > Josep Dur=E0n "you have probably considered implementing the UARTS in a uC. I think a small AVR (or PIC) " ahh, no I havent. I don't know what those things are: uC, AVR, PIC. I was told our company wants to have things done in FPGA so that is were I have been looking for solutions. I was hired to figure it out on the strength of my wits to keep looking and not give up. I had 10 years of experience in PLC programming, and Prior to this job I spent 10 years on wall st in the forex data processing dept. However, DSP, FPGA, VHDL, were are brand new terms to me when I started with this company and you have just introduced me to 3 more terms. Plus I've hinted at the fact, but not declared it, I am only using the UART as an methodology for controlling a digital signal. I have to speed these things up into the MHZ "baud" rate environment. In addition, without even knowing what a line of VHDL code looked like 3 months ago, I'm getting pretty good at controlling digital signals already. so the development time curve is not that bad. I'd hate to think how much time it will take me to pick out a uC/AVR/PIC solution. It took me 8 man days to program the entire solution to to our product's deficiencies on my Virtex-II Pro, a day to move the code into the coolrunner and on Friday at 1:00pm I fell into the tiger trap on the size problems on the coolrunner. Here it is 2 days later (10 man days ok so I've been working on the weekend) and Its beginning to look like I've got a workaround. I don't see another solution having a faster development time than 2 weeks. Shoot, it took the original boys 3 months just to pick out the coolrunner... and for a nickel I'd give them all an atomic wedgie for being so bone ass short sighted...Article: 139177
On Mar 22, 11:00=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > On Mar 22, 10:51=A0am, Peter Alfke <al...@sbcglobal.net> wrote: > > > On Mar 22, 10:36=A0am, "kadhiem_ayob" <kadhiem_a...@yahoo.co.uk> wrote: > > > > Hi Wang, > > > I think either xnor or xor are possible. The effect is then choosing = seed > > > value. > > > > Implementation can be either in registers or memory. The choice is yo= urs > > > > kadhiem > > > The difference between XOR and XNOR is the illegal (lock-up) state. In > > one case it is all-ones, in the other it is all-zeros. > > Peter Alfke > > Hi Peter, > I don't know if XOR will tranverse all data, excluding the lock-up > state. Maybe there are some reasons why the original paper uses XNOR, > not XOR. > > Weng It's all symmetrical. XNOR gives you a lock-up with all-ones. That keeps the all-zeros a legitimate state. That was the reason I picked XNOR. Nothing else. Peter AlfkeArticle: 139178
On Mar 22, 7:55=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > > It took me 8 man days to program the entire solution to to > our product's deficiencies on my Virtex-II Pro, =A0a day to move the > code into the coolrunner and on Friday at 1:00pm I fell into the tiger > trap on the size problems on the coolrunner. Here it is 2 days later > (10 man days ok so I've been working on the weekend) and Its beginning > to look like I've got a workaround. > > I don't see another solution having a faster development time than 2 > weeks. > > Shoot, it took the original boys 3 months just to pick out the > coolrunner... =A0and for a nickel I'd give them all an atomic wedgie for > being so bone ass short sighted... I know from experience that these man-days thing is not a reliable unit. Sometimes we are talking about different men, sometimes different days. ;) Good luck Josep DuranArticle: 139179
On 22 Mar, 18:15, rickman <gnu...@gmail.com> wrote: > On Mar 22, 2:12=A0pm, Elizabeth D Rather <erat...@forth.com> wrote: > > > Jacko wrote: > > > On 21 Mar, 22:28, rickman <gnu...@gmail.com> wrote: > > ... > > >> Do you really care if you make anyone understand what you are talkin= g > > >> about? > > > > making people understand? If people understand the y do, if people do > > > not understand the may eventaually, if the is such an important need > > > to indoctrinate people, making may be an unsavoury procedure. > > > > Really care? As opposed to virtually care? As in expressing a duty of > > > care? Please elaborate using non circular arguments ... > > > In other words, no. =A0Advice to Rick: =A0give up. > > On one hand I would like to understand his thinking. =A0On the other > hand I also need to spend time thinking for myself and this is being a > time sink. =A0I think I may have pressed too hard and he is seeing me as > an antagonist. =A0So maybe it is time to stop pressing. > > Rick I don't think you pressed to hard. The rotation about the word care and circles of infinite decent, would have just been of topic. Scalability to interleave CPU with memory was a major, major goal of the design. The fact it can be a small thing, with only one core needed to do much embedded work is an offshoot, not a raison d'etre. Test in truth, it would have been easy to crunch the thread earlier had ant's been in strong pain, but this was not necessary. Did you like the BAr stack underflow joke? cheers jackoArticle: 139180
I am sure either traverses all states except its lock state. xor will lock if the value becomes all zeros. Thats why I reset it to non-zero at power up. xnor doesn't need reset(in fpgas) as it can start in all zeros (assuming all ones is not expected at power up). kadhiemArticle: 139181
John, Oh don't worry, you've got me sold. You'll be getting a call from me on Monday morning. I wasn't on the project when they first designed it about a year ago, I was only put on it starting March 1st 2009 to bail them out. I remember when I first heard they bought a $100,000 development suite I jokingly asked did it come packaged in a Porsche 928... I can't believe what they have spent on this project. Anyway the PC104 is the stack version (the squares, the cards in the stack look like the hollybush2: http://www.enterpoint.co.uk/oem_industrial/hollybush2.html I really don't know what the PCI means. I thought it meant "card slot for a PC" but I'm not sure. Again I'm just going by what I heard the other guys talking about. They told me to stay away from the PC104 stack. fine by me. Assuming all goes well I'm gonna end up needing about a 10 of the patch job drigmorn/craignell/raggedstone1 solutions for for this run, and we are gearing up for a real production run after that. We are eventually going to need to minaturize, but I keep reminding the PM to get it to at least work ANY way first. I will definitely be thinking of this conversation when it comes to the miniaturization effort. On Mar 22, 2:53 pm, John Adair <g...@enterpoint.co.uk> wrote: > If it's a PCI version of the PC104 stack usually the biggest > limitation it is the grant/request signals and only 4 available for > bus mastering negotiation that are usually the problem. For the money > they are spending they could have had a custom board, or boards, with > all the features smaller, lighter and cheaper and so on from us. > > It's not particularly well known but a major part of of our business > is either custom derivatives of development boards an/or full custom > boards. We actually design and build several times the amount of > development boards as customer boards and if it's based on FPGAs we > use and parts we can get quickly we can do boards on very short > timescales. Our record for a whole new board being designed, > manufactured, tested and delivered to the customer is 18 days and > that's not a particular unique event not that I would want to that > every week. > > John Adair > Enterpoint Ltd. > > On 22 Mar, 14:59, jleslie48 <j...@jonathanleslie.com> wrote: > > > On Mar 22, 10:23 am, Brian Drummond <brian_drumm...@btconnect.com> > > wrote: > > > > On Sat, 21 Mar 2009 19:19:09 -0700 (PDT), jleslie48 <j...@jonathanleslie.com> > > > wrote: >Article: 139182
djj08230 <djj08230@gmail.com> wrote: > I know from experience that these man-days thing is not a reliable > unit. Sometimes we are talking about different men, sometimes > different days. ;) There is a whole book, "Mythical Man-Month" about that. Specifically about software engineering, though now probably could be extended to hardware, too. -- glenArticle: 139183
On Mar 22, 3:07 pm, djj08230 <djj08...@gmail.com> wrote: > On Mar 22, 7:55 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > It took me 8 man days to program the entire solution to to > > our product's deficiencies on my Virtex-II Pro, a day to move the > > code into the coolrunner and on Friday at 1:00pm I fell into the tiger > > trap on the size problems on the coolrunner. Here it is 2 days later > > (10 man days ok so I've been working on the weekend) and Its beginning > > to look like I've got a workaround. > > > I don't see another solution having a faster development time than 2 > > weeks. > > > Shoot, it took the original boys 3 months just to pick out the > > coolrunner... and for a nickel I'd give them all an atomic wedgie for > > being so bone ass short sighted... > > I know from experience that these man-days thing is not a reliable > unit. Sometimes we are talking about different men, sometimes > different days. ;) > > Good luck > > Josep Duran quite true. I've had I guy working on some message passing stuff for 2 months now, something I thought would of been a weeks project at most. Meantime, I got put on this project on March 1st, my PM has given me to May 1st to get a programming solution to the missing signal. You can imagine his surprise when on March 18, I showed him his missing signal generated by the Virtex-IIP. Now I just have to get it to fit into the box.Article: 139184
On Mar 22, 3:23 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > djj08230 <djj08...@gmail.com> wrote: > > I know from experience that these man-days thing is not a reliable > > unit. Sometimes we are talking about different men, sometimes > > different days. ;) > > There is a whole book, "Mythical Man-Month" about that. > Specifically about software engineering, though now probably > could be extended to hardware, too. > > -- glen LOL. I bought for my PM a pair of 10-sided dice. I marked one of the die red. when he wants to know how long something is going to take me I told him to roll the dice. the red one is the tens column and the white one is the ones. I swear its the truth: http://cgi.ebay.com/Lot-of-20-white-odd-size-10-sided-game-dice-NEW_W0QQitemZ310127393388QQihZ021QQcategoryZ7317QQssPageNameZWDVWQQrdZ1QQcmdZViewItemArticle: 139185
PC104 has something of an organic growth with the initial 8 bit ISA based connect having a 16 bit extension. That's the connector with the funny layout. The PCI is located at the opposite end and is a a uniform 30x4 connector on 2mm pitch. There are now also PCIE extensions of the standard. HB2 supports both ISA and PCI connections. HB1 only supports PCI. We have another product CR1 which supports only the ISA connector. The PCI is basically the same as what you get on PC motherboards except rather than having individual connectors the cards stack into one another. John Adair Enterpoint Ltd. On 22 Mar, 19:15, jleslie48 <j...@jonathanleslie.com> wrote: > John, > > Oh don't worry, you've got me sold. =A0You'll be getting a call from me > on Monday morning. =A0 I wasn't on the project when they first designed > it about a year ago, I was only put on it starting March 1st 2009 =A0to > bail them out. =A0I remember when I first heard they bought a $100,000 > development suite I jokingly asked did it come packaged in a Porsche > 928... =A0 I can't believe what they have spent on this project. > > Anyway the PC104 is the stack version (the squares, the cards in the > stack look like the hollybush2:http://www.enterpoint.co.uk/oem_industrial= /hollybush2.html > I really don't know what the PCI means. =A0I thought it meant "card slot > for a PC" but I'm not sure. > Again I'm just going by what I heard the other guys talking about. > They told me to stay away from the PC104 stack. fine by me. > > Assuming all goes well I'm gonna end up needing about a 10 of the > patch job drigmorn/craignell/raggedstone1 solutions for =A0for this run, > and we are gearing up for a real production run after that. =A0We are > eventually going to need to minaturize, but I keep reminding the PM to > get it to at least work ANY way first. =A0I will definitely be thinking > of this conversation when it comes to the miniaturization effort. > > On Mar 22, 2:53 pm, John Adair <g...@enterpoint.co.uk> wrote: > > > > > If it's a PCI version of the PC104 stack usually the biggest > > limitation it is the grant/request signals and only 4 available for > > bus mastering negotiation that are usually the problem. For the money > > they are spending they could have had a custom board, or boards, with > > all the features smaller, lighter and cheaper and so on from us. > > > It's not particularly well known but a major part of of our business > > is either custom derivatives of development boards an/or full custom > > boards. We actually design and build several times the amount of > > development boards as customer boards and if it's based on FPGAs we > > use and parts we can get quickly we can do boards on very short > > timescales. Our record for a whole new board being designed, > > manufactured, tested and delivered to the customer is 18 days and > > that's not a particular unique event not that I would want to that > > every week. > > > John Adair > > Enterpoint Ltd. > > > On 22 Mar, 14:59, jleslie48 <j...@jonathanleslie.com> wrote: > > > > On Mar 22, 10:23 am, Brian Drummond <brian_drumm...@btconnect.com> > > > wrote: > > > > > On Sat, 21 Mar 2009 19:19:09 -0700 (PDT), jleslie48 <j...@jonathanl= eslie.com> > > > > wrote:- Hide quoted text - > > - Show quoted text -Article: 139186
On Sun, 22 Mar 2009 12:30:46 -0700 (PDT), jleslie48 wrote: >LOL. I bought for my PM a pair of 10-sided dice. I marked one of the >die red. when he wants to know how long something is going to take me >I told him to roll the dice. the red one is the tens column and the >white one is the ones. But don't you see... your _whole_team_ is playing Russian roulette with the project! Because you're so unfamiliar with the way FPGA designs get done, the whole thing becomes a research exercise for you as you learn the background. That learning is a great thing to do, but makes it impossible to estimate project schedules. Way back when you first approached comp.arch.fpga, several of us urged you to get (a) some formal training, (b) some paid help. Unless you work for nothing, the amount of salaried time you've burned up on this could have bought you, several times over, a good training class for yourself and a couple of weeks of a first-rate contractor's time to kick-start the details of your project(s). It's abundantly obvious that you have ample talent and enthusiasm but nowhere near enough knowledge. I've seen many not-invented-here projects in my time, and have been guilty of a good few of them myself, but I don't recall ever seeing such a spectacular waste of time and resources as seems to be going on in what you're doing. Good luck... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 139187
On Sun, 22 Mar 2009 05:56:07 -0700 (PDT), Guy_FPGA <guybye@hotmail.com> wrote: >Hello all, > >I am facing a weired problem with my stratix 3 device. >There is a controller on an external board that apply writes data to >my altera. For example it applys re_, we_, and one signlas of '1'. >this '1' turns into two signals of '1' on the pcb (short-circuited). >these two signals are then connected to two input pins on the startix >3 device. When I look on these signals from the signal - tap, these >signals arent identical which means that i have a cross-talk issue >inside the altera. More likely a synchronisation problem. If the input signal fails to meet setup/hold on the device inputs, you can expect the two linked inputs to show different values sometimes. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 139188
On Mar 22, 6:31 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sun, 22 Mar 2009 12:30:46 -0700 (PDT), jleslie48 wrote: > >LOL. I bought for my PM a pair of 10-sided dice. I marked one of the > >die red. when he wants to know how long something is going to take me > >I told him to roll the dice. the red one is the tens column and the > >white one is the ones. > > But don't you see... your _whole_team_ is playing Russian roulette > with the project! Because you're so unfamiliar with the way FPGA > designs get done, the whole thing becomes a research exercise for > you as you learn the background. That learning is a great thing > to do, but makes it impossible to estimate project schedules. > > Way back when you first approached comp.arch.fpga, several of us > urged you to get (a) some formal training, (b) some paid help. > Unless you work for nothing, the amount of salaried time you've > burned up on this could have bought you, several times over, > a good training class for yourself and a couple of weeks of a > first-rate contractor's time to kick-start the details of your > project(s). It's abundantly obvious that you have ample > talent and enthusiasm but nowhere near enough knowledge. > > I've seen many not-invented-here projects in my time, and have > been guilty of a good few of them myself, but I don't recall > ever seeing such a spectacular waste of time and resources as > seems to be going on in what you're doing. > > Good luck... > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. I hear what you are saying and I am steering my boss in that direction. I'm actually interviewing several candidates this up- coming week. Hopefully I'll see some talent. We are actually looking to hire full time people, as many as 5. That's not bad in this economy and especially as we are only a company of 50. I was at one point half a heartbeat away from spending a week with a professional in MD; but the PM put that on hold for at least the next 3-6 months. Meantime I don't think I'm really that far off on this one. Only 500 FF''s/macrocells away... Actually the first one is not that far off from done either. When it picks up again in 3-6 months I actually get a real schedule, 18 months, so I can actually plan for some training. I'm also light years ahead of the other 4 guys that HAVE tried to do fpga/vhdl in the company. All of them have tried and failed; and that is with going to classes and calling in hired guns.Article: 139189
"Andrew Holme" <ah@nospam.co.uk> wrote in message news:Kmrxl.223082$Dz4.54592@newsfe20.ams2... > Hi, I'm using the Spartan 3 XC3S400-TQ144. Does this device have internal > 100-ohm termination for LVDS input pairs, or must I use an external > 100-ohm resistor? When I designed my board, I assumed internal > termination would be enabled automatically by instantiation of the > IBUFGDS; but looking at my signal levels, although my board is working, I > would say there is no termination. The only statement I can find in the > datasheet is note 5 hidden away below table 37, which I think I can be > forgiven for overlooking. I only have two input pairs, and it's a > prototype board, so I can just solder 0201 resistors between the pins; but > maybe someone here knows better ... > > TIA > Spartan 3 family does not have the true "differential termination" (DIFF_TERM) capability, but Spartan 3A does. In Spartan 3A, you still have to have the "DIFF_TERM = yes" contraint in the constaint file in order to enable this differential termination. Spartan 3 family does have pseudo differential termination by using digitally-controlled impedance (DCI), but you have to have the Rref resistors (on the Vrp and Vrn pins) stuffed in order to use this feature. However, I would not use this feature without also using the "DCI FREEZE" option because of the amplitude jitter that DCI causes by its constant adjustment of this impedance. DCI can also generate significant amounts of heating if you use a bunch of it. 0201's are fun to work with. Enjoy. Bob -- == All google group posts are automatically deleted due to spam ==Article: 139190
For my hobby work, I am looking for a low-cost development kit to develope a simple embedded system. This system will measure the temperature and heart beat rate, compare them with a predefined table which implements some health-care knowledge, then provide some useful information. This development kit should be low-cost, support C programming, debugging, better with JTAG or other on-site debugging. It should support at least one type of popular microprocessors, or a mainstream FPGA, and easy to use. Could anybody recommend me some? Thank you in advance. JohnsonArticle: 139191
On Mar 22, 12:14=A0pm, "kadhiem_ayob" <kadhiem_a...@yahoo.co.uk> wrote: > I am sure either traverses all states except its lock state. > xor will lock if the value becomes all zeros. Thats why I reset it to > non-zero at power up. > xnor doesn't need reset(in fpgas) as it can start in all zeros (assuming > all ones is not expected at power up). > > kadhiem Hi kadhiem, Do you know why some length random number generator uses last 2 data while others may use 3 or 4 data at different positions. I am really very interested in the generator theory. References in the AP written by Peter are very old and cannot be found in internet. WengArticle: 139192
Hi Wang, I wouldn't dare (at my age) to get absorbed into that algebra of feedback shift pipes and polynomials. I believe there is plenty around(even wiki got interesting stuff). I rather get things ready for me to use and let the young research into the underlying mess. kadhiemArticle: 139193
jleslie48 <jon@jonathanleslie.com> writes:
> I'm working with a new chipset and I've got to add some functionality
> to this coolrunner cpld xpla3 but I can't figure out its reports after
> I get through with the synth--translate--fit. A report comes out in
> html that looks like this:
Having looked over the whole thread, it's probably a bit late, but if
you are going to target an FPGA rather than a CPLD (in which case you
problem goes away :), you can use this tool to see where your
resources are going:
http://www.conekt.net/fpgaoptim.html
Disclaimer: I wrote it :) Mail me if you want a download link...
It was written for precisely the issue you have ("my code is too big -
what's using all the resources?"). You can sort the design on various
types of design elements (eg LUTs, FFs, multipliers, RAMs) by clicking
the column headings and then you can see where in the hierarchy the
FFs are "coming from".
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
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Article: 139194Hopefully I'm not throwing a big spanner in the works but.. Have you considered using an ALTERA MAXII. They market it as a CPLD but is is really a very small (but bigger that your coolrunner) FPGA. They only need 3v3 and while not a drop in replacement it will replace your coolrunner very easily. All FPGAs need several supplies. Some time ago I designed a 40 pin DIL which just has a MAXII on it so if you only need 36 IO it would only take a short time to install the ALTERA dev tools and see if it fits. I have several bare PCBs so I could easily sort you something out. ColinArticle: 139195
On Mar 23, 12:43=A0pm, "colin_toog...@yahoo.com" <colin_toog...@yahoo.com> wrote: > Hopefully I'm not throwing a big spanner in the works but.. > > Have you considered using an ALTERA MAXII. They market it as a CPLD > but is is really a very small (but bigger that your coolrunner) FPGA. > > They only need 3v3 and while not a drop in replacement it will replace > your coolrunner very easily. All FPGAs need several supplies. > > Some time ago I designed a 40 pin DIL which just has a MAXII on it so > if you only need 36 IO it would only take a short time to install the > ALTERA dev tools and see if it fits. I have several bare PCBs so I > could easily sort you something out. > > Colin Lattice XP FPGA's are TRUE single supply FPGA's also much better price/performance ratio then maxII or machXO AnttiArticle: 139196
Hi guys, Just wondering if anyone has any tips or tricks for the problem of having global variables/constants etc that are usable in mixed-language (VHDL, Verilog) projects? I guess it depends on the tool - ultimately Quartus? I'm mainly looking for way way to control compile-time build options. For VHDL I tend to use a global packge with boolean constants; for Verilog I'd use an include file with the 'define/'ifdef directive pair... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 139197
On Mar 23, 5:19=A0am, "kadhiem_ayob" <kadhiem_a...@yahoo.co.uk> wrote: > Hi Wang, > > I wouldn't dare (at my age) to get absorbed into that algebra of feedback > shift pipes and polynomials. I believe there is plenty around(even wiki g= ot > interesting stuff). I rather get things ready for me to use and let the > young research into the underlying mess. > > kadhiem I was under the impression that all LFSR's used an even number of terms. The table of feedback terms in the appnote is only one possible set of polynomials for maximal LFSR's of each length, however these represent the ones with the least number of terms for that length of LFSR. At one time I had written a C program to search for maximal LFSR feedback terms. Then I found the Xilinx appnote. I think the main requirement for a maximal LFSR is that the polynomial is relatively prime with respect to 2^N - 1. The number of states for a given set of feedback terms does not depend on use of XOR vs XNOR. You can easily prove that these two are equivalent by simply inverting the logic: if Y =3D A XOR B then not Y =3D not A XOR not B Regards, GaborArticle: 139198
On Mar 23, 9:15=A0am, gabor <ga...@alacron.com> wrote: > On Mar 23, 5:19=A0am, "kadhiem_ayob" <kadhiem_a...@yahoo.co.uk> wrote: > > > Hi Wang, > > > I wouldn't dare (at my age) to get absorbed into that algebra of feedba= ck > > shift pipes and polynomials. I believe there is plenty around(even wiki= got > > interesting stuff). I rather get things ready for me to use and let the > > young research into the underlying mess. > > > kadhiem > > I was under the impression that all LFSR's used an even > number of terms. =A0The table of feedback terms in the appnote > is only one possible set of polynomials for maximal LFSR's of > each length, however these represent the ones with the least > number of terms for that length of LFSR. =A0At one time I had > written a C program to search for maximal LFSR feedback > terms. =A0Then I found the Xilinx appnote. =A0I think the main > requirement for a maximal LFSR is that the polynomial is > relatively prime with respect to 2^N - 1. =A0The number of > states for a given set of feedback terms does not depend > on use of XOR vs XNOR. =A0You can easily prove that these > two are equivalent by simply inverting the logic: > > if Y =3D A XOR B > then not Y =3D not A XOR not B > > Regards, > Gabor Oops, posted too fast. I meant: if Y =3D A XOR B then not Y =3D not A XNOR not BArticle: 139199
Antti and others, This may be covered by another thread, in which case I would appreciate a link. What are your thoughts on the Silicon Blue devices? How is it to use their tools? Sephen
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