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On Tue, 02 Nov 2010 09:02:40 +0000, Richard <Richard@yahoo.com> wrote: >> Combinational net names can get sliced, diced, absorbed and further >> processed so it might be difficult to find out what they've become, if >> indeed they've survived at all. So my suggestion would be to set your >> constraints based on clock period and chip IOs instead of trying to >> set delays on nets. >> One helpful note might be that register names are almost always >> preserved so you might be able to refer to ip_we_cs etc more easily. > >Thanks for all your feedback, is there any way that with some kind of >options I can make sure that the name of the nets is preserved? The >problem is that these nets interact with a third party IP, and the >constraints on these nets are apparantly mandotory, so in other words >I have to contrain these particular signals to make the whole design >working. There are various attributes you can attach to nets in VHDL, to preserve them. If life were simple, they would actually preserve the net names you need. Unfortunately there is a mysterious set of rules determining when the tools will preserve a net, and when they will simply ignore the attribute (and maybe print a message in the synthesis report). Some of the useful ones are "keep", "syn_keep", "preserve_signal" (in some synthesis tools, not sure about XST), "equivalent_register_removal=no", and "don't_optimise". For example, if you use "keep" on a signal that is being removed by equivalent register removal, the signal will be deleted anyway, and the warning buried in a megabyte of synthesis report. Some apply during synthesis, but there are further optimisation stages in Map, and these may need different constraints. See the Constraints Guide for more information, and try searching the answers database. http://www.xilinx.com/support/answers/25016.htm shows a case where a specific combination of three constraints are required on the same signal... attribute syn_keep: boolean; attribute keep: boolean; attribute preserve_signal: boolean; Also, from AR#23990 http://www.xilinx.com/support/answers/23990.htm # The KEEP attribute does not block trimming - A common misconception is that KEEP properties can be used to block signal trimming. The KEEP property can be used to prevent a signal from being absorbed into a component, but it has no effect on trimming behavior. The correct attribute to block trimming is "S" (AKA Save, SAVESIG, NOCLIP). # Beginning with ISE version 10.1, the S attribute not only blocks trimming, but also constant optimization. The S property can be applied directly to a logical block, or to a net attached to a logical block to prevent both constant optimization or trimming. Ed: How about a white paper entitled "Help: my signal disappeared!" or "You are lost in a maze of optimization constraints; all different" with a comprehensive list of such constraints and their interactions? - BrianArticle: 149526
On 2 Lis, 11:53, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > =A0When I program fpga via USB Blaster for > > a one second led User is on but after that it returns to the factory > > mode and led factory is on. I don't know how to program this board > > with simple logic program. Can anyone explain me what am I doing wrong? > > From memory one of the FPGA pins is 'reset_n' (or reset) into the CPLD th= at controls > configuration. > > If this isn't held at the right polarity the image will be immediately re= set. > > Have a look at the example designs provided on the Altera web site. > > Nial. On the Altera Web are only the NIOS examples. They don't say how program FPGA like CPLD. Still I don't see this:(Article: 149527
On Nov 2, 7:03=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Tue, 02 Nov 2010 09:02:40 +0000, Richard <Rich...@yahoo.com> wrote: > >> Combinational net names can get sliced, diced, absorbed =A0and further > >> processed so it might be difficult to find out what they've become, if > >> indeed they've survived at all. So my suggestion would be to set your > >> constraints based on clock period and chip IOs instead of trying to > >> set delays on nets. > >> One helpful note might be that register names are almost always > >> preserved so you might be able to refer to ip_we_cs etc more easily. > > >Thanks for all your feedback, is there any way that with some kind of > >options I can make sure that the name of the nets is preserved? The > >problem is that these nets interact with a third party IP, and the > >constraints on these nets are apparantly mandotory, so in other words > >I have to contrain these particular signals to make the whole design > >working. > > There are various attributes you can attach to nets in VHDL, to preserve = them. > If life were simple, they would actually preserve the net names you need. > > Unfortunately there is a mysterious set of rules determining when the too= ls will > preserve a net, and when they will simply ignore the attribute (and maybe= print > a message in the synthesis report). > > Some of the useful ones are "keep", "syn_keep", "preserve_signal" (in som= e > synthesis tools, not sure about XST), "equivalent_register_removal=3Dno",= and > "don't_optimise". > > For example, if you use "keep" on a signal that is being removed by equiv= alent > register removal, the signal will be deleted anyway, and the warning buri= ed in a > megabyte of synthesis report. > > Some apply during synthesis, but there are further optimisation stages in= Map, > and these may need different constraints. > > See the Constraints Guide for more information, and try searching the ans= wers > database. > > http://www.xilinx.com/support/answers/25016.htm > shows a case where a specific combination of three constraints are requir= ed on > the same signal... > > attribute syn_keep: boolean; > attribute keep: boolean; > attribute preserve_signal: boolean; > > Also, from AR#23990http://www.xilinx.com/support/answers/23990.htm > # The KEEP attribute does not block trimming - A common misconception is = that > KEEP properties can be used to block signal trimming. The KEEP property c= an be > used to prevent a signal from being absorbed into a component, but it has= no > effect on trimming behavior. The correct attribute to block trimming is "= S" (AKA > Save, SAVESIG, NOCLIP). > # Beginning with ISE version 10.1, the S attribute not only blocks trimmi= ng, but > also constant optimization. The S property can be applied directly to a l= ogical > block, or to a net attached to a logical block to prevent both constant > optimization or trimming. > > Ed: How about a white paper entitled "Help: my signal disappeared!" or "Y= ou are > lost in a maze of optimization constraints; all different" with a compreh= ensive > list of such constraints and their interactions? > > - Brian Another point on the final net name. Some of it depends on the settings for synthesis. "keep hierarchy" and "hierarchy separator" options both affect the final net names. Also you can use wildcard characters in your .ucf file. So for example if you know the hierarchy but not the hierarchy separator character you could change your lines to: Net "testip?ip_datain<*>" MAXDELAY =3D 2 ns; Net "testip?ip_ce" MAXDELAY =3D 2 ns; Net "testip?ip_we" MAXDELAY =3D 2 ns; or if you only know part of the hierarchy but not the top level instantiation you might have: Net "*/testip/ip_datain<*>" MAXDELAY =3D 2 ns; Net "*/testip/ip_ce" MAXDELAY =3D 2 ns; Net "*/testip/ip_we" MAXDELAY =3D 2 ns; For any particular build, you could remove your constraints to get an error-free build and then search through the nets in the FPGA editor to see where they went. Regards, GaborArticle: 149528
> On the Altera Web are only the NIOS examples. They don't say how > program FPGA like CPLD. Still I don't see this:( The CPLD is a separate IC on the board that controls programming the FPGA, you have to let this know the FPGA is programmed properly. There is an output from the FPGA to this device, actually I think it's called 'reconfig_n', which lets the CPLD know the FPGA is programmed with a valid image. I'm not doing the donkey work for you, look at the board schematics or an example FPGA design to see what I'm talking about. Nial.Article: 149529
hi all
i am new with EDK, i am working with microblaze and have to run on my own
board XC3S1000-fg456 -4
i write a simple code to blink 2 leds
code here:
#include "xparameters.h"
#include "xgpio.h"
main()
{
XGpio led;
unsigned int i,j,k;
XGpio_Initialize(&led,XPAR_LEDS_DEVICE_ID);
XGpio_SetDataDirection(&led, 1, 0x0);
while(1)
{
XGpio_DiscreteWrite(&led, 1, 0x3);
for(k=0;k<60000;k++);
XGpio_DiscreteWrite(&led, 1, 0x0);
for(k=0;k<60000;k++);
} // while(1)
}//main()
there are the following error, plz help me
/usr/bin/bash: cd: /cygdrive/e/technical: No such file or directory
make: *** No rule to make target `/cygdrive/e/technical', needed by
`TestApp/executable.elf'. Stop.
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 149530On 11/02/2010 10:00 AM, Nial Stewart wrote: >> On the Altera Web are only the NIOS examples. They don't say how >> program FPGA like CPLD. Still I don't see this:( > > > The CPLD is a separate IC on the board that controls programming the FPGA, > you have to let this know the FPGA is programmed properly. > > There is an output from the FPGA to this device, actually I think it's called > 'reconfig_n', which lets the CPLD know the FPGA is programmed with a valid > image. > > I'm not doing the donkey work for you, look at the board schematics or > an example FPGA design to see what I'm talking about. > A good hint, though, is to make sure you know what unassigned pins are set to. I believe the default in current versions of Quartus II is "as output driving ground", which is probably a bad choice. I suggest "as input with weak pullup" instead. -hpaArticle: 149531
On 2 Lis, 19:15, "H. Peter Anvin" <h...@zytor.com> wrote: > A good hint, though, is to make sure you know what unassigned pins are > set to. =A0I believe the default in current versions of Quartus II is "as > output driving ground", which is probably a bad choice. =A0I suggest "as > input with weak pullup" instead. Yes this is it. Now FPGA don't ground unassinged pins and in this way configure CPLD MAX configuration circuit. Thank You so much.Article: 149532
I have a question regarding the minimum clock rates allowed on LVDS- based LCD display panels. Perhaps someone in the group has some expertise here. I have HD data coming in at 30 frames per second. I have no place to store a full frame. The HD display panel requires a minimum clock rate of at least 50 MHz (which, according to the display data sheet, equates to about 50 frames per second). I'd like to drive it at about 36 MHz. Even if I had a frame buffer, the I/Os are not fast enough to drive the display at more than about 300 megabits per second (the LVDS is emulated with external resistors). Do you know if the minimum specified clock rate is the absolute minimum guaranteed clock frequency to guarantee that the display operates, or is it the minimum clock frequency to guarantee the display's specified response time? Will the display actually operate with a lower clock frequency. I know that I should ask this of the vendor, but unfortunately, there is little support for this display. I have tested another vendor's LCD display at well below the data sheet specified frequency and it operated just fine. Thanks in advance for any advice you might have.Article: 149533
Hi, all, Thanks for the help, unfortunately I'm not having any luck figuring out where the failing paths are. In the meantime, I might have found a way around my problem. I had originally set up my data stream to be asynchronous for speed issues, but I had no knowledge of using asynchronous FIFOs to bridge the two clock domains, so I was running into issues with the readout occurring while the data bits were changing, creating a jibberish output. So, I went to a synchronous system. I need a high clock to 'probe' the data stream with (to keep my time resolution up), which is what brought me to this 400MHz business. If I can figure out how to set up one of these asynchronous FIFOs, however, I can avoid these DCM issues all together, and this way I wont be on the border of my FPGA's capabilities. Cheers, Sean. On Nov 2, 1:51=A0am, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > Sean > > Looing at the V4 datasheet the max freq of the CLK2X is 400MHz, so you > might have a problem with timing. Maybe if you had a better speed grade > device things might be a bit easier. But all you can do is look at the > failing paths and see if you can get them to time. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 149534
On 10/25/2010 05:24 AM, cdb wrote: > Hi everybody, > I'm designing a VHDL testbench for a VHDL module. > > I have to generate values to be written into a 32 bit register of my > module. > I decided tu use integer variables to compose my data and than convert them > to std_logic_vector to perform the write operation on the module. > > The issue is that I discovered that VHDL > integer range is from -2147483647 to 2147483647, > that is to say 0x80000000 integer is not supported. This is, indeed, an invalid positive integer in a signed 32-bit field. The correct form would be -2147483648 (decimal). I'm not exactly sure how to write a negative value in hex notation. If the value doesn't need to be signed, then make it unsigned, and the assignment should work properly. JonArticle: 149535
On Nov 2, 10:57=A0pm, Prevailing over Technology <steve.kn...@prevailing- technology.com> wrote: > I have a question regarding the minimum clock rates allowed on LVDS- > based LCD display panels. =A0Perhaps someone in the group has some > expertise here. > > I have HD data coming in at 30 frames per second. =A0I have no place to > store a full frame. =A0The HD display panel requires a minimum clock > rate of at least 50 MHz (which, according to the display data sheet, > equates to about 50 frames per second). =A0I'd like to drive it at about > 36 MHz. =A0Even if I had a frame buffer, the I/Os are not fast enough to > drive the display at more than about 300 megabits per second (the LVDS > is emulated with external resistors). > > Do you know if the minimum specified clock rate is the absolute > minimum guaranteed clock frequency to guarantee that the display > operates, or is it the minimum clock frequency to guarantee the > display's specified response time? =A0Will the display actually operate > with a lower clock frequency. =A0I know that I should ask this of the > vendor, but unfortunately, there is little support for this display. > > I have tested another vendor's LCD display at well below the data > sheet specified frequency and it operated just fine. > > Thanks in advance for any advice you might have. Good question, one I have asked some years back myself. I wish I had got the answer. The minimum clock frequency spec began to appear perhaps 5 years ago or less. I don't remember why now but I think TFT panels which won't work below that frequency (my level of certainty is pretty low on that, however). I have had displays which will operate at much much lower frequencies, however below a certain one their contrast etc. parameters won't meet their spec (the gates of the TFT can only hold charge for a limited amount of time, if you have seen how a display fades into rainbow colours a second or so after losing its clock etc. signals you'll know what I mean). I suppose the bottom line is "check that display you will use"... Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/Article: 149536
"David Brown" <david@westcontrol.removethisbit.com> wrote in message news:poednSAUkb9tRlLRnZ2dnUVZ7v6dnZ2d@lyse.net... > If you get an appropriate DAC (such as the AD5791) with an SPI interface, > you could connect it up to an FTDI FT4232H module. That would let you > fairly easily run a high speed SPI bus directly from a PC. If I remember > the figures correctly, the FT4232H can run an SPI bus at 30 MHz. You get > relatively long latencies using USB and a PC - it's not much good if you > have to mix reading and writing. But you can write out a continuous > stream at full speed. Thanks. It looks like an interesting and useful part. I will probably use it in a future project. For the test system I'm working on I don't think I really need arbitrary waveforms, so I'll just end up coding everything I need (sweeps, steps, noise, spot frequencies, etc) into a small FPGA board. I've probably got five different Spartan 3 boards in my basement, so I'm sure one will work nicely. Thanks everybody for your suggestions on this project. PeteArticle: 149537
On Tue, 2 Nov 2010 14:56:04 -0700 (PDT), Griffin <captain.griffin@gmail.com> wrote: >Hi, all, > >Thanks for the help, unfortunately I'm not having any luck figuring >out where the failing paths are. Timing Analysis should have listed them in its report file, with either .twx or .twr extension. - BrianArticle: 149538
> Yes this is it. Now FPGA don't ground unassinged pins and in this way > configure CPLD MAX configuration circuit. > Thank You so much. OK, but if that is the fix you should check and drive that pin inactive instead of allowing it to float (it might be tied inactive on the board, I can't remember). Nial.Article: 149539
I'm looking for a good FPGA dev board. My budget is not low, but since I'm a grad student it's certainly not high. The primary requirement is that I need gates, and lots (>1M) of them. I've had a good experience with an XC3S500 board (Digilent) but my research is pushing me further. In my world gates for dedicated resources don't count (unless they can be commandeered for my own use) because I need to create machine descriptions that are as "portable" as possible. Any suggestions?Article: 149540
On Wed, 3 Nov 2010 06:10:44 -0700 (PDT), gordon sumner <olgordy@gmail.com> wrote: >I'm looking for a good FPGA dev board. My budget is not low, but >since I'm a grad student it's certainly not high. The primary >requirement is that I need gates, and lots (>1M) of them. I've had a >good experience with an XC3S500 board (Digilent) but my research is >pushing me further. In my world gates for dedicated resources don't >count (unless they can be commandeered for my own use) because I need >to create machine descriptions that are as "portable" as possible. >Any suggestions? Actel has a ProAsic3 dev board with a 1.5M-gate device on it, which may be interesting because it's a fine-grained architecture with few dedicated structures apart from RAM blocks and PLLs. But at a glance I thought the board was quite expensive for what's on it. You can upgrade to a 3M-gate device on the same board, which is good; but there's almost nothing by way of peripherals, which means quite a lot of do-it-yourself work. If you're going all-out for portability, it might not be a bad choice. Certainly an alternative to the usual big-name LUT-based architectures. -- Jonathan BromleyArticle: 149541
We are awarding a SP601 Spartan-6 board to the winner of our You Write the Caption contest. To enter, visit http://cde.cerosmedia.com/1N4cc1a89f283a0012.cde/page/66 (this is a flash page). Here is a link to the latest issue if you prefer PDF (see page 66): http://www.xilinx.com/publications/xcellonline/index.htm. You have to be from North America (excluding Quebec) to officially participate in the contest. Mike Santarini, publisher/editor XcellArticle: 149542
ARM University relations is working on an easily available encrypted FPGA netlist for academic use. I don't know the details but I have asked my colleage about it. In the meantime ARM has a university program that you can contact at www.arm.com/support/university or university@arm.com regards, --steve "Oliver Mattos" <omattos@gmail.com> wrote in message news:5d26e81a-576a-4ff5-8e2f-490239880f46@f33g2000yqh.googlegroups.com... > > There is talk here of the Cortex M1/3 processor here - is that the > kind of thing you can just download and use in a softcore as a > student, or do you have to pay a multi-million dollar license to get > hold of it? > > Thanks > OliverArticle: 149543
On Nov 3, 6:10=A0am, gordon sumner <olgo...@gmail.com> wrote: > I'm looking for a good FPGA dev board. =A0My budget is not low, but > since I'm a grad student it's certainly not high. =A0The primary > requirement is that I need gates, and lots (>1M) of them. =A0I've had a > good experience with an XC3S500 board (Digilent) but my research is > pushing me further. =A0In my world gates for dedicated resources don't > count (unless they can be commandeered for my own use) because I need > to create machine descriptions that are as "portable" as possible. > Any suggestions? If I understand what you are looking for (A whole mess of gates to verify some RTL), I would suggest getting a 1 or 2 generation old board, like a Virtex-4 or a Stratix-2. You are not going to be able to clock these as fast as current boards, but you will get a lot more gates for the money. These show up on eBay fairly often, or you can get them direct some times. Be sure to ask about the student discount if you're buying direct (you may have to get a faculty member to register with the university program.) $.02, RKArticle: 149544
On Nov 3, 1:08=A0pm, Mike Santarini <mike.santar...@gmail.com> wrote: > We are awarding a SP601 Spartan-6 board to the winner of our You Write > the Caption contest. =A0To enter, visithttp://cde.cerosmedia.com/1N4cc1a8= 9f283a0012.cde/page/66 > (this is a flash page). Here is a link to the latest issue if you > prefer PDF (see page 66):http://www.xilinx.com/publications/xcellonline/i= ndex.htm. > > You have to be from North America (excluding Quebec) to officially > participate in the contest. > > Mike Santarini, publisher/editor Xcell O.K. I have to ask. What did Quebec do wrong?Article: 149545
On Nov 3, 1:22=A0pm, Gabor <ga...@alacron.com> wrote: > On Nov 3, 1:08=A0pm, Mike Santarini <mike.santar...@gmail.com> wrote: > > > We are awarding a SP601 Spartan-6 board to the winner of our You Write > > the Caption contest. =A0To enter, visithttp://cde.cerosmedia.com/1N4cc1= a89f283a0012.cde/page/66 > > (this is a flash page). Here is a link to the latest issue if you > > prefer PDF (see page 66):http://www.xilinx.com/publications/xcellonline= /index.htm. > > > You have to be from North America (excluding Quebec) to officially > > participate in the contest. > > > Mike Santarini, publisher/editor Xcell > > O.K. =A0I have to ask. =A0What did Quebec do wrong? Evidently they made some onerous laws: http://contests.about.com/od/sweepstakes101/f/VoidinQuebec.htm Ed McGettigan -- Xilinx Inc.Article: 149546
Does anybody have any information like "when" and "how much" about Achronix Speedster22i? Petter -- .sig removed by request.Article: 149547
Check out Xilinx' University program boards, most of which are from Digilent: http://www.xilinx.com/products/boards_kits/university/index.htm The Genesys and XUPV5 provide two Virtex-5 options with very good Academic pricing. You'll find Virtex-5 performance is much higher than the Spartan you've been using, as well as the 6-input LUT gives you more synthesized logic per cell than the 4-input LUT. Genesys $449 XC5VLX50T 28800 6-input LUTs/FFs XUPV5 $750 XC5VLX110T 69120 6-input LUTs/FFs BryanArticle: 149548
On Nov 3, 11:59=A0pm, Petter Gustad <newsmailco...@gustad.com> wrote: > Does anybody have any information like "when" and "how much" about > Achronix Speedster22i? > > Petter > -- > .sig removed by request. On article had a mention of fourth quarter 2011 and $400 for 1M LUTs. Ed McGettigan -- Xilinx Inc.Article: 149549
Hi, I have seen a demo of LAVA 10 (SVGA Controller based on FPGA) on youtube and I was wondering if there are some similar solutions like this? I've read about generating VGA but first time about SVGA. Any info about how fast processor I need to use that module? Thanks, Matti
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