Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 150925

Article: 150925
Subject: Re: timing issues at high speed
From: vasu <vasu.devunuri@gmail.com>
Date: Tue, 22 Feb 2011 01:56:18 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 22, 12:45=A0pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Tue, 22 Feb 2011 01:28:15 -0600, "salimbaba"
>
> <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
>
> >Thanks a lot Gabor for the help. I tried 4 stage S/R approach but still =
the
> >same problem. And there are no failing paths in my design, at least not
> >reported in the timing report. Any other suggestions ? And also, i read
> >this Cummings's paper on synchronous and asynchronous resets which state=
d
> >the same solution, but i am still facing the same problem. In need of
> >urgent help!
>
> I have several questions some of which may give you a clue (and
> hopefully not duplicative):
> * how many clocks do you have in the system? All of them constrained?
> Any of them coming from different sources (different oscillators,
> crystals, PHYs etc?)
> * did you check the "report unconstrained paths" option? did you read
> the resulting report?
> * do you have any latches (mainly combination feedback) in the design?
> * do you have any divided clocks in the design?
> * did you constrain all you IOs? did you check the datasheet/scope to
> verify that these timing values are correct?
> * do you have any multi-cycle constraints in your design? are you
> using the version of TRCE/PAR which has a bug with MC paths? (this is
> a trick question!)
> --
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Services
>
> http://www.dspia.com

I would like to a point here. Do you have any shift registers i.e. SRL
in your design? These create problems when there is a glitch on clock
signal.

Article: 150926
Subject: Re: lattice machXO2 VCCP pin
From: Antti <antti.lukats@googlemail.com>
Date: Tue, 22 Feb 2011 05:01:08 -0800 (PST)
Links: << >>  << T >>  << A >>
Super!

the datasheet already was up to date, but the pinout listing still included this pin, that is what caused confusion!

The XO2 demo board is already shipped to prepared for Embedded World show :)

Antti writing officially from the office

Article: 150927
Subject: Re: timing issues at high speed
From: "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com>
Date: Tue, 22 Feb 2011 07:51:24 -0600
Links: << >>  << T >>  << A >>

>
>I have several questions some of which may give you a clue (and
>hopefully not duplicative):
>* how many clocks do you have in the system? All of them constrained?

I have 4 clocks in my system and 2 of them are constrained i.e. i have
placed OFFSET IN constraints on them. The other 2 are not constrained as i
am using them to output data. So i have just given them PERIOD and
TIMESPEC.

>Any of them coming from different sources (different oscillators,
>crystals, PHYs etc?)

2 clocks are coming from 1 PHY and 2 are coming from 2nd PHY.

>* did you check the "report unconstrained paths" option? did you read
>the resulting report?

NO. I will check it now and see the report.

>* do you have any latches (mainly combination feedback) in the design?

No latches are there in the design.

>* do you have any divided clocks in the design?

I have 2 divided clocks. The divided clocks are also being used in the
design.

>* did you constrain all you IOs? did you check the datasheet/scope to
>verify that these timing values are correct?

If by constraining IOs you mean timegrouping thing, then yes.

>* do you have any multi-cycle constraints in your design? are you
>using the version of TRCE/PAR which has a bug with MC paths? (this is
>a trick question!)

No, i dont have any multi cycle constraints in my design.
Well i dont know which version of TRCE/PAR has the bug, i am using xilinx
ISE 12.1 .


thanks	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 150928
Subject: Re: timing issues at high speed
From: Gabor <gabor@alacron.com>
Date: Tue, 22 Feb 2011 06:07:34 -0800 (PST)
Links: << >>  << T >>  << A >>
On Tuesday, February 22, 2011 2:50:53 AM UTC-5, Thomas Heller wrote:
> Am 21.02.2011 21:34, schrieb Gabor:
> > The simplest way to work around this is to generate
> > a local reset signal for each state machine or
> > module that releases synchronously one or two cycles
> > after the release of the asynchronous reset and
> > use that signal as a synchronous reset term for
> > your state machines.  Xilinx usually recommends
> > a 4-stage shift register to create a reset from
> > the GSR release.  The actual number of stages
> > required to reset cleanly will depend on the
> > clock frequency and the size of the device,
> > where the larger devices can have more skew in
> > releasing GSR.  My designs typically have no
> > external reset signal and use the 4-stage S/R
> > approach to an internal reset.  I have had
> > very good results with this approach, because
> > the four stages give the tools ample opportunity
> > to replicate the final S/R stage(s) to help
> > meet timing.
> 
> Can you post some code (or pointers) demonstrating
> this reset signal generation?
> 
> Thanks,
> Thomas

Here's the Xilinx approach using instantiated
flip-flops with asynchronous preset (and implied
initialization to 1):

wire sys_clock, sys_reset;
wire [2:0] presys_rst;
// --------------------------------------------------------------------
// Instantiate flip-flops for internal reset signals
// These flip-flops come up preset (all ones) after configuration.
FDP sys_rst_ff[3:0]
(
  .D    ({presys_rst,1'b0}),  // form a shifter with 0 shifting in from right
  .Q    ({sys_reset,presys_rst}),
  .C    (sys_clock),
  .PRE  (1'b0)  // A preset term may be inserted here, otherwise release reset after config
);

And here's the equivalent Verilog:


wire sys_clock;
reg sys_reset = 1'b1;
reg [2:0] presys_rst = 3'b111;

always @ (posedge sys_clock)
 {sys_reset,presys_rst} <= {presys_rst,1'b0};

-- Gabor

Article: 150929
Subject: Re: timing issues at high speed
From: Gabor <gabor@alacron.com>
Date: Tue, 22 Feb 2011 06:12:46 -0800 (PST)
Links: << >>  << T >>  << A >>
On Tuesday, February 22, 2011 2:28:15 AM UTC-5, salimbaba wrote:

> Thanks a lot Gabor for the help. I tried 4 stage S/R approach but still the
> same problem. And there are no failing paths in my design, at least not
> reported in the timing report. Any other suggestions ? And also, i read
> this Cummings's paper on synchronous and asynchronous resets which stated
> the same solution, but i am still facing the same problem. In need of
> urgent help! 
> 
> Thanks

In that case I would look for other asynchronous inputs to
the state machines that are failing.  How do you know they
are failing to start up after reset and not some time later?
The most common reason for a state machine to go haywire
is that it has a state transition that depends on an
asynchronous input.  Note that since your design has
more than one clock, asynchronous means any input that
was not created on the same clock used by the state
machine.

-- Gabor

Article: 150930
Subject: Re: timing issues at high speed
From: GoogleGoonsAreClueless <d_s_klein@yahoo.com>
Date: Tue, 22 Feb 2011 08:57:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 22, 6:12=A0am, Gabor <ga...@alacron.com> wrote:
> On Tuesday, February 22, 2011 2:28:15 AM UTC-5, salimbaba wrote:
> > Thanks a lot Gabor for the help. I tried 4 stage S/R approach but still=
 the
> > same problem. And there are no failing paths in my design, at least not
> > reported in the timing report. Any other suggestions ? And also, i read
> > this Cummings's paper on synchronous and asynchronous resets which stat=
ed
> > the same solution, but i am still facing the same problem. In need of
> > urgent help!
>
> > Thanks
>
> In that case I would look for other asynchronous inputs to
> the state machines that are failing. =A0How do you know they
> are failing to start up after reset and not some time later?
> The most common reason for a state machine to go haywire
> is that it has a state transition that depends on an
> asynchronous input. =A0Note that since your design has
> more than one clock, asynchronous means any input that
> was not created on the same clock used by the state
> machine.
>
> -- Gabor

How many times are we going to have this discussion, and how many
times are people (like the OP) going to get burned when they don't
believe the following:

"The most common reason for a state machine to go haywire is that it
has a state transition that depends on an asynchronous input."

All inputs that are used in a 'conditional' in a state machine MUST be
synchronized to the state machines clock.

<http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/
1ea0ba1a1005287f/0e3c67b4b4163205>
<http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/
fa2dba1d2e86c730/17568f37ad2dde1b>

RK

Article: 150931
Subject: Re: timing issues at high speed
From: Muzaffer Kal <kal@dspia.com>
Date: Tue, 22 Feb 2011 09:23:04 -0800
Links: << >>  << T >>  << A >>
On Tue, 22 Feb 2011 07:51:24 -0600, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:

>
>>
>>I have several questions some of which may give you a clue (and
>>hopefully not duplicative):
>>* how many clocks do you have in the system? All of them constrained?
>
>I have 4 clocks in my system and 2 of them are constrained i.e. i have
>placed OFFSET IN constraints on them. The other 2 are not constrained as i
>am using them to output data. So i have just given them PERIOD and
>TIMESPEC.
>
OFFSET constraints are for data. For clocks you always need PERIOD
constraint without which your design is NOT constrained properly.

>>Any of them coming from different sources (different oscillators,
>>crystals, PHYs etc?)
>
>2 clocks are coming from 1 PHY and 2 are coming from 2nd PHY.

How do you transfer data between these domains? (I am assuming the
PHYs have different oscillators, is this the case?) This can be source
of many unexplained issues in your silicon testing.

>>* do you have any latches (mainly combination feedback) in the design?
>
>No latches are there in the design.

How do you know? Do you have a method of finding unintentional
latches, combinational feedback?

>
>>* do you have any divided clocks in the design?
>
>I have 2 divided clocks. The divided clocks are also being used in the
>design.
>
Are the PERIOD constraints for the divided clocks set properly? 

>>* did you constrain all you IOs? did you check the datasheet/scope to
>>verify that these timing values are correct?
>
>If by constraining IOs you mean timegrouping thing, then yes.

IOs are constrained by OFFSET constraints (ie relative delay of
signals with respect to a clock) and clocks are constrained by PERIOD
constraints. You need to make sure every signal which arrives at a CLK
pin of a register has a PERIOD constraint attached to it.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Article: 150932
Subject: Programming FPGAs with Quartus under Linux
From: aldorus <him@here.com>
Date: Wed, 23 Feb 2011 06:10:16 GMT
Links: << >>  << T >>  << A >>
Ok I had a 95108 cpld based board (xilinx) and host pc running webpack 
ise 9.1. I had no problems programming the board (parallel jtag) onces 
WinDriver was installed.

Now I have a Cyclone based board (altera) and host pc running quartus 
10.0. I want to know if I will encounter any problems programming the 
device under linux. This particular board uses a USB interface with the
controller on board - so I dont need a separate usb byteblaster.

So my question is basically
Has anyone had success programming fpga boards with quartus under linux?
Did you use the usb byteblaster or some such interface?
What did you do?

Thanks

Article: 150933
Subject: Re: timing issues at high speed
From: "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com>
Date: Wed, 23 Feb 2011 03:09:01 -0600
Links: << >>  << T >>  << A >>

>>
>> In that case I would look for other asynchronous inputs to
>> the state machines that are failing. =A0How do you know they
>> are failing to start up after reset and not some time later?
>> The most common reason for a state machine to go haywire
>> is that it has a state transition that depends on an
>> asynchronous input. =A0Note that since your design has
>> more than one clock, asynchronous means any input that
>> was not created on the same clock used by the state
>> machine.
>>
>> -- Gabor
>
>How many times are we going to have this discussion, and how many
>times are people (like the OP) going to get burned when they don't
>believe the following:
>
>"The most common reason for a state machine to go haywire is that it
>has a state transition that depends on an asynchronous input."
>
>All inputs that are used in a 'conditional' in a state machine MUST be
>synchronized to the state machines clock.
>
><http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/
>1ea0ba1a1005287f/0e3c67b4b4163205>
><http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/
>fa2dba1d2e86c730/17568f37ad2dde1b>
>
>RK
>

All the inputs are synchronized with the state machine clock. It has
something to do with metastability of the signal that starts the state
machine because when i removed it, everything was in place. State machine
was in the IDLE mode as it should be.	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 150934
Subject: Re: Programming FPGAs with Quartus under Linux
From: dgreig <dgreig@ieee.org>
Date: Wed, 23 Feb 2011 01:22:34 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 23, 7:10=A0am, aldorus <h...@here.com> wrote:
> Ok I had a 95108 cpld based board (xilinx) and host pc running webpack
> ise 9.1. I had no problems programming the board (parallel jtag) onces
> WinDriver was installed.
>
> Now I have a Cyclone based board (altera) and host pc running quartus
> 10.0. I want to know if I will encounter any problems programming the
> device under linux. This particular board uses a USB interface with the
> controller on board - so I dont need a separate usb byteblaster.
>
> So my question is basically
> Has anyone had success programming fpga boards with quartus under linux?
> Did you use the usb byteblaster or some such interface?
> What did you do?
>
> Thanks

You will need to make sure the path environment vairable is set up and
install the driver (subdir "drivers" within the install dir). best
read the documentation.

It works fine on Scientific Linux 5.5 and 6.0 (RHEL5.5 & 6.0).

Article: 150935
Subject: Re: Most popular VHDL/Verilog
From: Philippe <philippe.faes@gmail.com>
Date: Wed, 23 Feb 2011 07:09:56 -0800 (PST)
Links: << >>  << T >>  << A >>
Thanks to all who have participated. The results are now online at:
http://www.vhdleditor.com
It may not be surprising, but this poll says Emacs is the most popular
VHDL/Verilog editor. Second and third are Notepad++ and VI.

Philippe

On Feb 15, 8:29=A0pm, Philippe <philippe.f...@gmail.com> wrote:
> Hi everybody.
>
> Could you please help me find out which is the most popular VHDL/
> Verilog editor, by filling out this poll:http://www.vhdleditor.com/poll
> I'm not looking for the "best VHDL/Verilog editor" (that would only
> get a flame war started). I'm just trying to find out which is used
> more often. So, please go and vote!
>
> thanks
>
> Philippe


Article: 150936
Subject: Re: Programming FPGAs with Quartus under Linux
From: Johann Streitwieser <Johann.Streitwieser@gmx.de>
Date: Wed, 23 Feb 2011 18:43:31 +0100
Links: << >>  << T >>  << A >>
aldorus wrote:

> Ok I had a 95108 cpld based board (xilinx) and host pc running webpack
> ise 9.1. I had no problems programming the board (parallel jtag) onces
> WinDriver was installed.
> 
> Now I have a Cyclone based board (altera) and host pc running quartus
> 10.0. I want to know if I will encounter any problems programming the
> device under linux. This particular board uses a USB interface with the
> controller on board - so I dont need a separate usb byteblaster.
> 
> So my question is basically
> Has anyone had success programming fpga boards with quartus under linux?
> Did you use the usb byteblaster or some such interface?
> What did you do?
> 
> Thanks

Hello,

I run quartus 10.1 (web) on ubuntu 10.10 without problems

For install please read this: http://www.philpem.me.uk/elec/fpga/quartus-
ubuntu/
More infos on: http://www.alterawiki.com/wiki/Main_Page

Johann


Article: 150937
Subject: how to keep iSE from grounding unused pins
From: Jon Elson <jmelson@wustl.edu>
Date: Wed, 23 Feb 2011 16:42:23 -0600
Links: << >>  << T >>  << A >>
I have an interface project using XC9500XL CPLDs, using iSE 10.1,
and it grounds all pins that don't have logic connected to them.
I have a couple pins connected to external busses, so they do not
need to be held to prevent floating voltages.  I see in the pin report
that they have been grounded with the "PGND" setting.  Is there a way in 
the UCF file or other way to prevent these several pins from getting the 
PGND option?  I'd want other unused pins to still be treated that way, 
but these pins are wired on the board for future expansion, but are
now jamming bus signals.

Thanks,

Jon

Article: 150938
Subject: How to keep iSE from grounding pins
From: Jon Elson <jmelson@wustl.edu>
Date: Wed, 23 Feb 2011 16:59:22 -0600
Links: << >>  << T >>  << A >>
I have an interface project using XC9500XL CPLDs, using iSE 10.1,
and it grounds all pins that don't have logic connected to them.
I have a couple pins connected to external busses, so they do not
need to be held to prevent floating voltages.  I see in the pin report
that they have been grounded with the "PGND" setting.  Is there a way in 
the UCF file or other way to prevent these several pins from getting the 
PGND option?  I'd want other unused pins to still be treated that way, 
but these pins are wired on the board for future expansion, but are
now jamming bus signals.

This is a one-page VHDL project.

Thanks,

Jon

Article: 150939
Subject: Re: How to keep iSE from grounding pins
From: Jon Elson <jmelson@wustl.edu>
Date: Wed, 23 Feb 2011 17:50:23 -0600
Links: << >>  << T >>  << A >>
On 02/23/2011 04:59 PM, Jon Elson wrote:
> I have an interface project using XC9500XL CPLDs, using iSE 10.1,
> and it grounds all pins that don't have logic connected to them.
> I have a couple pins connected to external busses, so they do not
> need to be held to prevent floating voltages. I see in the pin report
> that they have been grounded with the "PGND" setting. Is there a way in
> the UCF file or other way to prevent these several pins from getting the
> PGND option? I'd want other unused pins to still be treated that way,
> but these pins are wired on the board for future expansion, but are
> now jamming bus signals.
>
> This is a one-page VHDL project.
>
Hah, didn't think I'd be able to find this one myself!  In implement, 
right click, click properties menu, click fitting, and there's an option
"preserve unused inputs".  I turned that on, and ONLY the ports listed 
in the VHDL port list were kept as inputs, all pins not mentioned there
were set to PGND.  That's what I wanted to do, but I couldn't find 
ANYTHING in Xilinx's documentation or the forum that mentioned this option.

Jon

Article: 150940
Subject: Re: How to keep iSE from grounding pins
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 24 Feb 2011 01:55:24 +0000 (UTC)
Links: << >>  << T >>  << A >>
Jon Elson <jmelson@wustl.edu> wrote:

> I have an interface project using XC9500XL CPLDs, using iSE 10.1,
> and it grounds all pins that don't have logic connected to them.
> I have a couple pins connected to external busses, so they do not
> need to be held to prevent floating voltages.  

I suppose you can turn on some option to float them, but you
can also connect them up as tristate outputs with the output
enable wired low.  

-- glen

Article: 150941
Subject: Re: timing issues at high speed
From: Mike Treseler <mtreseler@gmail.com>
Date: Wed, 23 Feb 2011 20:38:02 -0800
Links: << >>  << T >>  << A >>
On 2/23/2011 1:09 AM, salimbaba wrote:

> All the inputs are synchronized with the state machine clock. It has
> something to do with metastability of the signal that starts the state
> machine because when i removed it, everything was in place. State machine
> was in the IDLE mode as it should be.	

That start signal is also an input.
Is it synchronized?

                 -- Mike Treseler


Article: 150942
Subject: Re: timing issues at high speed
From: "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com>
Date: Thu, 24 Feb 2011 00:16:32 -0600
Links: << >>  << T >>  << A >>
>On 2/23/2011 1:09 AM, salimbaba wrote:
>
>> All the inputs are synchronized with the state machine clock. It has
>> something to do with metastability of the signal that starts the state
>> machine because when i removed it, everything was in place. State
machine
>> was in the IDLE mode as it should be.	
>
>That start signal is also an input.
>Is it synchronized?
>
>                 -- Mike Treseler
>
>
Yes it is synchronized. Ok i have solved the problem, in my opinion it must
be something to do with metastability of the start signal. I have solved it
by ANDing the start signal with a sync signal which i generate after 50
clock cycles. So, it ensures that no glitches or anything like that passes
through and my state machines don't get triggered. Don't know if it's a
good thing to do but what ever floats the boat, right ? Also, if there's a
better way around lemme know.And also, if anyone knows why this is
happening other than what i think, kindly tell me that also.


thanks	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 150943
Subject: Simulating mutiplication of 'X' with '0'
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Thu, 24 Feb 2011 10:11:24 +0100
Links: << >>  << T >>  << A >>
I am simulating multipliers [std_logic_vectors] with one factor containing 
'X' and the other has '0's, but the simulation gives me 'X'es as a result 
while I expected '0's. Is this a bug/weakness or is there any logical or 
technical reason at all for [dont' care]*zero<>zero?
Im working with Altera tools.



Article: 150944
Subject: Re: Simulating mutiplication of 'X' with '0'
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 24 Feb 2011 10:16:44 +0000
Links: << >>  << T >>  << A >>
On Thu, 24 Feb 2011 10:11:24 +0100, "Morten Leikvoll" <mleikvol@yahoo.nospam>
wrote:

>I am simulating multipliers [std_logic_vectors] with one factor containing 
>'X' and the other has '0's, but the simulation gives me 'X'es as a result 
>while I expected '0's. Is this a bug/weakness or is there any logical or 
>technical reason at all for [dont' care]*zero<>zero?
>Im working with Altera tools.

I suppose it would be possible for the sim model for a multiplier to treat 
all bits 0 on one input as a special case, but that adds complexity to the model
for questionable benefit.

"X" is not "don't care", ("-" is), it is "Indeterminate", usually as the result
of a design error. So it is normally good to propagate it when in any doubt,
rather than cover up the error.

- Brian

Article: 150945
Subject: Re: Simulating mutiplication of 'X' with '0'
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Thu, 24 Feb 2011 11:30:39 +0100
Links: << >>  << T >>  << A >>
"Brian Drummond" <brian_drummond@btconnect.com> wrote in message 
news:1obcm65dqmhc6eaogjnvq6q04sl4a5jqug@4ax.com...
> On Thu, 24 Feb 2011 10:11:24 +0100, "Morten Leikvoll" 
> <mleikvol@yahoo.nospam>
> wrote:
>
>>I am simulating multipliers [std_logic_vectors] with one factor containing
>>'X' and the other has '0's, but the simulation gives me 'X'es as a result
>>while I expected '0's. Is this a bug/weakness or is there any logical or
>>technical reason at all for [dont' care]*zero<>zero?
>>Im working with Altera tools.
>
> I suppose it would be possible for the sim model for a multiplier to treat
> all bits 0 on one input as a special case, but that adds complexity to the 
> model
> for questionable benefit.
>
> "X" is not "don't care", ("-" is), it is "Indeterminate", usually as the 
> result
> of a design error. So it is normally good to propagate it when in any 
> doubt,
> rather than cover up the error.

This is an multiplier + accumulator function, and the only way to propagate 
it is to add additional conditions to the input wich again adds logic at 
implementation stage. I've ended up with a generic input called simulate and 
conditional code, wich I don't like at all.



Article: 150946
Subject: Re: Simulating mutiplication of 'X' with '0'
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Thu, 24 Feb 2011 12:32:42 +0100
Links: << >>  << T >>  << A >>
"Morten Leikvoll" <mleikvol@yahoo.nospam> wrote in message 
news:FuGdnUiJXNslvfvQnZ2dnUVZ8vGdnZ2d@lyse.net...
>I am simulating multipliers [std_logic_vectors] with one factor containing 
>'X' and the other has '0's, but the simulation gives me 'X'es as a result 
>while I expected '0's. Is this a bug/weakness or is there any logical or 
>technical reason at all for [dont' care]*zero<>zero?
> Im working with Altera tools.

The only technological explanation I can think of is that '0' isn't really 
zero. It's "low" and "low" multiplied with "dont' care" is undefined. Maybe 
if I do integer conversion first, it will work?



Article: 150947
Subject: Difficulty in programming from PROM
From: "sam" <prateeksharma16@n_o_s_p_a_m.gmail.com>
Date: Thu, 24 Feb 2011 07:28:06 -0600
Links: << >>  << T >>  << A >>
Hello,
       I am using a custom FPGA board with xC3S250e-vq100 from xilinx and
the PROM XCF04S. I am using Master serial mode configuration and i have
permanently grounded M0,M1 and M2 mode select pins. I am using Platform
Cable USB II for programming the FPGA. My board has 6 pin JTAG header which
i connect to the Platform cable header. I am using Impact 12.4. The FPGA is
programmed properly when the bit file is downloaded directly to the FPGA
and i get the proper output signals on the I/O's.
When PROM is programmed the message on impact says " Program Succeeded " .
Given below is the console message. 
'2': Loading file 'C:/Users/tsrc/Desktop/FPGA Board
Test/fpgaboardtest/test.mcs' ...
done.
INFO:iMPACT - Current time: Sun Feb 13 16:15:37 2011
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'2': Erasing device...
'2': Erasure completed successfully.
'2': Programming device...
done.
'2': Putting device in ISP mode...done.
'2': Putting device in ISP mode...done.
'2': Verifying device...done.
'2': Verification completed successfully.
'2': Calculated checksum matches expected checksum, 00568e386
'2': Putting device in ISP mode...done.
'2': Putting device in ISP mode...done.
'2': Setting user-programmable bits...
done.
'2': Putting device in ISP mode...done.
'2': Starting FPGA Load with Prom Data...INFO:iMPACT:563 - '2':Please
ensure proper connections as specified by the data book ...
'2': Programming completed successfully.
'2': Programming completed successfully.
PROGRESS_END - End Operation.
Elapsed time =     14 sec.

The TCK speed was 6 MHz. Judging from the Console message i am guessing the
PROM is programmed correctly. But when i try to start up or pull down PROG
pin momentarily low the FPGA is not programmed. I do not get any output
signals on the I/O's. I did checked the DIN pin on FPGA using. When Started
up or gave 0 on PROG pin using push button i saw the random bits which i am
guessing is configuration data. I also observed that the CCLK pin on the
FPGA is continuously giving out the clk pusles no matter what when the PROM
is programmed but goes off when only FPGA is programmed.

I have tried to follow the schematics from FPGA precisely but still have no
clue what is wrong.

Please help
Thanks!


	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 150948
Subject: Having two PLB Bus in XUPV2P
From: "lamiastella" <mona66jalal@n_o_s_p_a_m.gmail.com>
Date: Thu, 24 Feb 2011 07:28:14 -0600
Links: << >>  << T >>  << A >>
Hi,
I just can't have two PLB bus in my design . I use a XUPV2P Virtex 2 pro
FPGA.
Do you have any idea about solving this problem?

Best regards.


	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 150949
Subject: How to transfer some data with FlashPro through JTAG into Actel Fusion FPGA ?
From: "Dayn" <daynbrad77@n_o_s_p_a_m.hotmail.com>
Date: Thu, 24 Feb 2011 07:28:24 -0600
Links: << >>  << T >>  << A >>
Hello everybody,

I'm looking for the way to transfer some datas (like .hex files) with
FlashPro soft through JTAG into Actel Fusion FPGA.

The FlashPro UG explain how to programming but not how to transfer datas.

Can Somebody help me to find a way to make that with FlashPro soft ?

I'm looking for that, because I want to save these Datas into a Flash
memory linked to this FPGA.

Best regards,

Dayn

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search