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In article <36DDAA02.ACBA2D71@xilinx.com>, Peter Alfke <peter.alfke@xilinx.com> wrote: >Joel Kolstad wrote: > >> Does anyone have a clever circuit that can divide an input >> clock by two and >> a half? We're looking to go from 100MHz down to 40MHz. > >The easiest, simplest and safest method is to cheat and >build a circuit that divides alternatingly by 2 and by 3. So >it generates two output periods for every five input >periods. You have your 40 MHz average output frequency, but >the two adjacent output periods are of unequal length, one >of them 20 ns, the other one 30 ns. That circuit is trivial >to implement in two CLBs. > There is actually a simpler way of doing this in the Virtex architecture. The Clock DLL circuits in Virtex allow you to divide the input clock by 2.5, require no CLB resources and none of the jitter problems associated with the other solutions in this thread. EdArticle: 15126
Daniel K. Elftmann wrote: > <snipped long post> > > I apologize upfront to those that see this as self-promoting vendor > propaganda. > At the risk of turning this into a "fast FPGA I/O" thread, I have no problem with vendors pushing uniquely fast parts backed by good data and application notes. The SX parts have very nice I/O timing and are certainly worth a look. (http://www.actel.com) It wasn't clear to me whether or not the free tools actually support the SX parts yet. This would definitely encourage designers with limited tool budgets to give them a try. Availability of SX IBIS I/O models would be nice, too (they weren't in the IBIS area when I checked) regards, Tom BurgessArticle: 15127
Hi! My name is Amy Wakefield and I was reviewing this forum to learn more about the industry that I work in and I was also looking to see if any of you can help me. I am conducting a confidential search for a client who is looking for several Design Engineers. They are looking for serious talent, at least 5 years in a design environment, using Intel Technologies, doing board level design. This is a fabulous opportunity for someone to get out of the corporate bureaucracy and become a BIG FISH in a SMALL pond. You can see a direct relation between your ideas and work to the company's bottom line line. But they are not a start up, so you don't have to wonder about their stability. They have a great group on board right now, and are very excited about adding new people who want to be individual contributors and part of a very dynamic team. This company has great relocation packages, competitive salaries and great benefits! What I really need from you is who you are in contact with, maybe former co-workers, professional associates, who might be interested in looking for a new position. Feel free to email me at the address you see and let me know what your ideas are! Thanks so much for your time! Amy Wakefield Sr. Recruiter Hall Kinion email me:awakefield@hallkinion.com -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15128
<snip> > : Generally, are how much tweaking with placement and timing constraints is > : required for the current crop of cores? My experience has only been with Xilinx. Things are certainly better than they were in the past. Basically, parts are now much faster, by at least 2x, over a few years ago, so implementing any PCI design (target/master/burst), and making timing isn't as big a feat as it was a few years ago....BUT... If you want to run in as inexpensive a part as you can, then you will have to do more placement and logic mapping than you would if you ran in a faster/more expensive part, and did less work on the placement/logic mapping. In either case, you need to make a good set of timing constraints for the placer/router to use...and you will probably make timing with minimal floor planning in the faster parts. In any PCI design, the PCI design is usually only half the job. The other half is the back end interface, so don't underestimate that amount of work... I feel $5k is a bargain for the PCI core...given how much work it is to do it in the first place. That's really only 2 weeks of engineering $$ at best. You can probably even get away with using some HDL to do this design, if you use a fast enough part ;-) I always found using schematics for PCI interfaces has been a much better design methodology because I have much better control over the placement and logic mapping than an HDL. I would like to believe that will change in a year or so....but if you want to run in the cheapest part you can, then I would strongly suggest the design be done in schematics. If cost is not a primary concern, than an HDL may suffice. Austin Franklin austin@darkroom.comArticle: 15129
You can get a free evaluation PCI Logicore from your local Xilinx salesman ..... then make your own judgement. Stosh Bob Bauman wrote in message <7bppqe$qlv$1@birch.prod.itd.earthlink.net>... >Hi all, > >About a year and a half ago I was considering implementing a PCI interface >in an FPGA. At that time I decided that the design was going to be very time >consuming and posed compatibility risks. Altera's and Xilinx's cores seemed >to require quite a bit of tweaking and they were expensive. > >As I embark down this path again, I thought I might illicit the response of >this newsgroup to the current state of PCI cores and development tools >supplied by Altera, Xilinx, and others. Hopefully, this topic was not just >recently discussed in a thread that I missed. If so, I would appreciate >being directed to an archive. > >From my initial survey it appears that Xilinx has put the most effort into >supplying PCI cores of various flavors that are supposedly easy to plunk >into a design. Is this observation correct ? Does anyone who has used either >or both of the Altera and Xilinx cores have any strong opinions? > >Generally, are how much tweaking with placement and timing constraints is >required for the current crop of cores? > >Thanks in advance. > >Bob Bauman > > >Article: 15130
Isn't there anyone frothing at the mouth to post the usual cynical but incisive followup to this posting ? amy_wakefield@my-dejanews.com wrote: > > Hi! My name is Amy Wakefield and I was reviewing this forum to learn more > about the industry that I work in and I was also looking to see if any of you > can help me. > > I am conducting a confidential search for a client who is looking for several > Design Engineers. They are looking for serious talent, at least 5 years in a > design environment, using Intel Technologies, doing board level design. This > is a fabulous opportunity for someone to get out of the corporate bureaucracy > and become a BIG FISH in a SMALL pond. You can see a direct relation between > your ideas and work to the company's bottom line line. But they are not a > start up, so you don't have to wonder about their stability. They have a > great group on board right now, and are very excited about adding new people > who want to be individual contributors and part of a very dynamic team. This > company has great relocation packages, competitive salaries and great > benefits! > > What I really need from you is who you are in contact with, maybe former > co-workers, professional associates, who might be interested in looking for a > new position. Feel free to email me at the address you see and let me know > what your ideas are! Thanks so much for your time! > > Amy Wakefield > Sr. Recruiter > Hall Kinion > email me:awakefield@hallkinion.com > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15131
Theseus Logic is a company that is working on self-timed circuit. Visit their home page. I am sure they would be helpful. - Sri J. Khatib <khatib@ieee.org> wrote in article <36DCDC1C.C1817CD7@ieee.org>... > Hi > Please what is the Self-Timed circuit design technique? Is it > synchronous, asynchronous or something different? > > What its advantage over the traditional design techniques? > > > Thanks in advance >Article: 15132
Hi all - We're finding it a constrant struggle to keep our programmers up to date in programming small scale programmable logic devices: 16V8's. Every manufacturer has a different algorithm, and every revision of the device seems to change the algorithm too. One of my older programmers can still do EPROMs but is completely non-functional for reading and writing 16V8's. And, of course as has been explained here before, the manufacturers are very reluctant to give out the programming information. The result is that the big guys in the logic progammer business, and only the big guys, have the resources to keep their logic device programmers up to date. This is in contrast to the EPROM programming business, which is more or less standardized, and as a consequence one can buy an EPROM programmer at a reasonable price and be confident it will not be a boat anchor in 5 years. For example, it is completely within reason for a student to purchase an EPROM programmer, but a logic progammer is far too expensive. In circuit progammable devices are an attractive alternative to this mess, and the somewhat higher price is not a major problem to the student or small quantity user. Unfortunately, these devices do not seem to be second-sourced and of course they are not nearly as readily available as the 16V8. For example, in Toronto, Active Surplus, notable by the animated gorilla on the doorstep, has Lattice 16V8's for $3, which is unlikely to be the case for ISP devices for the forseeable future. I would argue that a standard programming algorithm will entice new, low cost programmers into the market and open up larger markets for the devices themselves. After all, it's clear that 7400 bubblegum logic is on the way out. There are no villains in this case that I can see, but surely there needs to be some sort of JEDEC standard for programming these very common, second-sourced devices. So, why can't we have a standard for this? Peter -- Peter Hiscocks Phone: (416) 979-5000 Ext 6109 Department of Electrical Engineering Fax: (416) 979-5280 Ryerson Polytechnic University, Email: phiscock@ee.ryerson.ca Toronto, Ontario, M5B 2K3, Canada ******************************************************************* * There are worse things than being wrong, and being * * dull and pedantic are surely among them. * * * * Mark Kac, in 'Discrete Thoughts: * * Essays on Mathematics, Science and Technology' * *******************************************************************Article: 15133
hdl_fan@my-dejanews.com wrote:
> 1. Shall I give two OFFSET constraints for both directions of
> an inout port in the SAME UCF file? I am using both directions
> of these pads occasionally in the design.
>
> NET "ram_data_bus<*>" OFFSET=IN 10 BEFORE ram_if_clk ;
> NET "ram_data_bus<*>" OFFSET=OUT 10 AFTER ram_if_clk ;
>
Yes
>
> 2. Some pads are driven by logic triggered by an internal clock
> but not external clock. I tried to constrain these pads with:
>
> NET "some_pin<*>" OFFSET=IN 10 BEFORE internal_clk ;
>
> where internal clock is running 12.5 MHz and derived from
> 25 MHz. But Xilinx Design Manager gave error:
>
> ERROR:basts:168 - NET 'internal_clk' , which is the reference clock net
> for the OFFSET 'some_pin<4> IN : 10000.000000 pS : BEFORE : internal_clk',
> is not a pad related net (not driven by a pad).
>
you can try if these pads goes only to flip-flops using 'internal_clk' as the
clock:
timegrp "some_pads" = PADS ("some_pin<*>");
timespec TSP2S = FROM : "some_pads" : TO : FFS : 10 ns;
Of course, this does not include the setup time.
>
> How can I give constraint to pad via internal clock???
>
> Utku
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
Michel Le Mer
(33) 2 99 51 17 18
Gerpi sa
3, rue du Bosphore
Alma city
35000 Rennes
France
Article: 15134test of news serverArticle: 15135
Hi, I am about to configure my very first SpartanXL device and I was hoping to find some pointers on it. I am wondering if it is ok not to use the XC17S10XL that Xilinx recommend for the XC17S10XL? If so which SPROM would be the best to use? Regards, Rickard Norberg -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15136
Pierre Langlois wrote: > Hello all, here's my problem: > > I have a DSP design which fits nicely in a X4010E chip. The design was > described in VHDL, and I used the Xilinx F1.5 tools to synthesize, map, > and PAR. In order to meet stringent timing requirements, I also had to > use Floorplanner to manually place components on the critical paths, and > obtained results much improved from what PAR could do. > > Now, I want to reuse this design in a larger one by adding some > front-end and back-end processing. The new design should go in a larger > chip, and maybe a different family. Obviously, I would like to re-use > my manual placement information instead of spending three or four days > going through the process again. > > The Xilinx documentation says that guided mapping and incremental design > with the Floorplanner constraints is not recommended for VHDL-based > designs, because every new synthesis may generate different signal and > instance names. I'm not the kind of guy who takes no for an answer, at > least not initially. Therefore, I was hoping to be able to generate > some kind of RPM from my first design and use it as a whole component in > another design, much like using a Logiblox component. I haven`t been > able to find a way to do this. > > Can anyone recommend a process that would allow me to solve this > problem? Thanks in advance. > > =============================================== > Pierre Langlois > Département de mathématiques et informatique > Collège militaire royal du Canada tél. (613)541-6000 x6860 > B.P. 17000 Succ. "FORCES" fax. (613)541-6584 > Kingston ON K7K 7B4 Canada langlois-p@rmc.ca > =============================================== I do not how to do it entirely but hope this could help. If you use vhdl entry, you can specify a black box by : attribute black_box : boolean; attribute black_box of my_logiblox : component is true; and just define my_logiblox as any other component and instantiate its ports. I guess that you have to synthesize my_logiblox alone, (without pads ? preserve hierarchy?) Does that create a logiblox? You can use the placement constraints to map into an area. (inside a rectangular area : RnCn to RmCm). An other way is to map and place my_logiblox alone into a chip big enough to accept the future full design. Then add your modification and set the "copy guide (map and flooplanner) to clipboard". Could you let me know if you find a solution please. Good luck. Michel Le Mer.Article: 15137
Places that sell software for JTAG testing of boards will generally have something that will program a chain of PLDs with a mix of vendor's parts. Two that I have run across are: Asset Intertech http://www.asset-intertech.com/ and Corelis http://www.corelis.com/index.html I've looked into both a little bit, but have no direct experience using either product. bob elkind wrote in message <36E05BF0.9FA16865@aracnet.com>... >Is there a common, single solution set for hw and sw to program FPGAs and serial ROMs and CPLDs, from a PC parallel port to a >JTAG port? > >Xilinx has the Parallel Cable (with software modules that are proprietary to Xilinx)... > >Altera has the JAM language and Byte Blaster (and JAM is officially non-propietary, > but is there JAM support for non-Altera devices?)... > >Altera's ByteBlaster is very similar to Xilinx' Parallel Cable, except the pinouts are different. Hence the SW to drive them is >different. Is there a single, common solution for programming and/or testing A's and X's devices that are both JTAG supporters >? > >Thanx in advance, > >-- Bob Elkind, eteam@aracnet.comArticle: 15138
The problem which you describe is not in the Jedec file formats. It is caused by the fact that while EPROM programming methods have hardly changed (and most recent devices can in fact be programmed using "old" algorithms, without damage), PLD programming methods vary all the time. So, a 16V8A and a 16V8B (both from the same mfg) might use different programming voltages. So before you buy a programmer, you must verify support for that **specific** manufacturer and device. This makes programmer support hard to maintain, and it creates a nice gravy train for those programmer manufacturers who charge for updates, and who like to discontinue new device support on a particular model. Also, the details of the algorithms are confidential, and this has kept home building to a very low level. You can purchase cheap programmers easily enough, and they will generally program the old devices. The problem is that you may not be able to purchase the devices themselves any more, and this means you have to buy a newer programmer. There is a separate problem with Jedec file formats, with many programmers being unable to read files formatted in a certain way (usually because the developer's stupidity). But that is another story. >There are no villains in this case that I can see, but surely there needs to >be some sort of JEDEC standard for programming these very common, >second-sourced devices. So, why can't we have a standard for this? -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 15139
A firm called Cogency Technology Inc. also has methodologies and software
for self-timed integrated circuit design. See http://www.cogency.com
The advantages include reduced power consumption, reduced ground and
substrate noise, as well as a number of commercial/developmental
advantages.
In article <01be69d2$4fef8b20$cb4f14cf@spike3.spiketech.com>,
Spike Technologies <sri@spiketech.com> wrote:
>Theseus Logic is a company that is working on self-timed circuit. Visit
>their home page. I am sure they would be helpful.
>
>- Sri
>
>J. Khatib <khatib@ieee.org> wrote in article
><36DCDC1C.C1817CD7@ieee.org>...
>> Hi
>> Please what is the Self-Timed circuit design technique? Is it
>> synchronous, asynchronous or something different?
>>
>> What its advantage over the traditional design techniques?
--
Lorne Wilkinson mailto:lrw@interlog.com http://www.interlog.com/~lrw
"Going forward, please, please, don't lick the neon sign..."
Interlog Internet Services - Toronto, Canada (416)-920-2655
Article: 15140Any lessons learned on power up sequence with 24c04. Initially there might be some activity on the SCL SDA lines as master and eeprom power up. I suppose one might accidently give a start to the eeprom. But, the eeprom has warm up time, so maybe it would ignore anyway. If the master did give a bogus start... some time later the master would give a real start. Hmm. Would the eeprom be responsive? I guess the eeprom would be hanging looking for address? (the state machine internal to the eeprom.) Any hints? Thanks. JimArticle: 15141
1. I'm looking for the numbers of fan out that the secondary clock lines can drive. 2. Is there a way to get the same skew on a gated clock line and the same clock line but not gated.Article: 15142
Rickard Norberg wrote: > Hi, > > I am about to configure my very first SpartanXL device and > I was hoping to > find some pointers on it. I am wondering if it is ok not > to use the XC17S10XL > that Xilinx recommend for the XC17S10XL? If so which SPROM > would be the best > to use? There is nothing special about SpartanXL in Master Serial configuration mode. It behaves like any other Xilinx 3.3V device. I would keep the configuration speed at SLOW ( 1 MHz, the default ) You can use any Xilinx SPROM that is large enough and works at 3.3 V. Hälsningar och lycka till. Peter Alfke, Xilinx ApplicationsArticle: 15143
New User wrote: > Any lessons learned on power up sequence with 24c04. This sounds like a familiar problem when the design blindly relies on FPGA ( what's a 24c04?) and EPROM properly waking up together. Murphy does not sleep!That's why I always recommend keeping the SPROM reset as long as possible, e.g. by driving its RESET from the INITbar output of the (Xilinx) FPGA. That method is 100% safe. Peter Alfke, Xilinx ApplicationsArticle: 15144
Hello, The Xilinx F and G generators are capable of implementing any 4 bit function (arbitrary). If you assume 4 inputs then 16 possible product terms arise. like abcd, a_bcd, ab_cd etc.. There are 2^16 different sum of product functions. How does Xilinx implement these in a 16 bit RAM or LUT. Can anybody give details as to how this implementation is achieved. I feel this sort of implementation should consume 64K bits to implement all possible functions. Can somebody give details of how this LUT implementation is carried out Thanks in advance Shardendu Pandey -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15145
I have inherited a design for a xilinx chiip that uses VHDL and about a one page schematic using Xilinx's foundation tool. I am looking for a way to "lock" in the current design as far as place and route to keep the timing constraints constant during a couple of minor logic changes. Unfortuantely Foundations option to use a previous design as a "guide" for the current design appears to re-place and re-route about half the clb's. Does anyone know of a way to keep the place and route from a previous design from changing short of using the EPIC design editor?Article: 15146
pandey@my-dejanews.com wrote: > Hello, > > The Xilinx F and G generators are capable of implementing > any 4 bit function > (arbitrary). If you assume 4 inputs then 16 possible > product terms > arise. like abcd, a_bcd, ab_cd etc.. > > There are 2^16 different sum of product functions. > How does Xilinx implement these in a 16 > bit RAM or LUT. Can anybody give details as to how this > implementation is > achieved. I feel this sort of implementation should > consume 64K bits to > implement all possible functions. > You are correct in saying that a 4-input look-up table can be programmed 65,536 different ways. That is the beauty of a look-up table. But the implementation ist just a simple 16-bit ROM with 4 address lines. Effectively, we store a 16-bit word in the LUT, and you must agree that there are 65,536 different possible 16-bit words. The LUT is built pretty much like a conventional ROM, with 16 latches, read out by a tree-structure reducing the 16 inputs to one output. The decoding is done with pass transistors. Therefore we can claim that there never is a glitch when you change only one address input. And there also is no glitch when you change two address lines more or less simultaneously if - and only if - all four address combinations generate the same output. I get that question quite often Peter Alfke, Xilinx ApplicationsArticle: 15147
It's doing this because the net names change when the design is resynthesized. I don't know of a way around this without writing your code structurally with RLOC attributes (which I don't think FPGA express supports). Maybe you can use the edif to vhdl utility to generate a structural design and make the changes to that. I'm not sure that will do the trick, and it certainly ain't pretty. Anyone else? Fred Ganong wrote: > I have inherited a design for a xilinx chiip that uses VHDL and about a > one page schematic using Xilinx's foundation tool. I am looking for a > way to "lock" in the current design as far as place and route to keep > the timing constraints constant during a couple of minor logic changes. > Unfortuantely Foundations option to use a previous design as a "guide" > for the current design appears to re-place and re-route about half the > clb's. Does anyone know of a way to keep the place and route from a > previous design from changing short of using the EPIC design editor? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15148
I've got a weird one I can't see to figure out. I have two XC300 Virtex parts on my board which are being programmed in Master serial mode (ie. first one is in master serial mode and the second is in slave serial mode). When I disable my 50 MHz system clock (this clock has nothing to do with the programming ... only required for operation ... it is connected to one of the GCLK pins) the parts program every time. But, when the 50 MHz clock is running the parts will not program. I'm convinced this is not a noise / interference type of problem ... my board has solid power and ground planes and decoupling is quite generous. I'm starting to suspect something weird in the Virtex part itself. Has anyone seen any similar problems with the Virtex parts? Thanks, mark More Info ... The 50 MHz clock is comming from a 5V clock driver IC ... The Vccio of the Virtex parts are connected to 3.3V which should provide 5V tolerence ... in playing around I have inserted a low value resistor (50 ohms) in series with the clock line between the buffer and the Virtex ... with this setup the parts will program part of the time with the clock runningArticle: 15149
Michael J Sharples > wrote in message <7bspct$k6u$1@news-2.news.gte.net>... >1.) Is it a practical project given a two month window for a working model? Perhaps. Probably. It depends upon experience and available time, and of course some folks learn and work much faster than others. See the DWARF 8-bit CPU design in chapter 10 of Vanden Bout's "The Practical Xilinx Designer Lab Book" of the Xilinx Student Ed. kit. Build it, boot it, then modify it to suit, or design a new CPU based upon what you learn from your DWARF experience. >2.) What resources(specifically as possible)are helpful in designing a >control unit that manages seven registers, eight instructions on eight-bit >words, and controls a 32k X 8-bit memory. (((Your datapath will probably require a register file made from RAM16X8S or RAM16x8D, an adder made from an ADSU8, a logic unit of 8 instances of a 4-1 mux of (a[i]&b[i], a[i]|b[i], a[i]^b[i], ~a[i]), and some muxes and registers. You might as well store the program counter in the register file and reuse the adder to increment PC. To interface to external SRAM, consider clock-enabled IOB output flip-flops (OFDXs) for A[14:0], and 3-state IOB outputs (OBUFT8 or OFDTX8) and input buffers (IBUF8 or IFDX8) for D[7:0].))) For your control unit, consider a random logic state machine design written in ABEL (as is the DWARF design). Jan Gray www3.sympatico.ca/jsgray/homebrew.htm
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