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There are Atmel replacements for the EPC1 (under their FPGA configuration memories) which are electronically erasable, but again they do not have an 8 pin dip version. Perhaps an adapter would work, but it won't look good. :-) Thanks, Garrick Peter Sørensen wrote: > > I looked too and found nothing. > There no standard serial EPROMs that big. > I suppose you know of the EPC2 which can not fit into the 8 dip package. > > Hi Peter > > Garrick Kremesec wrote: > > > Hello, > > > > This was brought up recently, but are there any erasable replacements > > for the 8 pin dip Altera EPC1? I'm really looking for something that is > > pin/function equivalent yet either electronically erasable or UV > > erasable. > > > > Thank you for the help. > > > > Garrick Kremesec > > University of Illinois > > gkremese@ews.uiuc.eduArticle: 16901
We have ordered this board and are awaiting delivery. Don't know how good it'll be, but there are very few around at the moment, only others I found were from nallatech (about 5K) and annamicro (or something like that - can't remember the name)- a wildfire board anyway. We've ordered the Xilinx Foundation software and Xchecker cable to join up the board to our nice new spangly PIII to run the software - Once we have the system up and running and have run a few demos I'll post a message to the newsgroup to let you know how it is going (hopefully within 3-4 weeks if the stuff arrives) If it all goes well we're hoping to order another board and pc to do more work on if they turn out to be good Anyone acutally used one yet? Davide Anguita wrote: > Hi all. > I'm currently planning to purchase a Virtex prototype board. > The VCC VW-300 ( http://www.vcc.com ) looks appealing. > Any advise, suggestion, experience on this (or similar) board ? > > Thanks a lot, > > -- Davide. -- Bio-Inspired Architectures Department of Electronics University of York, UKArticle: 16902
> > I don't use the SPO's of some DP RAM's on XC40150XV. > > NGDBUILD and XNF2NGD give warnings. Do these warnings > > imply a possibly bad routing architecture? Shall I > > use the commands which ignore these pins? I have > > used following command but the warnings didn't go away: > > > > NET "dp_ram_spo<*>" TIG=TS01; > > > > Shall this TS01 be defined for write clock of the Dual > > Port RAM? Shall I use such a command to improve the > > performance? > > > > Utku > > Which warning do you have? > > Michel Le Mer In the output file of NGDBUILD, chip.bld, following warnings: WARNING:basnu:113 - logical net "top_level_ram_table_un1_ram<13>" has no load I am using Synplify and this net corresponds to the SPO output of a Dual Port RAM. The SPO outputs of this Dual Port RAM are not used. Do the unused pins of a macro consume FPGA resources? Are the unused pins of a macro taken into consideration in Static Timing Analyzer TRACE? UtkuArticle: 16903
Switch to Exemplar's Leonardo Spectrum. It handles recursive structures very nicely. I use them all the time in my VHDL library code. The problem you are having is a tool issue, not a language issue. John McCluskey J.McCluskey@nospam.ieee.org Sandro Wefel wrote: > A problem occurs under Aldec Active VHDL 3.3 if I > try to use recursive structures e.g. recursive architectures > of an entity. The code in the appendix is from the > book "The Designer's Guide to VHDL" but the error > occurs on all files using recursive architectures. > The code describes a fanout_tree. The generic parameter > height is mapped in each recursionsstep to a smaller > value and the recursion terminates when height=0. > I also wrote a testbench tree_test instantiating the > fanout_tree and mapping height to an initial value of 3. > The compilation is succesfull but if I try setting tree_test > as top-level I get the following error: > > ELBREAD: Error: Circular reference in 'Versuch1.fanout_tree(recursive)': instance 'subtree_0'. > ELBREAD: Error: Elaboration process completed with errors. > Design: Error: Elaboration failed > > Is this an error of AVHDL3.3 or have I make a mistake? > > Sandro Wefel > > ------------------------------------------------------------------------ > library ieee; > use ieee.std_logic_1164.all; > > entity buf is > port ( a: in STD_LOGIC; > y: out STD_LOGIC ); > end entity buf; > > architecture basic of buf is > begin > -- a simple buffer !!! > y <= a; > end basic; > > library ieee; > use ieee.std_logic_1164.all; > > entity fanout_tree is > generic ( height: natural); > port ( input: in std_logic; > output: out std_logic_vector ( 0 to 2**height-1) ); > end entity fanout_tree; > > architecture recursive of fanout_tree is > begin > degenerate_tree: if height = 0 generate > begin > output(0) <= input; > end generate degenerate_tree; > > compound_tree: if height > 0 generate > signal buffered_input_0, buffered_input_1 : std_logic; > begin > buf0: entity work.buf(basic) > port map ( a=> input, y=> buffered_input_0); > > subtree_0 : entity work.fanout_tree(recursive) > generic map ( height => height-1 ) > port map ( input => buffered_input_0, > output => output(0 to 2**(height-1)-1)); > > buf1: entity work.buf(basic) > port map ( a=> input, y=> buffered_input_1); > > subtree_1 : entity work.fanout_tree(recursive) > generic map ( height => height-1 ) > port map ( input => buffered_input_1, > output => output(2**(height-1) to 2**height-1)); > > > end generate compound_tree; > > end architecture recursive;Article: 16904
Tim Tyler <tt@cryogen.com> writes: > It appears to me that a large volume of the FPGAs in use today are > employed to prototype silicon designs. Glue logic in mass market designs is probably a much bigger piece of the revenue pie. > The whole point of FPGAs, is that > Say I am implementing a lattice-gas automata in order to simulate > turbulent fluid flow through a confined space. What earthy use are > counters or addition and subtraction primitives to me? None > whatsoever. Perhaps you'd be interested in some of the purpose-built CA machines that have been presented at FCCM. This one looks appropriate: Margolus, N., "An FPGA Architecture for DRAM-based Systolic Computation," FCCM 1997, pp 2-11. -- Jack Greenbaum -- j.greenbaum@computer.orgArticle: 16905
IPU wrote in message <7k7sgk$arb$1@black.news.nacamar.net>... >Hi newsgroup, >I have a simple (?) problem using VHDL and Viewlogic. After declaration of >an entity I use VHDL2SYM.EXE to create a symbol for ViewDraw. It works fine, >but I want to have an active low signal (signalname with overline) in my >schematic. >I have no idea how to realize it in VHDL . Any suggestions? VHDL, being a text-only language, has no way of indicating that a signal is active low. Some people like to create signal/variable names that indicate that a signal is active low. I use _l (as in oe_l for an output enable). Since the language doesn't have any way to indicate active low, the symbol generator utility won't be able to put bars over signals. Can you go in an edit the symbol? (Probably not, at least without breaking connectivity.) -- a ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu NY Knicks in '99: "Ya gotta believe!"Article: 16906
wannarat wrote in message <376765C7.6BA5680A@kmitl.ac.th>... >Hi > Can use FPGa with Analog circuit design (ADC , DAC )? >Or can i use circuit about RF with FPGA? >Please suggest me!!! >Xilinx can do that? >REgard. >Wannarat Suntiamorntut >E-mail : ksuwanna@kmitl.ac.th Answers to your questions: No, no and no. -- a ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu NY Knicks in '99: "Ya gotta believe!"Article: 16907
Sandro, This issue has been addressed in Active-HDL 3.5 released June 1st - please check with your distributor how you can upgrade. BTW, John's suggestion to switch to Leonardo is of the 'comparing apples to oranges' sort: Active-VHDL is design entry environment with VHDL simulator, Leonardo is first of all synthesis tool... Thank you, Jerry Sandro Wefel <wefel@informatik.uni-halle.de> wrote in message news:3767446A.2DC001A2@informatik.uni-halle.de... > A problem occurs under Aldec Active VHDL 3.3 if I > try to use recursive structures e.g. recursive architectures > of an entity. The code in the appendix is from the ....Article: 16908
#2 rang a bell. This is a known bug. The message can be safely ignored. See Solution #3152 on the Xilinx Answers data base: http://www.xilinx.com/support/support.htm You should check for other 9500 software "solutions" while you're there, too. regards, tom Martin Maurer wrote: > > Hello, > > i have three question come up when using Xilinx Foundation: > > 1) I got the following message by ngd2edif: undriven net "PRLD". > What does it mean, how can i prevent it ? > > 2) I got another message by ref_2_inst: dangling ports. > Is this a warning or error. Must/Can i do something to prevent it ? > > 3) I use the following in one of my designs with a XC95108: > <snipped> Tom Burgess -- Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.caArticle: 16909
Utku Ozcan wrote: > In the output file of NGDBUILD, chip.bld, following warnings: > > WARNING:basnu:113 - logical net "top_level_ram_table_un1_ram<13>" has no load > > I am using Synplify and this net corresponds to the SPO output > of a Dual Port RAM. The SPO outputs of this Dual Port RAM are > not used. > > Do the unused pins of a macro consume FPGA resources? > > Are the unused pins of a macro taken into consideration in > Static Timing Analyzer TRACE? > > Utku I am pretty sure that you can ignore this message. I would get the same message from a schematic based design where I used dual port RAM elements. It is simply a warning for you to look at your design to make sure you haven't missed something, which in this case you haven't. This type of message can indicate that the element with an unused output would be optimized away, but in this case there are other used outputs which will prevent that from happening. I am also pretty sure that the unused outputs do not consume any additional resources either. They are outputs from the CLB that do not get routed. So they can also be ignored. I don't believe these unused outputs will be analyzed by TRACE since they don't connect to a measurement point such as a FF, an IO pin or another RAM. So once again, I think you are safe. Perhaps one of the Xilinx Gurus can verify this? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16910
Go to www.optimagic.com for a pretty comprehensive list of what is out there. Rickman wrote: > I need to test a design that will interface directly to the PC ISA bus > via an FPGA. I am looking for an off the shelf board that connects all > of the ISA bus signals to the FPGA, or at least the subset needed for a > standard IO card. Does anyone know of such a board? > > There were a number of posts on this recently, but most of them have > expired from my server. > > I believe there were a few posts listing lists of FPGA boards. Can > anyone repost them? > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16911
Get version 3.5. I've done recursive structures there without any problems. Sandro Wefel wrote: > A problem occurs under Aldec Active VHDL 3.3 if I > try to use recursive structures e.g. recursive architectures > of an entity. The code in the appendix is from the > book "The Designer's Guide to VHDL" but the error > occurs on all files using recursive architectures. > The code describes a fanout_tree. The generic parameter > height is mapped in each recursionsstep to a smaller > value and the recursion terminates when height=0. > I also wrote a testbench tree_test instantiating the > fanout_tree and mapping height to an initial value of 3. > The compilation is succesfull but if I try setting tree_test > as top-level I get the following error: > > ELBREAD: Error: Circular reference in 'Versuch1.fanout_tree(recursive)': instance 'subtree_0'. > ELBREAD: Error: Elaboration process completed with errors. > Design: Error: Elaboration failed > > Is this an error of AVHDL3.3 or have I make a mistake? > > Sandro Wefel > > ------------------------------------------------------------------------ > library ieee; > use ieee.std_logic_1164.all; > > entity buf is > port ( a: in STD_LOGIC; > y: out STD_LOGIC ); > end entity buf; > > architecture basic of buf is > begin > -- a simple buffer !!! > y <= a; > end basic; > > library ieee; > use ieee.std_logic_1164.all; > > entity fanout_tree is > generic ( height: natural); > port ( input: in std_logic; > output: out std_logic_vector ( 0 to 2**height-1) ); > end entity fanout_tree; > > architecture recursive of fanout_tree is > begin > degenerate_tree: if height = 0 generate > begin > output(0) <= input; > end generate degenerate_tree; > > compound_tree: if height > 0 generate > signal buffered_input_0, buffered_input_1 : std_logic; > begin > buf0: entity work.buf(basic) > port map ( a=> input, y=> buffered_input_0); > > subtree_0 : entity work.fanout_tree(recursive) > generic map ( height => height-1 ) > port map ( input => buffered_input_0, > output => output(0 to 2**(height-1)-1)); > > buf1: entity work.buf(basic) > port map ( a=> input, y=> buffered_input_1); > > subtree_1 : entity work.fanout_tree(recursive) > generic map ( height => height-1 ) > port map ( input => buffered_input_1, > output => output(2**(height-1) to 2**height-1)); > > > end generate compound_tree; > > end architecture recursive; -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16912
BOPS has the following positions available for Hardware Engineers and Software Engineers: HW01: VLSI Design Engineer – PCI/SDRAM HW02: FPGA Design Engineer – SYNTHESIS HW03: VLSI Verification Engineer – Signal Processor SW01: Software Engineer – DEVELOPMENT TOOLS SW02: Software Engineer – X86 DRIVER & DIAGS SW03: Telecommunications Applications Engineer-DSP SW04: DSP Software Engineer Find specifics at http://www.bops.com/company_jobs.htm Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16913
Utku Ozcan wrote: > > > I don't use the SPO's of some DP RAM's on XC40150XV. > > > NGDBUILD and XNF2NGD give warnings. Do these warnings > > > imply a possibly bad routing architecture? Shall I > > > use the commands which ignore these pins? I have > > > used following command but the warnings didn't go away: > > > > > > NET "dp_ram_spo<*>" TIG=TS01; > > > > > > Shall this TS01 be defined for write clock of the Dual > > > Port RAM? Shall I use such a command to improve the > > > performance? > > > > > > Utku > > > > Which warning do you have? > > > > Michel Le Mer > > In the output file of NGDBUILD, chip.bld, following warnings: > > WARNING:basnu:113 - logical net "top_level_ram_table_un1_ram<13>" has no load > Its just a warning to let you know there are dangling nets in the design. It can safely be ignored. You'll get similar warnings anywhere you have unused counter outputs etc. These are presented so that you can see anything that was not supposed to be left unconnected > I am using Synplify and this net corresponds to the SPO output > of a Dual Port RAM. The SPO outputs of this Dual Port RAM are > not used. > > Do the unused pins of a macro consume FPGA resources? > No. > Are the unused pins of a macro taken into consideration in > Static Timing Analyzer TRACE? > No. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16914
FPGAs don't have analog elements, but there is no reason you can't use them in conjunction with external ADC's, DAC's, PLL's and RF components. The FPGA itself is a strictly digital circuit. wannarat wrote: > Hi > Can use FPGa with Analog circuit design (ADC , DAC )? > Or can i use circuit about RF with FPGA? > Please suggest me!!! > Xilinx can do that? > REgard. > Wannarat Suntiamorntut > E-mail : ksuwanna@kmitl.ac.th -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16915
The label bar (label sense) in viewlogic alters the signal name, so you'll lose connectivity if you change that. Be careful using the label bar in schematics for FPGAs, some of the tools don't like it. The pin sense on the symbol is just on the symbol, so you can go into the symbol editor and change that (select the pin(s) and type pse on the command line). Changing the pin sense will put a bubble on the pin without changing the connectivity to the underlying logic. Andy Peters wrote: > IPU wrote in message <7k7sgk$arb$1@black.news.nacamar.net>... > >Hi newsgroup, > >I have a simple (?) problem using VHDL and Viewlogic. After declaration of > >an entity I use VHDL2SYM.EXE to create a symbol for ViewDraw. It works > fine, > >but I want to have an active low signal (signalname with overline) in my > >schematic. > >I have no idea how to realize it in VHDL . Any suggestions? > > VHDL, being a text-only language, has no way of indicating that a signal is > active low. Some people like to create signal/variable names that indicate > that a signal is active low. I use _l (as in oe_l for an output enable). > > Since the language doesn't have any way to indicate active low, the symbol > generator utility won't be able to put bars over signals. Can you go in an > edit the symbol? (Probably not, at least without breaking connectivity.) > > -- a > ------------------------------------------ > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters@noao.edu > > NY Knicks in '99: > "Ya gotta believe!" -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16916
Try the atmel parts, they are functionally equivalent and are EEPROMS. Part numbers: AT17C65, AT17C128, AT17C256 Jason Garrick Kremesec wrote in message <376678FC.5CEA58AF@ews.uiuc.edu>... >Hello, > > This was brought up recently, but are there any erasable replacements >for the 8 pin dip Altera EPC1? I'm really looking for something that is >pin/function equivalent yet either electronically erasable or UV >erasable. > >Thank you for the help. > >Garrick Kremesec >University of Illinois >gkremese@ews.uiuc.eduArticle: 16917
Ooops! My apologies, Jerry. My brain was on the fritz and somehow I read AVHDL as "Altera VHDL", which I consider to be a "grape", as opposed to an "apple", or an "orange". I have not tried Active-VHDL, and cannot honestly offer any opinions, one way or another. I hereby retract my previous post regarding Leonardo vs Active-VHDL. Tools that supported recursive VHDL were something of a rarity up until this year, and I suspect that it will be a standard feature in VHDL tools from now on. John McCluskey Jaroslaw Kaczynski wrote: > Sandro, > > This issue has been addressed in Active-HDL 3.5 released June 1st - > please check with your distributor how you can upgrade. > BTW, John's suggestion to switch to Leonardo is of the 'comparing > apples to oranges' sort: Active-VHDL is design entry environment > with VHDL simulator, Leonardo is first of all synthesis tool... > > Thank you, > > Jerry > > Sandro Wefel <wefel@informatik.uni-halle.de> wrote in message > news:3767446A.2DC001A2@informatik.uni-halle.de... > > A problem occurs under Aldec Active VHDL 3.3 if I > > try to use recursive structures e.g. recursive architectures > > of an entity. The code in the appendix is from the > ....Article: 16918
So, does this require some hand edits to make a vital library compliant
which was generated from the ascii file used to create a synthesis library?
We are considering using the library compiler to make a vital library. Now,
what are the caveats to make
the library 'compliant' ?
i.e. The missing edge specifier in your example would seem to be a
short-fall of the tool which created the vital library... but is it? How
can a vendor be sure that the library does
not cause grief like the grief spoken about in this thread?
Thanks.
Jim
alex_schreiber@my-dejanews.com wrote in message
<7hukau$554$1@nnrp1.deja.com>...
>In article <37370ED0.12DDF8E5@usa.com>,
> asap <asapd@usa.com> wrote:
>> Hi all,
>>
>> I'm trying to do a post-synthesis
>> simulation with Modelsim EE 5.2,
>> using the VITAL lib of my ASIC vendor.
>> I keep getting errors that some instances
>> do not have one or two generics (e.g.: tpd_c_q_posedge).
>> (I do not have errors of missing instances...)
>> I don't think there is any error on the top instance
>> I apply the sdf file, nor similar things...
>> However, I don't know if i produce wrongly the sdf/vhdl files
>> from Synopsys DC v1999.05 (I use the SDF v2.1 format).
>> Is there any chance that the vendor ASIC VITAL models
>> are not 100% VITAL compatible, as mentioned on the
>> Modelsim user manual?
>>
>> Thanks,
>
>The story has two sides. For an ASIC library used inside Synopsys
>a Synopsys model needs to be described (.lib) which is compiled
>into a binary format (.db) by Library Compiler (lc) of Synopsys.
>Usually the ASIC vendor is already providing the .db format, so
>you as customer do not need to have the lc license and do not need
>to compile it yourself.
>
>In this Synopsys model there is a delay defined from the rising
>edge of 'c' to the output 'o' (for tpd_c_q_posedge). It looks
>like follows in the .lib model (often not delivered by the ASIC
>vendor):
>
> pin(q) {
> :
> timing() {
> timing_type : rising_edge;
> timing_sense : "non_unate";
> intrinsic_rise : 2.00;
> intrinsic_fall : 2.00;
> rise_resistance : 0.20;
> fall_resistance : 0.20;
> related_pin : "c";
> }
> }
>
>Based on this model the delay calculator in Synopsys DC
>is generating the SDF file. In your case you will find
>there an entry like
>
> IOPATH (posedge c) q (2.00:2.00:2.00)
>
>The second part are the VITAL models of your standard cell
>library. To be able to backannotate the values estimated
>by Synopsys delay calculator, the VITAL timing generics
>need to meet certain requirements. Only then the SDF
>backannotator in the Simulator (like ModelSim) can map the
>SDF entry with the VITAL generic correctly. In the assumed
>SDF entry given above the generic needs to be like follows:
>
> tpd_c_q_posedge
>
>If you have the VHDL/VITAL source code of your standard cell
>library (usually delivered by the ASIC vendor) you can check
>the defined timing generics of the cell which makes trouble.
>I guess, you will find either no definition or something like
>
> tpd_c_q
>
>The missing edge specifyer is enough to let the SDF backannotator
>failing.
>
>Have fun,
>
> Alex
>
>
>--== Sent via Deja.com http://www.deja.com/ ==--
>---Share what you know. Learn what you don't.---
Article: 16919John, I previously had success with recursive designs under synplicity 5.08 (for example a barrel shift normalizer). Now I'm trying to do a scaling adder tree under 5.1.4, but it no longer seems to be able to handle recursive calls. I don't know if you work at all with synplicity or if you've seen this. Synplicity's tech support so far has told me "In your code you have instantiated the 'addtree' within itself and this is causing the compiler to get confused. The size of 'inpa' depends on the parameters passed, and since it is recursively called the compiler does not evaluate it correctly ". The error generated is "Couldn't find binding for variable inpa_7"; inpa is a signal declared within the recursive routine. Hopefully they haven't done away with the ability to handle recursive calls! John McCluskey wrote: > Ooops! My apologies, Jerry. My brain was on the fritz and somehow I > read AVHDL as "Altera VHDL", which I consider to be a "grape", as > opposed to an "apple", or an "orange". > I have not tried Active-VHDL, and cannot honestly offer any opinions, > one way or another. > I hereby retract my previous post regarding Leonardo vs Active-VHDL. > > Tools that supported recursive VHDL were something of a rarity up until > this year, and I suspect that it will be a standard feature in VHDL > tools from now on. > > John McCluskey > > Jaroslaw Kaczynski wrote: > > > Sandro, > > > > This issue has been addressed in Active-HDL 3.5 released June 1st - > > please check with your distributor how you can upgrade. > > BTW, John's suggestion to switch to Leonardo is of the 'comparing > > apples to oranges' sort: Active-VHDL is design entry environment > > with VHDL simulator, Leonardo is first of all synthesis tool... > > > > Thank you, > > > > Jerry > > > > Sandro Wefel <wefel@informatik.uni-halle.de> wrote in message > > news:3767446A.2DC001A2@informatik.uni-halle.de... > > > A problem occurs under Aldec Active VHDL 3.3 if I > > > try to use recursive structures e.g. recursive architectures > > > of an entity. The code in the appendix is from the > > .... -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16920
This is a multi-part message in MIME format. --------------72197D4EEABA7EDEEA6F0FF4 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit The Virtual Workbench release had been delayed due to a delivery problem on BG352 Virtex FPGAs by Xilinx. The problem has been corrected according to our sources. We have been informed production of this virtex package is on schedule now. The VW-300 is being assembled this week. We are sorry for the delay. -- Best Regards, John Schewel, VP Marketing & Sales Virtual Computer Corp. --------------72197D4EEABA7EDEEA6F0FF4 Content-Type: text/x-vcard; charset=us-ascii; name="jas.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John Schewel Content-Disposition: attachment; filename="jas.vcf" begin:vcard n:Schewel;John x-mozilla-html:TRUE org:<img src="http://www.vcc.com/Images/VCCvCard.gif" alt="Virtual Computer" adr:;;6925 Canby Ave. #103;Reseda;CA;91335;USA version:2.1 email;internet:jas@vcc.com title:VP Marketing & Sales tel;fax:+1 (818) 342-0240 tel;work:+1 (818) 342-8294 x-mozilla-cpt:;0 fn:John Schewel end:vcard --------------72197D4EEABA7EDEEA6F0FF4--Article: 16921
Ray Andraka wrote: > FPGAs don't have analog elements, but there is no reason you can't use > them in conjunction with external ADC's, DAC's, PLL's and RF > components. The FPGA itself is a strictly digital circuit. There are some mixed mode FPGA's from the Fraunhofer Institute of Microelectronic Circuits and Systems Dresden Germany. They have an analog and digital core and also analog and digital ports. The problem: there aren't synthesis tools. A simulation tool for such AFPGAs was part of my diplom thesis and solved in conjunction with SPICE (not VHDL). To contact the FHG watch http://www.imsdd.fhg.de/ims-dd-e.html Regards Sandro WefelArticle: 16922
Rickman wrote: > ... > I believe there were a few posts listing lists of FPGA boards. Can > anyone repost them? List of boards and links to other lists: http://www.fernuni-hagen.de/IT/FPGA/boards.html Markus WannemacherArticle: 16923
Hi,
In fact the latest synopsys dc version has been enhanced for edge
relative timing and now most of the vital library are not compatible
with the new sdf generated by dc. In order to solve this problem end to
get a dc 98.08 like sdf you can set in your .synopsys_dc.setup a
variable call sdfout_no_edge to "true";
After that it should work as with the previous version
Best regards,
Eric.
jok wrote:
>
> So, does this require some hand edits to make a vital library compliant
> which was generated from the ascii file used to create a synthesis library?
> We are considering using the library compiler to make a vital library. Now,
> what are the caveats to make
> the library 'compliant' ?
> i.e. The missing edge specifier in your example would seem to be a
> short-fall of the tool which created the vital library... but is it? How
> can a vendor be sure that the library does
> not cause grief like the grief spoken about in this thread?
> Thanks.
>
> Jim
> alex_schreiber@my-dejanews.com wrote in message
> <7hukau$554$1@nnrp1.deja.com>...
> >In article <37370ED0.12DDF8E5@usa.com>,
> > asap <asapd@usa.com> wrote:
> >> Hi all,
> >>
> >> I'm trying to do a post-synthesis
> >> simulation with Modelsim EE 5.2,
> >> using the VITAL lib of my ASIC vendor.
> >> I keep getting errors that some instances
> >> do not have one or two generics (e.g.: tpd_c_q_posedge).
> >> (I do not have errors of missing instances...)
> >> I don't think there is any error on the top instance
> >> I apply the sdf file, nor similar things...
> >> However, I don't know if i produce wrongly the sdf/vhdl files
> >> from Synopsys DC v1999.05 (I use the SDF v2.1 format).
> >> Is there any chance that the vendor ASIC VITAL models
> >> are not 100% VITAL compatible, as mentioned on the
> >> Modelsim user manual?
> >>
> >> Thanks,
> >
> >The story has two sides. For an ASIC library used inside Synopsys
> >a Synopsys model needs to be described (.lib) which is compiled
> >into a binary format (.db) by Library Compiler (lc) of Synopsys.
> >Usually the ASIC vendor is already providing the .db format, so
> >you as customer do not need to have the lc license and do not need
> >to compile it yourself.
> >
> >In this Synopsys model there is a delay defined from the rising
> >edge of 'c' to the output 'o' (for tpd_c_q_posedge). It looks
> >like follows in the .lib model (often not delivered by the ASIC
> >vendor):
> >
> > pin(q) {
> > :
> > timing() {
> > timing_type : rising_edge;
> > timing_sense : "non_unate";
> > intrinsic_rise : 2.00;
> > intrinsic_fall : 2.00;
> > rise_resistance : 0.20;
> > fall_resistance : 0.20;
> > related_pin : "c";
> > }
> > }
> >
> >Based on this model the delay calculator in Synopsys DC
> >is generating the SDF file. In your case you will find
> >there an entry like
> >
> > IOPATH (posedge c) q (2.00:2.00:2.00)
> >
> >The second part are the VITAL models of your standard cell
> >library. To be able to backannotate the values estimated
> >by Synopsys delay calculator, the VITAL timing generics
> >need to meet certain requirements. Only then the SDF
> >backannotator in the Simulator (like ModelSim) can map the
> >SDF entry with the VITAL generic correctly. In the assumed
> >SDF entry given above the generic needs to be like follows:
> >
> > tpd_c_q_posedge
> >
> >If you have the VHDL/VITAL source code of your standard cell
> >library (usually delivered by the ASIC vendor) you can check
> >the defined timing generics of the cell which makes trouble.
> >I guess, you will find either no definition or something like
> >
> > tpd_c_q
> >
> >The missing edge specifyer is enough to let the SDF backannotator
> >failing.
> >
> >Have fun,
> >
> > Alex
> >
> >
> >--== Sent via Deja.com http://www.deja.com/ ==--
> >---Share what you know. Learn what you don't.---
Article: 16924Hi, I am repeating my post since no one had the answer last time. Does anyone know the die sizes of the xilinx XC4000 series FPGAs? I need them for a comparative study. Thanks, Eugene
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