Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi John, and Group...
I think that you may have noticed that the "researcher" feels that
recollections
of normal people are perfectly random ("no better than chance") and that he
also feels that the recollections of disturbed individuals is more random
than
perfectly random. I am not aware of a mathematical basis for such a
conjecture. On the other hand, if one interprets the statement as meaning
that recollections of normal people have a zero (0) correlation with fact,
then
one may conclude that the researcher is stating that disturbed people have
recollections that have a negative correlation with fact. However, a
negative
correlation is by no means random.
I hope that I haven't muddied the water too much, but I must note that it
was already pretty muddy.
Best Regards,
Frank Madison
John Larkin <jjlarkin@highlandSnipSniptechnology.com> wrote in message
news:9HVCOTo63PgB0cro4F19Bx=Ns5eX@4ax.com...
> In an article in sciencedaily, a researcher said...
>
> "If accurate memory of past events and relationships is no better than
> chance for normal, mentally healthy individuals, we might expect that
> the reports of past experiences by people who are currently medically
> ill, psychologically disturbed or otherwise compromised would be even
> less accurate."
>
> Could somebody good with math please explain this to me?
>
> John
>
Article: 23051Hi Please I have some questions about the Virtex family: 1. what is the difference between using BX,BY as the Source for Din and using one of the LUT inputs as a buffer to Din. "specially if this CLB is going to be used as part of register core" 2. How can I Route from YQ to XDin and vice versa. in order to implement a shift register. 3. How to use the LUT as shift reg. 4. If I want to design a generic shift-rotate register with selected size how can I route from the LSB CLB to MSB CLB using singles and hexes. I know that each single route only to its neighbors and hexes to the 6th clb Thanks in advance Jamil KhatibArticle: 23052
I just happen to have these nice and handy for ya:
A "free" core, raw and untested :
http://www.eej.ulst.ac.uk/tutor/m68000.html
(It's nice to loath over what its missing and
where...)
Two "real" Motorola 68000 cores with support
http://www.vlsi-concepts.com/V68000.html
VLSI Concepts phone (610-408-9121)
email hepler@vlsi-concepts.com
and also:
http://www.dcd.com.pl/english/d68000.htm
tel. (210) 677 0185
fax (210) 677 0635
e-mail:info-us@dcd.com.pl
--
JoeT also squattith amiga @ mind spring.com !
Amiga, BeOS, Linux, QNX, Windoze
So many mice: with so many meanings....
"Holger Azenhofer" <holger.azenhofer@vs.dasa.de>
wrote in message
news:8g35hv$sdu@newsserv.vs.dasa.de...
> Hi,
>
> I'm looking for a 68k - core in order to replace
an old 68000 design with an
> fpga.
> does someone know an 68k core and where to get
it.
> 68020 would be fine.
>
> thanks
>
> Holger
>
>
Article: 23053
You need to apply an attribute which defines the divsion factor: this
example will work for Foundation 2.1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY unisim; -- DLL component is in this library
USE unisim.vcomponents.ALL;
ENTITY dll_div IS
PORT (clkin : IN std_logic;
clkdv : OUT std_logic);
END ENTITY dll_div;
ARCHITECTURE structural OF dll_div IS
-- attributes to pass to DLL
ATTRIBUTE CLKDV_DIVIDE : string;
ATTRIBUTE CLKDV_DIVIDE OF dll : LABEL IS "8.0"; -- division value = 8
SIGNAL s_clkin, s_clk0, s_clkfb : std_logic;
BEGIN
clkpad : IBUFG port map (I=>clkin, O=>s_clkin);
dll : CLKDLL port map (CLKIN=>s_clkin, CLKFB=>s_clkfb, RST=open,
CLK0 =>s_clk0, CLK90=>open, CLK180=>open,
CLK270=>open,
CLK2X=>open, CLKDV=>clkdv, LOCKED=>open);
clkg : BUFG port map (I=>s_clk0, O=>s_clkfb);
END ARCHITECTURE structural;
Christophe Heyert <heyertc@rsd.bel.alcatel.be> wrote in message
news:3940AEC9.8073F9CC@rsd.bel.alcatel.be...
> Hi everybody,
>
> I was wondering if anyone has ever used the DLL's in the virtex FPGA.
> I can't find the solution of how to code a divider in VHDL.
> I have only found multiplications.
> Does someone ever tried this before, and if so, can you give an example
> Thanks
>
> Christophe
Article: 23054I'm not sure about FFT but xilinx.com has a lot of dsp type application notes. Also try some VHDL web sites. They usually have lots of code for all sorts of things. Hope this helps, good luck Bill Anthony Rowe wrote in message <8hrr9n$3p8$1@lure.pipex.net>... >Hello Folks > >I'm am wondering if any one knows any web based resources for implementing a >hardware based FFT processor on an fpga. and if they do could they point me >in the right direction. > >Thanks >Anthony > >Article: 23055
Could someone please explain to me how to perform a back annotated timing simulation using FPGA Advantage from Mentor , e.g. Renoir, Leonardo, Modelsim. Could you please take me through it from synthesis to simulation because I'm beginning to lose the will to live. thanks for any help, DaveArticle: 23056
Hi Laszlo... Not really possible without serious reverse engineering effort. It will be easier to approach the owner of the design. Why are you duplicating the device? Eric Pearson Cser Laszlo wrote in message <8hr0oo$bpe$1@goliat.eik.bme.hu>... >Hi, > >I own a programmed Actel A1225XL. I'd like to make copies of a programmed >device. Is it possible to read out the contents or duplicate one? > >Laszlo Cser > > > > > >Article: 23057
In article <39406C87.22F82D45@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > I guess the question is, what are you trying to accomplish by passing > the clock through the chip? Unless you are tying to compensate for an > asynchronous delay there is no reason to do this, You are forgetting the rule.... "Requirements change just after the board layout is done" We often do this where I work. The clock for something on the board comes from the FPGA, and we can use the FPGA to provide the input clock, a divided version of the clock, or even gate the clock for low-power modes. For flexibility, all nets lead to FPGA. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23058
In article <8hpmr9$62v$1@mawar.singnet.com.sg>, "Sherdyn" <sherdyn@yahoo.com> wrote: > I have a design problem right now concerning the state machine. I am using > synplicity and target to Altera Flex10K30E device. My problem is, if I were > to pull the state bits out to observe which state I am stuck at, then the > whole thing is running. But if I do not pull the state bits out, the circuit > just won't work at all. I am guessing it is timing problem but do not know > how to solve this. Can someone help? > > Sherdyn I don't have much to go on, but I'll give it a try. First thing- are you following the "ten commandments" of clean synchronous design? You know these hopefully: 1) Thou shalt have but one clock 2) Thou shalt use only one clock edge 3) Thou shalt synchronize signals coming into state machine from another clock domain... etc... Lastly Perhaps Synplicity/Max Plus are optimizing away some of your state bits but when you pull them to primary I/O's it prevents this? Using the "one-hot" approach or standard coding? Hope this help! Josh > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23059
Hey, I've finished a design which sim's good, but i constantly get an automation error when I try to impliment exiting with 80010104 as the exception code. Any ideas as to whats going on?Article: 23060
Not to start a religious war, but I am in the process of choosing between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design. Can someone post a message of what the advantages and disadvantage of their FPGA's are? e.g. cost, support, performance, ease of use, ... We will use Verilog, BTW. We are going to implement a video scaling application. thanks SW Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23061
Not to start a religious war, but I am in the process of choosing between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design. Can someone post a message of what the advantages and disadvantage of their FPGA's are? e.g. cost, support, performance, ease of use, ... We will use Verilog, BTW. We are going to implement a video scaling application. thanks SW Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23062
To do that you then need to bring the clock back into the chip on a clock pin. Then all of the external devices and the FPGA will be getting clocked by the same signal. There may be a way to source a clock that is synchronized to the internal clock, but I have not seen it. Some others have posted info for bringing the clock into a pin where it can be input to the DDL for synchonization. But I would rather bring it back in as a clock to use inside the chip. brian_boorman@my-deja.com wrote: > > In article <39406C87.22F82D45@yahoo.com>, > Rickman <spamgoeshere4@yahoo.com> wrote: > > I guess the question is, what are you trying to accomplish by passing > > the clock through the chip? Unless you are tying to compensate for an > > asynchronous delay there is no reason to do this, > > You are forgetting the rule.... "Requirements change just after the > board layout is done" > > We often do this where I work. The clock for something on the board > comes from the FPGA, and we can use the FPGA to provide the input clock, > a divided version of the clock, or even gate the clock for low-power > modes. For flexibility, all nets lead to FPGA. > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23063
I always seem to end up using Altera. My last project got forced into Altera because they had a larger device (at the time, flex 10K250 vs. Xilinx 125K gate part). This was a few years ago. You might try synthesizing to both types of devices with code fragments and see what types of percent utilization and speed you get. In the end, if both will work, it really doesn't matter. Good Luck! PJ In article <8i3knp$noq$1@nnrp1.deja.com>, swfpga@my-deja.com wrote: > Not to start a religious war, but I am in the process of choosing > between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design. > Can someone post a message of what the advantages and disadvantage of > their FPGA's are? e.g. cost, support, performance, ease of use, ... > We will use Verilog, BTW. > We are going to implement a video scaling application. > > thanks > > SW > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23064
There are specific advantages to each of the FPGA vendors, which I am sure, is what you are asking. But the list is long and it is a lot of work to sort it all out without knowing what you are mainly interested in. I don't know enough about video scaling to know specifically which features of the FPGAs would be of interest, but I think on most issues Xilinx and Altera are roughly equal. From some of the postings of Ray Andraka, it sounds like the Altera parts don't do quite as good a job of certain counters (up/down) and adders (add/sub). The Virtex also has quite a lot of RAM on board, especially with the latest versions of VirtexE. I think support and overall performance is roughly equal as well. But for the applications that I work in, cost is a significant factor. Here I think the new Xilinx Spartan II parts greatly excell over the other vendors. I believe you can get a 200K gate chip (which includes a fair amount of RAM in the gate count) for well under $30. Even in a 456 pin FPBGA the price is only $40. These prices will be coming down as they fully enter production later this year. BTW, does anyone have info from Xilinx yet on real production dates for the various parts? But if you need do get to production sooner than that, then you need to take a good look at both product lines. You might also want to look at the Lucent Orca parts. I am using them on my current board and they work well. They also give you more IO pins in a given package. When Xilinx went to Virtex, they really pumped up the number of power and ground pins. They seem to feel a greater need to ward off any potential ground bounce problems in the Virtex series than the previous lines. For example, a Virtex BGA 256 gives 180 IOs max, while an Orca part gives you up to 221 IO pins. swfpga@my-deja.com wrote: > > Not to start a religious war, but I am in the process of choosing > between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design. > Can someone post a message of what the advantages and disadvantage of > their FPGA's are? e.g. cost, support, performance, ease of use, ... > We will use Verilog, BTW. > We are going to implement a video scaling application. > > thanks > > SW > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23065
It all depends on many factors, not the least of which is you comfort level with the tools and architecture. For signal processing applications, the Xilinx architectures have a few considerable advantages in terms of how arithmetic functions are implemented and the ability to create very compact delay queues in the CLB select ram. These advantages can be a deciding factor in many designs, including video designs (It depends on your exact algorithm too). I've posted on the comparative advantages before, so a search in deja news is likely to turn up some additional detail. Altera FPGAs are generally less sensitive to placement than xilinx because of the internal routing architecture. This is good for limited performance/density designs, but can be a limiting factor in high speed and heavily arithmetic datapath designs. The tools ease of use is a religious preference for the most part. Xilinx tools provide more control over the design, but many claim the learning curve for a basic design is steeper (I don't see it though). swfpga@my-deja.com wrote: > Not to start a religious war, but I am in the process of choosing > between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design. > Can someone post a message of what the advantages and disadvantage of > their FPGA's are? e.g. cost, support, performance, ease of use, ... > We will use Verilog, BTW. > We are going to implement a video scaling application. > > thanks > > SW > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23066
Hi, While personaly I find altera to be more friendly there is at least one reason why to consider Xilinx and that is they have and altera don't (from what I heard Xilinx wrote on this patent, but I might be worng) a capability to change the LUT value during runing and this is very powerfull. have a nice day Illan In article <8i3o79$q22$1@nnrp1.deja.com>, phil_jackson@my-deja.com wrote: > I always seem to end up using Altera. My last project got forced into > Altera because they had a larger device (at the time, flex 10K250 vs. > Xilinx 125K gate part). This was a few years ago. > > You might try synthesizing to both types of devices with code fragments > and see what types of percent utilization and speed you get. > > In the end, if both will work, it really doesn't matter. > > Good Luck! > PJ > > In article <8i3knp$noq$1@nnrp1.deja.com>, > swfpga@my-deja.com wrote: > > Not to start a religious war, but I am in the process of choosing > > between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design. > > Can someone post a message of what the advantages and disadvantage of > > their FPGA's are? e.g. cost, support, performance, ease of use, ... > > We will use Verilog, BTW. > > We are going to implement a video scaling application. > > > > thanks > > > > SW > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23067
On Mon, 12 Jun 2000 18:31:09 -0400, Rickman <spamgoeshere4@yahoo.com> wrote: [some good comparison stuff deleted] >But if you need do get to production sooner than that, then you need to >take a good look at both product lines. You might also want to look at >the Lucent Orca parts. I am using them on my current board and they work >well. They also give you more IO pins in a given package. When Xilinx >went to Virtex, they really pumped up the number of power and ground >pins. They seem to feel a greater need to ward off any potential ground >bounce problems in the Virtex series than the previous lines. For >example, a Virtex BGA 256 gives 180 IOs max, while an Orca part gives >you up to 221 IO pins. I have to give Xilinx points for having the guts to do this. No chip marketeer worth his name wants to give up I/O pins for power/ground pins, but good engineering demands it. Unless, of course, Lucent did something super-sophisticated to reduce ground bounce on their chips (*real* risetime control, for example), in which case I tip my hat to them. Take care, Bob Perlman > > >swfpga@my-deja.com wrote: >> >> Not to start a religious war, but I am in the process of choosing >> between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design. >> Can someone post a message of what the advantages and disadvantage of >> their FPGA's are? e.g. cost, support, performance, ease of use, ... >> We will use Verilog, BTW. >> We are going to implement a video scaling application. >> >> thanks >> >> SW >> >> Sent via Deja.com http://www.deja.com/ >> Before you buy. ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 23068
This is a multi-part message in MIME format. --------------F7AE4CFA8A02540532EAEC8E Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Search on the support.xilinx.com site for that error code. There are a number of fixes for it. I assume you have already installed the patch that cures many of the ills in F1.5? If not, that would be the first thing to try. Seiya wrote: > Hey, I've finished a design which sim's good, but i constantly get an > automation error when I try to impliment exiting with 80010104 > as the exception code. Any ideas as to whats going on? -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 || --------------F7AE4CFA8A02540532EAEC8E Content-Type: text/x-vcard; charset=us-ascii; name="devb.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Dave Vanden Bout Content-Disposition: attachment; filename="devb.vcf" begin:vcard n:Vanden Bout;Dave tel;fax:(919) 387-1302 tel;work:(919) 387-0076 x-mozilla-html:FALSE url:http://www.xess.com org:XESS Corp. adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA version:2.1 email;internet:devb@xess.com title:FPGA Product Manager x-mozilla-cpt:;-16464 fn:Dave Vanden Bout end:vcard --------------F7AE4CFA8A02540532EAEC8E--Article: 23069
If you already understand the basic functionality of the DLL, you only need to understand one important constraint: The internally distributed global clock cannot drive any output pad. Thus, you can use a DLL to make one output coincident with the incoming clock. You can also use a DLL to make the internally distributed clock coincident with the incoming clock. But you cannot use one DLL to do both these delay adjustments simultaneously. If you use the DLL to make the output pin coincident with the incoming clock, you can actually make this DLL also drive the internal global clock, but you have lost all control of the relative timing between the internal clock and the clock input/output pin. Depending on relative internal routing delays, either of these two signals can be early or late. So, if you need to control both, use two DLLs. I think this subject was discussed a while ago. Peter Alfke ============================================ Rickman wrote: > To do that you then need to bring the clock back into the chip on a > clock pin. Then all of the external devices and the FPGA will be getting > clocked by the same signal. > > There may be a way to source a clock that is synchronized to the > internal clock, but I have not seen it. Some others have posted info for > bringing the clock into a pin where it can be input to the DDL for > synchonization. But I would rather bring it back in as a clock to use > inside the chip. > > > brian_boorman@my-deja.com wrote: > > > > In article <39406C87.22F82D45@yahoo.com>, > > Rickman <spamgoeshere4@yahoo.com> wrote: > > > I guess the question is, what are you trying to accomplish by passing > > > the clock through the chip? Unless you are tying to compensate for an > > > asynchronous delay there is no reason to do this, > > > > You are forgetting the rule.... "Requirements change just after the > > board layout is done" > > > > We often do this where I work. The clock for something on the board > > comes from the FPGA, and we can use the FPGA to provide the input clock, > > a divided version of the clock, or even gate the clock for low-power > > modes. For flexibility, all nets lead to FPGA. > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 23070
Ah, that marketing gates thing works every time. The fit really depends on the design that's going in. I have several examples of designs that choked a 10K250 but were comfortable fits in a 40125 and could probably even have gone into a 4085. If you've go alot of arithmetic or small delay queues like you usually find in DSP applications, the design density in Altera is less than half of that of Xilinx if you go by the marketing gate counts. Consider: 1) Arithmetic carry chain operation in the Altera 10K devices reduces the 4 LUT to a pair of 3-LUTs, one of which is used for the carry function and one for the 'sum' function. That means you are limited to a 2 input arithmetic function if you keep the logic to one level. That rules out accumulators which need a load or a clear, adder-subtracters and other functions. On top of that, if you use the clock enable, it steals an input from the LUT leaving you with a 1 input arithmetic function. Now, last time I checked, there just weren't a whole lot of useful one input arithmetic functions. The APEX parts improve this situation slightly by providing a separate dedicated clock enable and a direct clear to the flip-flop 2) The Xilinx arrays (both virtex and 4000) allow you to use the LUT as a 16x1 memory, which can also be used as a 16 bit shift register. This makes for a dandy little delay queue, handy for all those pesky filter problems that seem to crop up in signal processing. In Altera 10K and Apex, you need to use an LE per bit per clock delay for these delay queues. For filter applications, you can easily chew up half the chip just in very expensive delay queues. 3) Altera routing is a somewhat global architecture, which makes placement less critical but also tends to be slower than what you could do with shorter interconnect. There is only enough row routing in the ALtera row to connect to about 3/4 the LE's in the row. This is fine for state machines and random logic, as the interconnect within the LABs is used extensively by those to reduce the LAB to LAB routing. In an arithmetic design, there is little or no routing within the LAB, because the carry chain runs across the LAB so that all the LE's in a LAB are used at the same point in your data path. As a result, a much higher percentage of the routing is forced onto the row routes. In data path designs, you can realistically only use about half of the LE's in the chip because the routing becomes congested long before you run out of logic. phil_jackson@my-deja.com wrote: > I always seem to end up using Altera. My last project got forced into > Altera because they had a larger device (at the time, flex 10K250 vs. > Xilinx 125K gate part). This was a few years ago. > > You might try synthesizing to both types of devices with code fragments > and see what types of percent utilization and speed you get. > > In the end, if both will work, it really doesn't matter. > > Good Luck! > PJ > > In article <8i3knp$noq$1@nnrp1.deja.com>, > swfpga@my-deja.com wrote: > > Not to start a religious war, but I am in the process of choosing > > between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design. > > Can someone post a message of what the advantages and disadvantage of > > their FPGA's are? e.g. cost, support, performance, ease of use, ... > > We will use Verilog, BTW. > > We are going to implement a video scaling application. > > > > thanks > > > > SW > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23071
Rickman wrote: > There are specific advantages to each of the FPGA vendors, which I am > sure, is what you are asking. But the list is long and it is a lot of > work to sort it all out without knowing what you are mainly interested > in. > > I don't know enough about video scaling to know specifically which > features of the FPGAs would be of interest, but I think on most issues > Xilinx and Altera are roughly equal. From some of the postings of Ray > Andraka, it sounds like the Altera parts don't do quite as good a job of > certain counters (up/down) and adders (add/sub). The Virtex also has > quite a lot of RAM on board, especially with the latest versions of > VirtexE. In defense of Altera, they do implement counters reasonably well, as they have special modes for the LUTs just for updown and loadable counters. It is not the counters where Altera falls down. Also, the Altera parts do have a sizable amount of 'block' RAM on chip. For a while they were the only ones with block RAM. The lack of an ability to create a large number of very small RAMs hurts in DSP applications (usually in video processing too) enough to make Xilinx a significantly better choice. You will have to floorplan to get best performance out of Xilinx, but that can get you quite a gain. Altera doesn't really benefit much if at all from floorplanning, partly because of the cross-chip interconnect and partly because the interconnect switch connections are not easily found to make sure your placement isn't forcing multiple level connections. > > > I think support and overall performance is roughly equal as well. > Altera performance has a significant droop as you go to bigger devices in the same family. This is because the routing gets longer with more capacitive loading, so max clocks drop off. You'll see a similar drop-off in XIlinx if you don't floorplan, but if you do the Xilinx can outperform an Altera chip of similar vintage and size by a factor of 2:1 or more in DSP applications. This is not true for random logic where Altera can take advantage of the intra-LAB connections which are very fast. > > But for the applications that I work in, cost is a significant factor. > Here I think the new Xilinx Spartan II parts greatly excell over the > other vendors. I believe you can get a 200K gate chip (which includes a > fair amount of RAM in the gate count) for well under $30. Even in a 456 > pin FPBGA the price is only $40. These prices will be coming down as > they fully enter production later this year. BTW, does anyone have info > from Xilinx yet on real production dates for the various parts? > > But if you need do get to production sooner than that, then you need to > take a good look at both product lines. You might also want to look at > the Lucent Orca parts. I am using them on my current board and they work > well. They also give you more IO pins in a given package. When Xilinx > went to Virtex, they really pumped up the number of power and ground > pins. They seem to feel a greater need to ward off any potential ground > bounce problems in the Virtex series than the previous lines. For > example, a Virtex BGA 256 gives 180 IOs max, while an Orca part gives > you up to 221 IO pins. > > swfpga@my-deja.com wrote: > > > > Not to start a religious war, but I am in the process of choosing > > between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design. > > Can someone post a message of what the advantages and disadvantage of > > their FPGA's are? e.g. cost, support, performance, ease of use, ... > > We will use Verilog, BTW. > > We are going to implement a video scaling application. > > > > thanks > > > > SW > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23072
Hi all, Does anyone know why the pad report from par for a XCV300 design includes pins TRDY and IRDY ? These pins are not found in my VHDL source. They are only briefly mentioned in the Virtex-E datasheet (and not described), but not at all in the Virtex datasheet. Does this indicate that there is something that I'm inadvertently activating that calls for these pins? Thanks, Dave BrownArticle: 23073
[posted and mailed] I want to deploy a very simple JTAG in-circuit programmer for the Altera MAX 7128A in my production department. The Windows version available for free download from Altera's site (Altera Stand-Alone Programmer, http://www.altera.com/html/tools/asap2.html) looks too fancy for simple blasting of a fixed file. I'd like my production people to be able to simply click on a shortcut and have a canned file pumped into the chips on my board. Is anything available to do this? Can I customize the Altera program to do this? I don't want to open the program to allow the user choice of file to blast.Article: 23074
swfpga@my-deja.com wrote: > > Can someone post a message of what the advantages and disadvantage of > their FPGA's are? e.g. cost, support, performance, ease of use, ... > We will use Verilog, BTW. > We are going to implement a video scaling application. > You will find Altera's development tools second to none. They are excellent. The NEW system is a memory and resource hog. They do still support the old software for now. Altera provides excellent documentation and training. Altera is, however, expensive. -- This is my signature file. Do you like it? Sent via Deja.com http://www.deja.com/ Before you buy.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z