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Perhaps this is the time to use syn_keeps? I end up with excessive use of this directive to get my
hdl to instantiate "well." Specifically, Synplify tends to play with synchronous sets and resets
because I don't specify an asynchronous reset on my registers.
I have a few state machines where I use a combinatorial always block
reg [3:0] n_state_vec /* synthesis syn_keep=1 */;
reg [5:0] n_iobreg /* synthesis syn_keep=1 */;
reg [3:0] state_vec;
reg [5:0] iobreg;
always @(state_vec or some_condition_or_other or new_state or _new_value)
case (state_vec)
...
some_state: begin
if (some_condition_or_other) begin
n_state_vec <= new_state;
n_iobreg <= new_value;
end
end
...
endcase
always @(posedge clk) state_vec <= n_state_vec;
always @(posedge clk) iobreg <= n_new_value;
This is a bit excessive but sometimes necessary to get my states to integrate well with each other
and to keep from getting other wierd results.
- John
Rick Filipkiewicz wrote:
> Rotem Gazit wrote:
>
> > Rick,
> > Try putting the directive :
> > /* synthesis syn_useioff=1 syn_srlstyle = "registers" */
> > In your module declaration.
> > If you don't have internal feedbacks from your output signals that
> > should do the trick for you.
> > Note that Synplicity tends to merge duplicated registers (use syn_keep
> > on these signals to prevent this) and convert sequential register to
> > SRL16.
> >
> > Cheers,
> >
>
> Rotem & Ray A.
>
> The problem I'm finding is not in the explicit, standalone, FFs that I want to get into IOBs or,
> to put it another way, where I have to avoid feedback from an output reg. My "standard" Verlilog
> state machine style is a single registered case statement with both state transitions and outputs
> defined in it e.g.
>
> always @(posedge clk)
> case (state_vec)
> ...
> some_state: begin
> if (some_condition_or_other) begin
> state_vec <= new_state;
> iobreg <= new_value;
> end
> end
> ...
> endcase
>
> where ``iobreg'' is supposed to end up in an IOB. What the Synplify optimiser does, sometimes, is
> to generate logic for ``iobreg'' that uses feedback from itself. In the two cases I'm fighting
> right now the state mach is 2 levels down in the hierarchy. What Syn support told me to do is to
> separate out the IOB registers into a separate always block. I really dislike that design style
> since its much more awkward to document and it fails what I call the ``visibility'' test of HDL
> code i.e. can you see at a glance that its right.
>
> The second place where Synplify can implicitly break the IOB packing rules relates to the common
> init condition for bidirs which are registered in both directions. Even if you have not defined a
> sync reset on a FF Synplify might generate one for you! If, after logic reduction, the input
> equation for an output FF can be made to look something like
>
> !foo & bar
>
> then Syn may put foo on the sync reset pin and bar on the D. This is the issue that I first
> brought to Synplicity's attention 2 years ago. They didn't seem to understand what I was talking
> about and I ended up kludging my way around it by putting fake async resets on the FFs.
>
> In both these cases syn_useioff could easily be used to tell the optimiser/mapper not to:
>
> (1) use feedback.
>
> (2) generate implicit sync set/reset. Only allow ones that are explicitly defined at the HDL
> source level.
Article: 32426Michael, my advice, if you want to learn about FPGAs and VHDL, take those XC2000 parts and throw them in the garbage can. Just like you would do with an intel 286 processor of similar vintage No software, no support, ancient features, slow as molasses.... Yes they work, but for little money you can aget a Spartan or Spartan XLpart ( XC4000 generation ), or, better yet, get Spartan-II or Virtex-E, two families that are mature, but halfway modern. My analogy is that one year of FPGA evolution equals 20 years of human aging. And the XC2018 is 15 years old, that makes it a 300 year old very senior citizen. Definitely retirement age. Peter Alfke ======================== Michael Stevens wrote: > Do you know if they have published anything regarding the ancient xc2000 series? > > I recently picked up a bunch of recycled xc2018's figuring I'd learn some VHDL > and > get some home projects on the go. Finding S/W to do P&A and to generate the > configuration > bitstream seems to be difficult as the current batch of free tools do not > support these > discontinued devices. > > Cheers, > MichaelArticle: 32427
Hey, whats up with all the gurus here?? Are all on vacations? Please, give me just a little comment about this. -- MFG FalkArticle: 32429
"Gary Meakin" <gmeakin@compd.com> wrote in message news:ee712db.-1@WebX.sUN8CHnE... > I am using a Xilinx Spartan XCS40 (PQ208) FPGA running at 40MHz. > > I am having problems with running a nubus interface design on this FPGA with the power rails approaching 5.00v. If the power rails are dropped to 4.80v then the design works. > > When the voltage rail is slowly increased from 4.80v upto 5.00v parts of the design will stop working. If you reset the FPGA it sometimes starts working but will quickly stop functioning. I believe the timing in the FPGA is changing with the increased voltage on the rails but I cannot see why it is causing serious problems that I am experiencing. > > Has anyone come across a similar problem or knows what might be going wrong with the FPGA when the power rail is increased? > One more simple thing to double-check: if your clock(s) are coming from the same 5V source, very carefully check the overshoot and undershoot. This will affect the protection diodes when you're approaching 5V. In one of my designs the Spartan was extremely sensitive to clocking anomolies and once the clock was properly terminated (NO under or overshoot) it worked fine. Other internal setup/hold errors are quite possible, but if you're not pushing the envelope with clock speed (< 50 MHz), this is worth checking. If you have a good scope, this is an easy thing to check and correct before digging into the guts of your design. Good luck Jeff -- *********************************************** Jeffrey Vallier Sr. FW Engineer Gibson Guitar Corp. GMICS Division 1283 F Old Mtn View/Alviso Rd. Sunnyvale, CA 94089 408 734 4394 ***********************************************Article: 32430
Kolja, let's not get carried away. Xilinx has no intentions whatsoever to sue any user of Xilinx devices for having used any of these "systems-related" patents. Why we patent such things is a long, complicated, and even controversial story. But reality is that patents can make or break a company. Fairchild survived for years on the royalties from the planar patent, Kodak had to give up instant photography, when it was found violating a Polaroid patent. Philips has a tendency to patent anything in sight. But they have also had smart ideas, like audio and video cassettes and the CD... Closer to home, we have a 7-year long fight with Altera over some basic FPGA patents. In the case you cited, we somehow must have convinced the patent examiner that this use of LUTs etc. was novel and not obvious. But any Xilinx user has an automatic license to use this patent. Hopefully very often! :-) Peter Alfke Kolja Sulimma wrote: > I just stumbled over a stupid Xilinx patent describing how to builld an > 8 input AND function in a single slice. > It was filed in August 1999. > http://www.delphion.com/details?pn=US06201410__ > > I know that I used structures like this years ago. > Jan Gray wrote some messages about this but I could not find any posting > that are old enough. > > Anyone published this before August 1999? > > I wonder what kind of licence fee xilinx has in mind. Or maybe they do > not license it at all? > What happens if synthesis implements this structure by chance? Remember > that you can map the mux that is described in the patent into a XC4K > H-LUT !!!! > So Xilinx patented two of the "some 9-input functions" that can be > implemented in a single XC4K CLB. There are only a few hundred left, > maybe I should patent some of them. Then I will license the 9-input > XOR for 1 cent per CLB. > > Kolja SulimmaArticle: 32431
You are pointing to the unisims source, not to a compiled library. You need to compile the unisim library with modelsim, and then the token should point to the compiled library. CHeck the answers data base on the xilinx website. There are instructions there on how to compile the library, as well as tcl scripts to do it. JianYong Niu wrote: > Hi, All: > > I am using Xilinx System Generator to design an application in Matlab > simulink evironment. I use ModelSim starter version to simulate the design. > > Problems occured while the vcom.do file was excecuted: > > I have changed the %XILINX% token in the vcom.do file into the xilinx path > in my computer. errors occured as follows: > > # ERROR: C:/XILINX/vhdl/src/unisims is not a valid library: no info file. > # ERROR: C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(14): > Library unisim not found. > # ERROR: C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(15): > Unknown identifier: unisim > # ERROR: C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(17): > VHDL Compiler exiting > > what is the info file? > > I find a info file from my matlab work directory, and copied it into the > xilinx unisims path. then the following errors occured when I run modelsim: > > ERROR: Could not find C:/XILINX/vhdl/src/unisims.vcomponents > # ERROR: C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(15): > cannot find expanded name: unisim.vcomponents > # ERROR: C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(15): > Unknown field: vcomponents. > # ERROR: C:/MATLABR11/toolbox/xilinx/sysgen/vhdl/synth_reg_w_init.vhd(17): > VHDL Compiler exiting > # ERROR: C:/Modeltech_xe/win32xoem/vcom failed. > > However, I do find a file 'unisims.vcomp' in the directory. what is the > problem? > > thanks. > > Jianyong -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 32432
Yes we use the select map port. We can change the both the Block Ram and any LUT. We can readback the state of all the flop too. This is done with a tool we developed. The FPGA Browser converts the .ncd file to a xdl (xilinx design language) file. There is a little known command (xdl or xdl.exe) that translates the .ncd binary format to a fully ASCII format. This command will also give you generic information about all the Xilinx devices. It shows you where all the tiles are on the device as well as all the interconnect (pips and switches) information. I'm pretty sure all the information to reverse the bit stream is extracted by the xdl command (it will produce files over 100 MBytes). This really makes it easy to write tools. So since we are power users we developed a tool for power users. We developed a download cable that uses active buffers and connects to the PCI bus. Steve Casselman, CEO Virtual Computer Corporation <hamish@cloud.net.au> wrote in message news:bA0_6.256$A5.1081@news1.eburwd1.vic.optushome.com.au... > Steve Casselman <sc@vcc.com> wrote: > > constant just the data content of the ram is changed). We just showed this > > at live at DAC where we were the only company doing partial reconfiguration. > > Is that partial reconfiguration using the actual features in the tools/chips > though? Or did you just change the block RAM contents the regular way? > > > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au> >Article: 32433
I see... I was wondering what the differance between Macros and Primitives were,
and now I know.. This helps a lot. For the sake of completeness (and at the risk of
beating a dead horse) I would like to explore many of these various options
(compiled edif, xc_map, using only primitives, etc..) so I can decide which is best
for us, and which results in the most readable designs. I dont see why there would
be any qualitative differance int he resulting bitstreams, so I assume this is all
about readibility and portability of the vhdl?
I am unable to locate the macros themselves. Meaning that the string "M2_1B2" does
not seem to show up anywhere in any of the vhdl files that came with the foundation
tools... I assume it exists somwhere, otherwise it would be silly to inlude it in
the library guide descriptions. =) Any succestions of which rock to overturn to
find these?
I am right in thinking that if I just include whatever vhdl file defines this macro,
that it will be expanded in synplify (or modelsim), and my design edif will then
contain the primitive(s) from which this unit is built, and the foundation tools
will then be able to synthesize it?
--
_____ _____
___ | | __ |
|___| | --| -|
|_____|__|__|
Article: 32434> Xilinx has no intentions whatsoever to sue any user of Xilinx devices for having > used any of these "systems-related" patents. I don't know if it would stand up even if you did, for a number of reasons...one of them being this is a technique I know I've used for as long as I can remember...certainly prior to the filing date in 1999! > Why we patent such things is a long, complicated, and even controversial story. > But reality is that patents can make or break a company. Not patents like this! > Fairchild survived for years on the royalties from the planar patent, > Kodak had to give up instant photography, when it was found violating a Polaroid > patent. Entirely different stories... > Philips has a tendency to patent anything in sight. And Intel, and er, well, Xilinx ;-) > In the case you cited, we somehow must have convinced the patent examiner that > this use of LUTs etc. was novel and not obvious. Xilinx convinced the patent examiner that if was novel and not obvious to HIM (or HER). Unfortunately, the patent examiners for electronics are NOT very good. For fishing lures, they are top notch...but no EE who is worth their salt is going to work for the patent office at $60k/year, when they can be working in industry and making at least 2x that. Keep that in mind.Article: 32435
I just stumbled over a stupid Xilinx patent describing how to builld an 8 input AND function in a single slice. It was filed in August 1999. http://www.delphion.com/details?pn=US06201410__ I know that I used structures like this years ago. Jan Gray wrote some messages about this but I could not find any posting that are old enough. Anyone published this before August 1999? I wonder what kind of licence fee xilinx has in mind. Or maybe they do not license it at all? What happens if synthesis implements this structure by chance? Remember that you can map the mux that is described in the patent into a XC4K H-LUT !!!! So Xilinx patented two of the "some 9-input functions" that can be implemented in a single XC4K CLB. There are only a few hundred left, maybe I should patent some of them. Then I will license the 9-input XOR for 1 cent per CLB. Kolja SulimmaArticle: 32436
I will not argue the validity of a specific patent, nor the general reasons for patenting, nor the quality of patent examiners. But I do maintain that no Xilinx user should be intimidated or feel restrained by this patent. Don't even be upset. If you want to, be amused. That's all. Peter Alfke ================================ Austin Franklin wrote: > > Xilinx has no intentions whatsoever to sue any user of Xilinx devices for > having > > used any of these "systems-related" patents. > > I don't know if it would stand up even if you did, for a number of > reasons...one of them being this is a technique I know I've used for as long > as I can remember...certainly prior to the filing date in 1999! > > > Why we patent such things is a long, complicated, and even controversial > story. > > But reality is that patents can make or break a company. > > Not patents like this! > > > Fairchild survived for years on the royalties from the planar patent, > > Kodak had to give up instant photography, when it was found violating a > Polaroid > > patent. > > Entirely different stories... > > > Philips has a tendency to patent anything in sight. > > And Intel, and er, well, Xilinx ;-) > > > In the case you cited, we somehow must have convinced the patent examiner > that > > this use of LUTs etc. was novel and not obvious. > > Xilinx convinced the patent examiner that if was novel and not obvious to > HIM (or HER). Unfortunately, the patent examiners for electronics are NOT > very good. For fishing lures, they are top notch...but no EE who is worth > their salt is going to work for the patent office at $60k/year, when they > can be working in industry and making at least 2x that. Keep that in mind.Article: 32437
Peter Alfke wrote: > Kolja, let's not get carried away. I just do not like the patent law, thats all. > Xilinx has no intentions whatsoever to sue any user of Xilinx devices for having > used any of these "systems-related" patents. Thats probably right. Unisiys had no intention to sue anyone about their compression patents for almost 20 years. Than they announced to sue everyone who has a GIF on his web site. Later they limited it to a couple of hundred software companies... AFAIK it is illegal for me to use this technique without permission from Xilinx. That's true even if the patent does not hold, because I am require to challenge any patent that I believe to be unjustified orior to using it. > Why we patent such things is a long, complicated, and even controversial story. > But reality is that patents can make or break a company. Or break other companies... To protect yourself from other peoples patent claims it is enough to publish any idea that you have. > Closer to home, we have a 7-year long fight with Altera over some basic FPGA > patents. Thats right. Xilinx patented the great idea of having two routing networks, one general and one special for short connections. Because this idea had been implemented a thousand times before (for example in automata designed by John v. Neumann in the 60's) they based the patent on the novel idea that these networks have no connectino whatsoever.. (all the other Implementations had at least one conenctions between those resources) On the ground of this missing connection Xilinx now tries to prevent the import of essentially all Altera products into the US. That's not what I call nice behaviour. You should try to build your success on superior products instead. Be honest: In the unlikely case that you succeed in banning altera from the US, your research budget would be cut. And Xilinx would become the Microsoft of the FPGA world. > In the case you cited, we somehow must have convinced the patent examiner that > this use of LUTs etc. was novel and not obvious. > But any Xilinx user has an automatic license to use this patent. Hopefully very > often! :-) Where is this fact published? I twenty years, when my IP core sold 10 Million times and Xilinx has become a huge dinosaur because they bet their money on FPGAs alone and ignored the new 3-D quantum logic trend and decides to behave like Unisys or Rambus, then I am going to need more then a newgroup posting... Suggestion: The Delphion Patent Database allows to enter licensing information for any patent. Why don't you add a note to these patents, that the use of it is free? Kolja Sulimma P.S.: The following patent (filed 2/2000) describes exactly one of the main feature of the BRASS HSRA FPGA design that I worked on at UC Berkeley in 1997: Published 1/99 at the FPGA symposium. BRASS uses many pages instead of 2, but otherwise it is the same. http://www.delphion.com/details?pn=US06150839__Article: 32438
I'm working on a differential qpsk encoding and decoding system. I can manage the portions for symbol encoding/decoding, fifo, cpu interface. However, I am confused on the front end portions of the receiver, namely the mixing/multiplying, filtering, and symbol detection of the received digitized baseband rf data. The receiver is digitized the rf signal with a 4x clock. There will be four data samples per symbol for each of I and Q. The previous symbol is mutliplied with the current symbol for differential detection. But how do I determine the boundaries of the received symbols ? I could be using the last data sample of the previous symbol and the first three data samples of the current symbol and incorrectly treat the four as one single symbol. With four data samples per symbol for each of I and Q, how can I level detect the decision ? Which three samples shall I discard ? Thanks.Article: 32440
Peter Alfke <peter.alfke@xilinx.com> writes: >I will not argue the validity of a specific patent, nor the >general reasons for patenting, nor the quality of patent examiners. >But I do maintain that no Xilinx user should be intimidated or >feel restrained by this patent. >Don't even be upset. If you want to, be amused. Everyone in the binary logic business learns quickly that XOR has the property that if applied twice restores the original value. Yet someone has a patent on using XOR on a bit-mapped display, with the property of being able to erase by XORint again. It was twice challenged and twice upheld. Now, as XOR is a fundamental logical operation, I feel badly toward a company that would try to patent it. I don't know the details of the Xilinx patent, but it does sound more than amusing to me. -- glenArticle: 32441
Not an answer, but something to research: digital Costas loops. I've seen I/Q demodulators that use costas loops for symbol tracking. I never got too far into it, just enough to know that the nastier qam systems require something extreme to track properly. It may be too involved for qpsk, but could provide insight and a deeper understanding of the RF techniques. Edward wrote: > I'm working on a differential qpsk encoding and decoding system. I > can manage the portions for symbol encoding/decoding, fifo, cpu > interface. However, I am confused on the front end portions of the > receiver, namely the mixing/multiplying, filtering, and symbol > detection of the received digitized baseband rf data. > > The receiver is digitized the rf signal with a 4x clock. There will > be four data samples per symbol for each of I and Q. The previous > symbol is mutliplied with the current symbol for differential > detection. But how do I determine the boundaries of the received > symbols ? I could be using the last data sample of the previous > symbol and the first three data samples of the current symbol and > incorrectly treat the four as one single symbol. With four data > samples per symbol for each of I and Q, how can I level detect the > decision ? Which three samples shall I discard ? > > Thanks.Article: 32442
> Don't even be upset. If you want to, be amused. I am amused, but also annoyed. Patents like this, are the bane of my existence at times, being that I do patent work.Article: 32443
Being a Fan of Peter I don't wish to upset him... but these are my views... Currently I see the two big guns of the FPGA world finding ways to block or out do each other just to gain some ground. I don't see how this can realy benifit us the engineers!? It would however be nice if these idears were published so that everyone can take advantage for the benifit of the design. Putting a Paten on the way a gate is implumented is like having a paten on a type of nut and blot! these are the things we build with to make our designs. If someone wishes to paten somthing then paten a PCI funtion block that will do 66Mhz/64Bits in under 100 gates!!! In other words paten something that is a major break though for the industre and not the way a gate is implumented. Question: If I do this in a Altera chip - Do I have to pay Xilinx? I never liked Microsoft - but we were all puched into it - I hope Altera and Xilinx continue to give us a choise as a monoply firm like Microsoft will come under the microscope and have the finger pointed at *it* for not suppling what *we* the designers want! I think compines should remember that it is us and our pennys that put them up at the top and things like this just make them look greedy and give a bad impresstion to its users. Regards Cyber_Spook_ManArticle: 32444
> The xilinx > mapper will push the FF's to the IOBs if you set the IOB FF's option > appropriately provided the rules are met for the IOB FFs. That's what I do. It is the "pr -b" option to map: map -pr b filenameArticle: 32445
Article: 32446
Gary, It may also be a signal integrity problem. Ground bounce causing double clocking, bad input value, etc. This is obvious if you lower supply and it gets better, raise temperature and it gets better, or find out you have 1+ volts of overshoot and undershoot and add virtual ground pins (drive unused IO's to a '0' with the strongest IO output type and ground them externally, creating more ground pins and less ground inductance) and the problem also goes away. I have solved 5+ pcb SI design issues with this trick to date that I know of. To those listening in (and I am not accusing Gary of such a thing): Please simulate your IO's with IBIS models and the pcb circuit extraction from layout before you build your boards --- it saves so much time later. Sometimes you have to deal with poor SI (PCI is a good example of a nightmare compromise). In these cases, the virtual ground is a life saver. Austin Gary Meakin wrote: > I am using a Xilinx Spartan XCS40 (PQ208) FPGA running at 40MHz. > > I am having problems with running a nubus interface design on this FPGA with the power rails approaching 5.00v. If the power rails are dropped to 4.80v then the design works. > > When the voltage rail is slowly increased from 4.80v upto 5.00v parts of the design will stop working. If you reset the FPGA it sometimes starts working but will quickly stop functioning. I believe the timing in the FPGA is changing with the increased voltage on the rails but I cannot see why it is causing serious problems that I am experiencing. > > Has anyone come across a similar problem or knows what might be going wrong with the FPGA when the power rail is increased?Article: 32447
http://www.xilinx.com/prs_rls/0145xqvr1000.htm There are some neat tricks you can use to check the memory using the readback feature, and reprogram if an error is detected. Austin Michael Boehnel wrote: > Hi, all! > > State machines (SM) are made more secure with additional logic which > detects an illegal state. If an illegal state occurs the SM is forced to > a special state (trap state; reset state) from where it can start > working correctly again. So far so good. > > What happens, if the additional logic is placed in LUTs of an FPGA? > Aren't the LUTs vulnerable from radiation too? > Is there a better protection for the configuration than for the FPGA's > FFs? > > MichaelArticle: 32448
The protocol is responsible. It should have regular bursts of prn sequences that you can lock onto using correlators. Can also use the same sequences for adjusting any adaptive equalizers. Edward wrote: > > I'm working on a differential qpsk encoding and decoding system. I > can manage the portions for symbol encoding/decoding, fifo, cpu > interface. However, I am confused on the front end portions of the > receiver, namely the mixing/multiplying, filtering, and symbol > detection of the received digitized baseband rf data. > > The receiver is digitized the rf signal with a 4x clock. There will > be four data samples per symbol for each of I and Q. The previous > symbol is mutliplied with the current symbol for differential > detection. But how do I determine the boundaries of the received > symbols ? I could be using the last data sample of the previous > symbol and the first three data samples of the current symbol and > incorrectly treat the four as one single symbol. With four data > samples per symbol for each of I and Q, how can I level detect the > decision ? Which three samples shall I discard ? > > Thanks. -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 32449
In article <3B339091.633A1FF8@gmx.de>, Falk.Brunner@gmx.de says... > Hello folks, > > I have a xc95288-10 in a design and I would like to divide a 155.52 MHz > (yes its STM-1) clock signal down to 38.88 MHz (just divide by four). > The counter can be a ripple one. But the datasheet says, it is not > possible, even if I go to speedgrade -6 (minimum pulse width 3.3 ns). > The duty cycle of the 155.52 MHz signal is not perfectly 50%, but > something like 40% can be guarantied I think. Do you think it is > possible (AND reliable). The datasheet of the smalles device (9536XL) > says something about 2.2 ns minimum pulse width, so I think if I just > have 1 FF on the fast clock net, this 2.2ns can also be achieved with > the big device?!! > The XV family is no option, also another FPGA/CPLD family. Is there also > a way to feed the 155.52 MHz signal, which is LVPECL, directly to the > CPLD?. Why dont the CPLDs have the nice IOBs of the FPGAs (with LVPECL > option)?? > > I'm certainly no Guru, but I will try to help you. For the XC95xxXL family of CPLDs all the feedback signals (Output of FFs) are routed through the FastConnectSwitch Matrix at the center of the CPLD. For bigger CPLDs (288 FF) this network is slower than for smaller ones, since it has to be larger. A smaller XC9572XL can therefore run at a higher system speed than the XC95288XL. The older XC95xx CPLD (5V Version) has a local and faster feedback path inside their Function Blocks, but the XL and XV seems to have not. Maybe someone from Xilinx can tell us why they removed them. In the case of local feedback internally the function block it should indeed be possible to have small counters which run equally fast in smaller and bigger devices. I think you should consider an external prescaler. In this case you can also connect the clock to the faster Global Clock Net, which is surely recommendable. Or you are going to look at CPLD from other vendors. -- Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.it
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