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Hi there, This may be a basic question but I'm new to VHDL and FPGA design so hope some of you could help me out on this. My problem is I have an output signal (called A) that should be implemented as RS flip-flops. However the Xilinx foundation 1.5 (student's edition) software would return an error message saying "The net A has more than one driver". This would be the case since two processes control A's logic level, but only one process can turn A high and the other turns A low. So do I need to explicitly create an RS flip-flop, or is there a more elegant way to imply this in VHDL? Thanks in advance.Article: 32626
it is not clear from the post if what you want to do is phase lock square waves (like for clock synthesis) or discrete value signals (like for demodulation) . For the first case , xilinx had some app notes on phase detectors that could be done on fpga's . Loop filters (analog) can be calculated following the FM Gardner , Phaselock Techniques book National semiconductor has a comprensive book online on pll for frequency synthesis . However I have yet to see a Charge pump phase detec. implemented with an fpga Cypress has some interesting parts where everything is in the ic , vco , phase det, loop filter Henri On 20 Jun 2001 05:27:03 -0700, vnwarrior@rediffmail.com (SilverByte) wrote: >hi, > I have to implement a Digital PLL on an FPGA. Does anyone have any >docs regarding this. >Any docs regarding generic design of a PLL is also appreciated. >Thanks in advance >SandyArticle: 32627
sounds like you need to recover symbol timing as a parallel activity to the demodulation . The timing recovery by Gardner published in the transactions on communications should work . Henri On Tue, 26 Jun 2001 20:47:09 GMT, edlee@gpetech.com (Edward) wrote: >I'm working on a differential qpsk encoding and decoding system. I >can manage the portions for symbol encoding/decoding, fifo, cpu >interface. However, I am confused on the front end portions of the >receiver, namely the mixing/multiplying, filtering, and symbol >detection of the received digitized baseband rf data. > >The receiver is digitized the rf signal with a 4x clock. There will >be four data samples per symbol for each of I and Q. The previous >symbol is mutliplied with the current symbol for differential >detection. But how do I determine the boundaries of the received >symbols ? I could be using the last data sample of the previous >symbol and the first three data samples of the current symbol and >incorrectly treat the four as one single symbol. With four data >samples per symbol for each of I and Q, how can I level detect the >decision ? Which three samples shall I discard ? > >Thanks. > > >Article: 32628
Hi, I have now to design on a very old FPGA XC4010 (not E or XL). The problem is the current development softwware that I am using is Fondation ISE 3.1 and this version does not support for xc4000 family and the old software XACT Step 5.2/Sun is out of license. I tried to contact distributor to get new license but just have got the NOT SUPPORT because the software (XACTStep) is too old. Does any one have an idea how to be able to work with XC4000 family at this time ? The device is not replacable because replacement means to destroy the PCB. Thank you very much. Tran Cong So.Article: 32629
1:20000000 would be no problem. In wich magnitude would the frequencies be ? How fast would the rate of change be ? Of course the reaction time is at least one period of the input signal. If the filter is activated the reaction time is even higher. Thomas "Noddy" <g9731642@campus.ru.ac.za> schrieb im Newsbeitrag news:994095820.450864@turtle.ru.ac.za... > If you can get your ratio to something in the order of 1:20000000, then I'll > have an application for it. > > AdrianArticle: 32630
Royan Ong a écrit :
>
> Hi there,
>
> This may be a basic question but I'm new to VHDL and FPGA
> design so hope some of you could help me out on this.
>
> My problem is I have an output signal (called A) that should
> be implemented as RS flip-flops. However the Xilinx foundation
> 1.5 (student's edition) software would return an error message
> saying "The net A has more than one driver". This would be the
> case since two processes control A's logic level, but only one
> process can turn A high and the other turns A low. So do I
> need to explicitly create an RS flip-flop, or is there a more
> elegant way to imply this in VHDL?
Hi
The basic principle is that one process describes one component (it's a
simplification). If you wrote two processes then you described two
components with theit outputs wired together.
I suppose you wrote something like this:
process(set)
begin
if set = '1' then
q <= '1';
end if;
end process;
process(reset)
begin
if reset = '1' then
q <= '0';
end if;
end process;
So what happens when set = '0' ? And when set ='1' AND reset = '1' ?
--
Nicolas MATRINGE IPricot European Headquarters
Conception electronique 10-12 Avenue de Verdun
Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 01 http://www.IPricot.com/
Article: 32631
Hi Royan,
>This may be a basic question but I'm new to VHDL and FPGA design so hope
>some of you could help me out on this.
>
>My problem is I have an output signal (called A) that should be
>implemented as RS flip-flops. However the Xilinx foundation 1.5
>(student's edition) software would return an error message saying "The
>net A has more than one driver". This would be the case since two
>processes control A's logic level, but only one process can turn A high
>and the other turns A low. So do I need to explicitly create an RS
>flip-flop, or is there a more elegant way to imply this in VHDL?
Aaargh.... I think you are doomed on two counts.
First, I suspect (tho' I haven't seen your code) that you have fallen
in to a fairly standard beginner's trap, of assuming that a process
in VHDL (it's VHDL, right???) does one well-defined job.
Something like
.... (declarations and stuff)
process (Set)
begin
if Set='1' then A <= '1'; end if;
end process;
process (Reset)
begin
if Reset='1' then A <= '0'; end if;
end process;
Now there's one truly vital piece of information that you must simply
never, never forget in VHDL: If a process writes to a signal, then
that process represents exactly one driver on that signal.
Here you've two processes both writing to A. So each of them
represents a chunk of logic (actually a rather naff sort of
transparent latch, but that's not the point) that is driving
signal A. Those two chunks of logic are SEPARATE apart from their
commoned output connection. Not what you want, I think.
So, what you really need is a SINGLE process that describes
everything that can be done to A. That means the process needs to
respond both to R and to S, something like this:
....
process (R, S)
begin
if R='1' then
A <= '0';
elsif S='1' then
A <= '1';
end if;
end process;
Note that this process now defines explicitly what happens when R
and S are both asserted (in my code R "wins", but you could easily
alter that of course). And since there's only one process, you
will have only one driver on A.
UNFORTUNATELY.....
this is a VERY bad thing to do in an FPGA. It has asynchronous
feedback (I guess you are familiar with it as a pair of cross-
coupled NOR gates?) and this causes all kinds of trouble both for
the synthesis tool and in the FPGA itself. You should try very
hard to re-work the design of which this is a part so that the
set/reset action is synchronous so that a proper D-type flip-flop
can be used instead of the cross-coupled gates abomination.
Now, that leaves you with an exquisite little problem....
First, you have to find a very nice way to tell your lecturer/
supervisor that he/she has asked you to do something that is
really, really bad practice. This is a far bigger challenge
than learning VHDL.
Second, you should work with that person to reach a clear
understanding of WHAT it is about asynchronous feedback that
is so strongly disapproved of in FPGA design. This shouldn't
be too hard; the Xilinx help files, and any text on FPGA
design, will give you lots of rationale for it.
Finally, you should tell that person how wonderful our courses
are, and how thoroughly they explain all this stuff, and how
you should all come on them one day :-)
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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Article: 32632
Hello all,
Is this a "known problem"?
(F3.1i with service pack #8; Target Spartan XCS10-4-VQ100)
The error comes up only with integer rage >= 0 to 31.
Timing Report:
Slack: -1.284ns path DIR to IST<1> relative to
0.009ns skew between DIR and IST<1>
Path DIR to IST<1> contains 2 levels of logic:
Path starting from Comp: CLB_R9C11.K (from CLK_BUFGed)
To Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- --------
CLB_R9C11.XQ Tcko 2.100F DIR
DIR_reg/I$1
CLB_R10C10.F3 net (fanout=7) 1.455F DIR
CLB_R10C10.K Tasc+Tick (-Th) 4.830F IST<1>
C22/C2/C2
C19
IST_reg<2>/I$1
-------------------------------------------------
Total (-2.730ns logic, 1.455ns route) -1.275ns (to CLK_BUFGed)
(214.1% logic, -114.1% route)
--------------------------------------------------------------------------------
HDL code:
=========
library IEEE;
use IEEE.std_logic_1164.all;
entity problem1 is
port (
SOLL: in integer range 0 to 31;
DIR_OUT : out STD_LOGIC;
CLK : in STD_LOGIC
);
end problem1;
architecture problem1_arch of problem1 is
signal IST : integer range 0 to 31;
signal DIR : BOOLEAN;
begin
DIR_OUT <= '1' when DIR else '0';
process
begin
wait until CLK'event and CLK = '1';
if (DIR) then
IST <= IST + 1;
else
IST <= IST - 1;
end if;
DIR <= (IST = SOLL);
end process;
end problem1_arch;
Any help?
Thank you to all
Ruediger
Article: 32633Actually I do know exactly what I want to do but I probably didn't do a great job of explaining it. It's somewhat similar to companding but it's exactly floating point notation. I want to start with a value that's 27 bits wide... BTime <something>(26 downto 0) and stuff the manipulated value into a value that's 16 bits wide... FOut <something>(15 downto 0) The upper 4 bits of FOut specify the resolution of the LSB 1111 FOut lsb is bit 15 of BTime 1110 FOut lsb is bit 14 of BTime ... 0001 FOut lsb is bit 1 of BTime 0000 FOut lsb is bit 0 of BTime The lower 12 bits of FOut start at the bit selected above and work up for 11 more bits (the msb of this 12 bit value will always be set except when the exponent is 0000 giving us the maximum resolution for any value represented, w/o needing all the bits, which for my purpose I really only need at the bottom end). So technically what I want to do is find the highest bit set in BTime, then set the exponent in FOut (upper 4 bits) accordingly and shift BTime the appropriate bits right before copying the lower 12 bits into the bottom of FOut (or the equivalent, a shift isn't probably the way to do it). Any thoughts? Dave. > There is no reason why you shouldn't be able to do what you want. I > think your problem is with specification, or lack thereof. I am not > clear on what you want and I think neither are you. If you can write > what you want to happen to bits in a detailed way step by step, you > can implement it. Forget VHDL; document what you want in any notation > you are comfortable with and then convert to VHDL. If you need help at > that time, ask in c.l.vhdl. > > PS what you want sounds like A-law or U-law companding in voice > communications. Check them out. > > PPS remember that floating point can not represent all numbers in its > range. Some integers in the 27 bit range will be missed in the 16 bit > format. Make sure that you can handle that case. > > Muzaffer > > FPGA DSP Consulting > http://www.dspia.comArticle: 32634
First of all 2^27 = 128M (134217728) 2^16 = 64K (65536). You can't possibly map 128M things to 64K things without duplicates. This means you can't have the same resolution in both mappings. You can however have the range. One way to do this is to take the high 16 bits (no floating point) and just say bit is equal to 2048 (2K = 2^(27-16)). Remember floating point gives you range at the _expense_ of resolution (for the same number of binary bits). Steve PS check out this paper for a 16-bit floating format. www.ccm.ece.vt.edu/papers/quantitative_text.pdf "David Pariseau" <dpariseau@compuserve.com> wrote in message news:5466a14a.0107031011.25655f3@posting.google.com... > Actually I do know exactly what I want to do but I probably didn't > do a great job of explaining it. It's somewhat similar to companding > but it's exactly floating point notation. > > I want to start with a value that's 27 bits wide... > BTime <something>(26 downto 0) > and stuff the manipulated value into a value that's 16 bits wide... > FOut <something>(15 downto 0) > > The upper 4 bits of FOut specify the resolution of the LSB > 1111 FOut lsb is bit 15 of BTime > 1110 FOut lsb is bit 14 of BTime > ... > 0001 FOut lsb is bit 1 of BTime > 0000 FOut lsb is bit 0 of BTime > > The lower 12 bits of FOut start at the bit selected above and > work up for 11 more bits (the msb of this 12 bit value will > always be set except when the exponent is 0000 giving us the > maximum resolution for any value represented, w/o needing all > the bits, which for my purpose I really only need at the bottom > end). > > So technically what I want to do is find the highest bit set in > BTime, then set the exponent in FOut (upper 4 bits) accordingly > and shift BTime the appropriate bits right before copying the > lower 12 bits into the bottom of FOut (or the equivalent, a shift > isn't probably the way to do it). > > Any thoughts? > > Dave. > > > > > There is no reason why you shouldn't be able to do what you want. I > > think your problem is with specification, or lack thereof. I am not > > clear on what you want and I think neither are you. If you can write > > what you want to happen to bits in a detailed way step by step, you > > can implement it. Forget VHDL; document what you want in any notation > > you are comfortable with and then convert to VHDL. If you need help at > > that time, ask in c.l.vhdl. > > > > PS what you want sounds like A-law or U-law companding in voice > > communications. Check them out. > > > > PPS remember that floating point can not represent all numbers in its > > range. Some integers in the 27 bit range will be missed in the 16 bit > > format. Make sure that you can handle that case. > > > > Muzaffer > > > > FPGA DSP Consulting > > http://www.dspia.com >Article: 32635
Hi, Does anybody has, knows who has a RS232 UART coded in VHDL? Thanks in advance, Gonzalo AranaArticle: 32636
I'm trying to use the Jtag connector to program the FPGA.
I have to use the parallel port in windows NT. And it's not
seeing the cable.
Is there a driver I have to install on my windows NT, How to
install or check if the LPT1 port is working properly in windows NT?
VhdlUser
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Article: 32637> Hmm, I would thinks something around SpartanXL or Spartan 2. Yes, thanks. I asked Xilinx tech-supp by e-mail as our news server at work was down. Within an hour they suggested Spartan 2 :-)Article: 32638
So the function you are asking for is called normalization. Using the restricted resolution (in your case, 12 bits) to represent the largest range ( in your case 0 .. (2^28)-1 ) with the most acuracy . For numbers between 0 .. 4095 you get all integers, for numbers between 4096 .. 8191 you get every second integer. For the numbers between 8192 .. 16383 you get every 4th, .. etc. The structures you need are a circuit to find the position of the first bit set, starting at the MSB of the 27 bit input. A common circuit for this is a priority encoder. For the selection operation (you call it a shift), you could implement this with 12 multiplexers, each with 16 inputs. All the muxes have their select code coming from the priority encoder. This structure is usually called a barrel shifter. Note that there is a common optimization, that assumes that since you are always shifting the number so that the most sig 1 in the 27 bit number ends up in the MSB of your 12 bit mantissa, the result of normalization will always have that bit set. therefore, shift 1 extra bit position, and throw away the '1' . You effectively end up with a 13 bit mantissa, using 12 bits. This is called the hidden '1' normalization. In your case, you would lose the ability to store the numbers 2047 .. 1. '0' is usually special cased. Philip Freidin On 3 Jul 2001 11:11:40 -0700, dpariseau@compuserve.com (David Pariseau) wrote: >Actually I do know exactly what I want to do but I probably didn't >do a great job of explaining it. It's somewhat similar to companding >but it's exactly floating point notation. > >I want to start with a value that's 27 bits wide... > BTime <something>(26 downto 0) >and stuff the manipulated value into a value that's 16 bits wide... > FOut <something>(15 downto 0) > >The upper 4 bits of FOut specify the resolution of the LSB >1111 FOut lsb is bit 15 of BTime >1110 FOut lsb is bit 14 of BTime >... >0001 FOut lsb is bit 1 of BTime >0000 FOut lsb is bit 0 of BTime > >The lower 12 bits of FOut start at the bit selected above and >work up for 11 more bits (the msb of this 12 bit value will >always be set except when the exponent is 0000 giving us the >maximum resolution for any value represented, w/o needing all >the bits, which for my purpose I really only need at the bottom >end). > >So technically what I want to do is find the highest bit set in >BTime, then set the exponent in FOut (upper 4 bits) accordingly >and shift BTime the appropriate bits right before copying the >lower 12 bits into the bottom of FOut (or the equivalent, a shift >isn't probably the way to do it). > >Any thoughts? > >Dave. Philip Freidin FliptronicsArticle: 32639
> On 20 Jun 2001 05:27:03 -0700, vnwarrior@rediffmail.com (SilverByte) > wrote: > > >hi, > > I have to implement a Digital PLL on an FPGA. Does anyone have any > >docs regarding this. > >Any docs regarding generic design of a PLL is also appreciated. > >Thanks in advance > >Sandy http://www-s.ti.com/sc/psheets/slaa011b/slaa011b.pdf Vitali.Article: 32640
Ray Andraka <ray@andraka.com> writes: >Properly done async logic doesn't depend on the delay differences between >signals, but then I have seen very few people that know how to do this >correctly. With that in mind, a properly done async design can be >accomplished in an FPGA, but it requires circumventing the tools so >that they don't do things like removing cover terms. I think what you mean is also called self-timed logic. While I like the term asynchronous logic, it does have other meanings. For example, the common counter with ripple carry is called an asynchronous counter, but it not what you are trying to describe. It might be that such asynchronous logic is a lost art by now. -- glenArticle: 32641
vhdl wrote: > I'm trying to use the Jtag connector to program the FPGA. > I have to use the parallel port in windows NT. And it's not > seeing the cable. > > Is there a driver I have to install on my windows NT, How to > install or check if the LPT1 port is working properly in windows NT? > > VhdlUser > > ------------------------------------------------------------ > Get your FREE web-based e-mail and newsgroup access at: > http://MailAndNews.com > > Create a new mailbox, or access your existing IMAP4 or > POP3 mailbox from anywhere with just a web browser. > ------------------------------------------------------------ There are 1,000,001 reasons for this and, until this afternoon, I thought I'd seen all of them. Here's a new one: Check that no s/w that uses the PP has been installed *after* the JTAG programmer was installed. Part of the JTAG installation is to add a PP driver. The critical file is, I think - c:\winnt\system32\vmm32\windrvr.vxd There are also some registry entries that may get mangled in HKEY_CURRENT_MACHINE\SYSTEM\CurrentControlSet\Services\WinDriverArticle: 32642
Posted for Clifford E. Cummings --- The arguments for and against permitting initializing with initial blocks in synthesizable code are nicely laid out in Ben's e-mail message. GENERAL CASE Initial blocks should NOT be synthesizable. Some synthesis tools, like Synplicity, ignore initial blocks. This is almost criminal! An ignored initial block means that the initial block is providing information to the simulator that is ignored by the synthesis tool. This can cause a mismatch between pre- and post-synthesis simulations. All initial blocks should be flagged as errors by synthesis tools (possible alternative discussed below). Users of any synthesis tool that ignores initial blocks should bitterly complain to their tool vendor. FPGAS AND OTHER POWER-ON-TO-KNOWN-STATE DEVICES An example has been given of FPGAs that power up their registers to known states (or they are programmed to a known state). I could envision using Verilog-2001 attributes to identify an initial block as something like: (* rtl_synthesis, power_on_initialize = true *) initial begin ... // initial register assignments end I imagine that this pragma would identify this initial block as power-on initialization only and any timing controls in the initial block would cause a synthesis tool to flag the initial block as illegal (syntax error). Without the pragma, IMO, the synthesis tool should flag this block as a syntax error, for the reasons stated above. There are a few difficulties with this mechanism: 1) A tool like Synopsys might ignore the pragma and flag a syntax error. This is reasonable behavior. 2) A tool like Synplicity might ignore the pragma and also ignore the initial block. This is the same problem that Synplicity currently has, as explained in the GENERAL CASE above. 3) In general, synthesis tools do not consider the target library when the HDL code is read. If the target device family does not support power-up register initialization, the synthesis tool would have to flag a syntax error at the compile stage, not when the code is read. 4) Libraries would probably require some type of property that synthesis tools could read to indicate if the library supports power-on register initialization. 5) The synthesis compiler will need to be capable of identifying if the initializations are valid, and flag a syntax error if the settings are invalid. 6) Should this feature require all registers to be initialized, or can a subset be initialized? If only a subset is initialized, this becomes a testbench coverage issue (have you tested all of the important scenarios where un-initialized registers are given some default value?). I have always found it a bit scary to power-on a device and not reset all registers before commencing functional operation. 7) Is there a better way to model, simulate and synthesize the behavior of initialized registers other than brute-force setting each register to a known value? How tedious is it to initialize all of the registers of larger FPGA devices from within an initial block? Until something like the above pragma is implemented, keep initial blocks out of all RTL code! Regards - Cliff Cummings At 04:38 PM 7/3/01 EDT, you wrote: >>>> An interesting topic (and responses) came up on comp.lang.Verilog newsgroup: Question: Would it make sense - or are there arguments against - using the Verilog 'initial' block (or VHDL signal initialization statements) to inform a synthesizer what the power-up state of the registers and memory should be? Arguments FOR (from Jonathan.Bromley@doulos.com): 1. Many FPGAs power up with defined states without the use of an external reset signal. Xilinx has "config-up" reset. The config bit stream gives an initial value to just about every FF on the device. And several CPLD families have real physical power-on reset to a known value; and it's always been essentially impossible to exploit that in VHDL or Verilog designs, which is sad because it's potentially a useful feature. The "initialise in an initial block" (Verilog) or "initialised signals" (VHDL) approach would open this window wide. 2. If there is a solid reset mechanism associated with power-up, and if that can be coded so that simulation and synthesis give the same results, then you have met the key requirements that normally force us into using explicit resets. And in any case there is no reason why power-up and explicit reset (possibly to different values!) shouldn't coexist in the same design. Arguments Against: 1. Currently initialization is only defined with explicit resets. Would synthesis vendors really want to change their tools? 2. Not all targets allow for configurations of registers. Synthesis tools would have a hard time synthesizing code for targets that do not provide those configuration features. 3. Portability issues. ---------------------------------------------------------------------------- -- -------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Component Design by Example ... a Step-by-Step Process Using VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ---------------------------------------------------------------------------- -- -------------------------------------- <<<< //*****************************************************************// // Cliff Cummings Phone: 503-641-8446 // // Sunburst Design, Inc. FAX: 503-641-8486 // // 14314 SW Allen Blvd. E-mail: cliffc@sunburst-design.com // // PMB 501 Web: www.sunburst-design.com // // Beaverton, OR 97005 // // // // Expert Verilog, Synthesis and Verification Training // //*****************************************************************//Article: 32643
Hi, I used the Xilinx system generator to implement a 12 bit by 12 bit signed multiplier with no pipelining or latencies. I then used Synplify, the P&R tools and the Timing analyzer, The only constraint entered in synplify was a clock speed of 50Mhz. The Timing analyzer indicated a maximum delay (maximum combinational path delay) of 19.935ns on a path containing 13 levels of logic. This time consists of 10.038ns logic and 9.897ns route. Does route mean the routing (connections between LUTs)? If this is true, is it typically that high (in this case it is 49.6% of the total time delay). DavidArticle: 32644
Could translate the ones at http://www.freecore.com/nosupport/modules.htm Gonzalo Arana wrote: > > Hi, > > Does anybody has, knows who has a RS232 UART coded in VHDL? > Thanks in advance, > > Gonzalo Arana -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 32645
"Stuart Clubb" <stuart_clubb@nospam.hotmail.com> wrote in message news:3b3bf8e1.4793733@news1.attglobal.net... > It seems commonplace for > Silicon Valley employees to make in upwards of $100K with little > competence or skills at all. I have personally interviewed candidates > who were about as much use as chocolate fireguards, yet claimed to > have base salaries of $150K. They were probably bullshitting, but you > will find that the average American engineer is frankly "a bit thick" > in comparison with UK and European standards. That's why Silicon > Valley companies are so reliant on imported Asian, Indian and European > (east and west) talent. > > Apologies to the smart US citizens on the board, but I have to be > honest here. Perhaps I just have high standards? I'm amazed no one has taken Stuart to task for this comment. I wonder how his co-workers at Synopsys feel about it? I've had many chances to make an impression on others, anything from looking a fool to a genius. I've also worked closely with European engineers, and have certainly formed opinions regarding some of their common traits, which I attribute to a different cultural background, rather than their intellect or personality. In my experience, the truly competent person has no need to denigrate others. As for being dependent on imported talent, it's a backwards argument. North America is a centre for technological innovation. This is why foreigners are drawn here, like yourself. I consider it a point of pride, not something to be criticized for. Regards, JamieArticle: 32646
David Nyarko wrote: > > Hi, > I used the Xilinx system generator to implement > a 12 bit by 12 bit signed multiplier with no pipelining > or latencies. > I then used Synplify, the P&R tools and the Timing analyzer, > > The only constraint entered in synplify was a clock speed > of 50Mhz. > > The Timing analyzer indicated a maximum delay (maximum combinational > path delay) of 19.935ns on a path containing 13 levels of logic. > This time consists of 10.038ns logic and 9.897ns route. > > Does route mean the routing (connections between LUTs)? > If this is true, is it typically that high (in this case > it is 49.6% of the total time delay). 60% or more route delay isn't uncommon on the worst case path, especially in a non-floorplanned design of significant size. It's interesting to me that this has not changed much over the past decade, even as the parts have gotten much bigger, much faster, and have more routing resources. -- Phil HaysArticle: 32647
Not sure to follow, if the clocks are related to data, you should be able to use a toggling dff fed by clkx2 ? Use a phase detection/correction circuit and select the proper clock edge so to have the clock aligned with the data or offset by 180 degree. Yanick Rotem Gazit <rotemg@mysticom.com> a écrit dans le message : 86b060d0.0107042309.213ce7b7@posting.google.com... > Hi, > > I need to drive 4 identical clocks out of my Virtex-E FPGA. > I have to align the 4 pins on the same side of the chip, where 2 of > those pins are at the corners and 2 of those pins are in the middle. > Because of other logic on the FPGA I can spare only one or two DLLs > for driving the 4 clocks . > The clocks are related to data , also driven from the FPGA, so I > cannot use tricks like dividing clkx2 near the output pines. > Is there any way to balance the routing delay inside the FPGA ,from > the DLL to the 4 output pins ? > After the routing has been balanced can it be fixed , so it will not > change when the design will be re-implemented ? > > Thanks, > > Rotem Gazit > MystiCom LTD > > mailto:rotemg@mysticom.com > http://www.mysticom.com/Article: 32648
In a same clock application, you violate the clkA setup to clkB. Consequence: the data written at address C is valid on the read port not at the immediate next cycle but at the second one. Given that your application will not write durring run-time, using the 2 ports is the best solution and at no cost. Yanick pete dudley <padudle@spinn.net> a écrit dans le message : tjulb64l2pd0e9@corp.supernews.com... > Hello All, > > I have an application where I am using an 18 by 256 block ram to supply the > coefficients for a filtering operation. The coefficients need to be loaded > from a host computer but during filter operation the address is supplied by > counter logic. > > For coefficient loading it appears that I could just use a dual port ram > configuration and use one port for loading the ram and the other for > addressing the coefficients during filter operation. The alternative is to > put a mux in front of the address bus and switch over to host addressing > when the coefficients are being loaded. I don't really need to be able to > reload the coefficients during filter operation and the host and filter > logic run on the same system clock. > > Is the dual port capability of the BRAM "free" or is there some hidden cost > in using the second port of the BRAM that might make the address mux a > better alternative? > > -- > Pete Dudley > > Arroyo Grande Systems > > >Article: 32649
Jan Gray wrote: > And I agree with Eric that I don't think you can copyright an > instruction set architecture. > > To be clear, my company does not and never has asserted any copyright > on the xr16 architecture or other instruction set architectures we > have described. Thanks Jan and Eric for clearing this up. I've revised statements about xr16 ISA accordingly in v1.01, along with minor doc cleanup. No source code changes. http://www.easystreet.com/~mbutts/xr16vx_jhdl.html --Mike
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