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Nate Goldshlag wrote: > > In article <3B59D22E.C7D8256F@gmx.de>, Falk Brunner <Falk.Brunner@gmx.de> > wrote: > > > Hello everybody, > > > > I (and I suppose many other people in this group ;-) have the problem, > > that it is really difficult to estimate AND measure the power > > consumption of a FPGA design. I know that power consumption strongly > > depends on size of the design, clock frequency and, one of the most > > difficult to estimate parameters, average toggle rate. OK, we have the > > virtex power estimator, XPower and some nice application notes, but > > after all its just a very raw guess, then we add 100% security plus a > > layout to change the power supply easy on the prototype ;-) > > But what is VERY sad is the fact, that it is mostly impossible, to > > measure the power consumption on the real, working board :-((( > > There inst just one VCC pin, there are many, all connectet to the power > > plane. Cutting the power plane and feeding the whole power over a zero > > Ohm resistor is no good idea. Socket?? With BGAs?? Signal integrity?? > > Damit!!! > > > > Whats your expirience with this? > > Any hints? > > One thing that would be really useful but that nobody has to my knowledge is a > tool that works in conjunction with a functional simulation of the device that > could actually look at internal nodes and see toggle rates, see pin I/Os > humping up and down, etc. and would automatically figure out the power > consumption. > > I have wanted a tool like this for years. Does anybody know if such a thing > exists? To do that, all the capacitances in every simulateable node of the fpga would need to be known. -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33301
Thanks, more detail than i could've hoped for. It will take a while to digest, as i haven't figured out in detail the operation of carry chains in relation to the AHDL code. Interesting to find that verilog didn't have signed-number support either. I've been reading up on vhdl, and found that its just like turbo pascal, but with a few extensions... John_H wrote: > > Since Verilog doesn't handle signed numbers natively (yet... look for > Verilog 2001 support from the synthesis vendors) I look at this from the > same perspective as AHDL. I don't think you can get conceptually much > simpler than the method you suggested but you can keep the logical > resources to a minimum. It's been a while since I've touched AHDL so > forgive me if something looks strange below - I think you'll get the > idea. > > Rather than sign extending the adder and doing an xor of the top two > bits (b'10' for saturated negative and b'01' for saturated positive), > recognizing that the inputs to the xor function boil down to just the > two sign bits and the carry-in to the sign stage lets you manipulate the > carry out of the last stage before the sign within the Altera > architecture carry chain to give you the results you want. > > VARIABLES > y[7..0] :NODE; > SignCarryIn :CARRY; > Saturated :CARRY; > q[7:0] :DFF; > > BEGIN > (SignCarryIn,y[6..0]) = (0,a[6..0]) + (0,b[6..0]); -- raw add w/o > signs > y[7] = a[7] & b[7] # (a[7] $ b[7]) & !SignCarryIn; > Saturated = a[7] & b[7] & !SignCarryIn # !a[7] & !b[7] & > SignCarryIn; > q[].clk = Clk; > q[7] = y[7]; -- sign bit above includes saturation > IF( Saturated ) THEN -- if saturated, > q[6..0] = !a[7]; -- a[7]==b[7]==1 gives q[7]=1, q[6..0]=0 > ELSE -- a[7]==b[7]==0 gives q[7]=0, q[6..0]=-1 > q[6..0] = y[6..0]; -- if unsaturated, q[]=y[] > END IF; > END > > Altera gives you a synchronous load that's independent of the carry > chain allowing the combinatorial result to control the load and the sign > from either value (it takes two positives or two negatives to saturate) > to determine the load value. [The Xilinx carry chain can't give > same-cycle load based on carry out unless the synchronous set/reset is > used and the MSbit is in a different slice than the other bits - a > little ugly.] > > If you don't care about symmetry around zero, ignore this paragraph to > avoid confusion... If you want the saturation to be +/- 2^n-1, you > might try adding a carry-in bit (+1) to the next adder stage based on a > -2^n detect. If there is no next adder stage a slower performance > saturable adder can take the +1 carry-in straight from the combinatorial > y[] == -2^n check though the timing analysis might choke a little on > this safe race condition; (a+b) == -2^n doesn't trigger the saturation > load so -2^n+1 still won't trigger the load. > > Not simpler as much as the same concept sped up. > > Russell Shaw wrote: > > > Hi all, > > > > I need a saturable adder like the ALU in DSPs. > > I thought maybe you could just sign-extend the two input > > busses, add them, then detect if the result has overflowed > > the input bus width. If so, the result could be saturated > > to max-neg or max-pos. > > > > AHDL seems a bit limited for handling signed numbers. I'm > > learning some VHDL because it seems to have more constructs > > and knows about signed/unsigned numbers. > > > > Are there any simpler ways of doing such an adder? > > > > --Russell --RussellArticle: 33302
Dave Feustel wrote: > > "bob elkind" <eteam@aracnet.com> wrote in message news:3B56B4AD.1CAB25AB@aracnet.com... > <snipped> > > > AHDL design language gets you pretty close to the the low level of the device > > technology, maintains pretty good "power", and avoids 90% of the frustration > > level of VHDL. Don't forget, schematic libraries can be a minor tar baby unto > > themselves. For a newbie, AHDL is a really good starting point. I'd steer my > > own offspring into AHDL first, to build confidence, before suggesting they > > tackle VHDL on their first design. And I still think schematics are (more or > > less) a dead end, with AHDL being a better alternative.. > > > > -- Bob Elkind, the e-team FPGA/design consulting > > I'm just getting started working with FPGAs. > What is an example of (and source for) an AHDL that I could use > to generate a design for a (Xilinx Spartan 2 or Virtex 2) FPGA? IIRC, AHDL is proprietory to Altera. --RussellArticle: 33303
I don't know, as i haven't tried. Altera or cadence support may know. Dave Feustel wrote: > > Must the network card be connected to the internet for > Leonardo to work? > > "Russell Shaw" <rjshaw@iprimus.com.au> wrote in message news:3B5A99EB.8E4F346D@iprimus.com.au... > > > > > > Peter Ormsby wrote: > > > > > > Philipp Krause <pkk@spth.de> wrote in message > > > news:3B594569.9000504@spth.de... > > > > Are there any free tools around? I'd like to learn VHDL, but don't want > > > > to spend money on commercial software since I don't know which chip > > > > family I'll use when it comes to implementing something. > > > > > > > > Philipp Krause > > > > > > > > > > You can get the free Altera software on this page: > > > > > > http://www.altera.com/support/software/sof-download_center.html > > > > > > Note that you can also get a free copy of Exemplar's Leonardo Spectrum > > > synthesis tool or Synopsys' FPGA Express synthsis tool for either VHDL or > > > Verilog on this page as well. The third-party tools are the same tools > > > you'd get if you were to buy them, but they only let you target Altera > > > devices. > > > > > > -Pete- > > > > and Leonardo only runs if you have a network card... -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33304
Nate Goldshlag wrote: > One thing that would be really useful but that nobody has to my knowledge is a > tool that works in conjunction with a functional simulation of the device that > could actually look at internal nodes and see toggle rates, see pin I/Os > humping up and down, etc. and would automatically figure out the power > consumption. Check out the new xpower program from Xilinx. http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=XPower Run a simulation in Modelsim to generate a toggle file, and load that and the placed and routed design, and xpower will spit out a power estimate. Unless you have a tiny design, don't mess around with the GUI, but run it in batch mode. It is "early access" software, a new code word for beta. Results are at least close to what I expect. Once I get the full design running and make a power measurement, I'll give a longer report. Xilinx claims that a high percentage of designs are close. -- Phil HaysArticle: 33305
John_H wrote: > ... > > VARIABLES > y[7..0] :NODE; > SignCarryIn :CARRY; > Saturated :CARRY; > q[7:0] :DFF; > > BEGIN > (SignCarryIn,y[6..0]) = (0,a[6..0]) + (0,b[6..0]); -- raw add w/o > signs > y[7] = a[7] & b[7] # (a[7] $ b[7]) & !SignCarryIn; > Saturated = a[7] & b[7] & !SignCarryIn # !a[7] & !b[7] & > SignCarryIn; > q[].clk = Clk; > q[7] = y[7]; -- sign bit above includes saturation > IF( Saturated ) THEN -- if saturated, > q[6..0] = !a[7]; -- a[7]==b[7]==1 gives q[7]=1, q[6..0]=0 > ELSE -- a[7]==b[7]==0 gives q[7]=0, q[6..0]=-1 > q[6..0] = y[6..0]; -- if unsaturated, q[]=y[] > END IF; > END There's not much said about handling the carry-chain in the altera docs, other than the acex data sheet. I assume that when a 'carry' type is on the left side of an assignment, its always the MSB carry out, and when on the right side, its always assumed to be a LSB carry-in. --RussellArticle: 33307
AHDL is a high-level design language that is Altera proprietary... It is supported only by Altera's design tools. You can download the design tools from Altera's website and Altera will grant you a free license for using the tools. However, you won't be able to target non-Altera devices with the Altera tools (practically speaking). -- Bob Elkind, the e-team FPGA/design consulting Dave Feustel wrote: > "bob elkind" <eteam@aracnet.com> wrote in message news:3B56B4AD.1CAB25AB@aracnet.com... > <snipped> > > > AHDL design language gets you pretty close to the the low level of the device > > technology, maintains pretty good "power", and avoids 90% of the frustration > > level of VHDL. Don't forget, schematic libraries can be a minor tar baby unto > > themselves. For a newbie, AHDL is a really good starting point. I'd steer my > > own offspring into AHDL first, to build confidence, before suggesting they > > tackle VHDL on their first design. And I still think schematics are (more or > > less) a dead end, with AHDL being a better alternative.. > > > > -- Bob Elkind, the e-team FPGA/design consulting > > I'm just getting started working with FPGAs. > What is an example of (and source for) an AHDL that I could use > to generate a design for a (Xilinx Spartan 2 or Virtex 2) FPGA? > > Thanks, > > Dave Feustel > Fort Wayne, IndianaArticle: 33308
Leon Heller wrote: > > I've just built up a prototype of a simple prototyping system for the > Altera Flex 10K10. If there is any interest, I'll get some more boards > made. I'll be placing the design in the public domain, and making the > Gerbers available for anyone who wants to get their own PCB made. > > The PCB is four-layers, 80mm X 100mm (half Eurocard). Unregulated DC > (8-12V) needs to be provided from a suitable PS, like a wall-wart. > There is an 'idiot' diode to prevent damage if the supply is round the > wrong way. A socket is provided for a 14-pin crystal oscillator > module. The Flex chip is configured via a standard Byteblaster header, > there is no provision for a configuration device. Most of the Flex I/O > and +5V is available via a 64-way DIN41612 plug, to which a suitable > Eurocard prototyping board may be attached. > > I've put a picture on my web site: > > http://www.geocities.com/leon_heller/flex.gif > > Leon Heller Burch use to make a nice 10k10 FPGA board but they moved to bigger chips. Having the this board has me thinking about the few problems I have using this board - I can't interface it to to a large solderless breadboard. Rather than making another full sized PC board is make a FPGA adapter PCB's to fit a solderless breadboards. Ben. PS. Your URL gives me a not found error. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics.Article: 33309
Hi I've built a Xilinx Parallel cable according to the schematics available on Xilinx's site and it doesn't work. When I use the original cable everything is fine so my board is OK. I looked at the signals with an oscilloscope and everything seems normal (I see TDI, TCK and TMS toggle on the board), except that TDO stays high. Any idea? -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 33310
Ray Andraka schrieb: > > Measure the differential power on the board between a configured and > running FPGA and one that is either unconfigured or loaded with a > placeholder static design. Hmmm, this may be a first attempt. But Iam afraid this wont work at all, because mostly the FPGA drives other circuits, and when it doesnt drive them, the other circuits draw also less current. So we would measure a part of the power consumption of other circuit, connected to the FPGA. Hmm. But maybe it is possible to create a fake interface to the other circuit that just toggle some data lines and clocks and so make the other circuits work. -- MFG FalkArticle: 33311
I am looking for an online description of the EDN netlist format. Does anybody know such a site? Is there free source code for the analysis of EDN-Files available? MichaelArticle: 33312
Yi-Shin Li wrote:
>
> Hello,
>
> I am thinking the cost between 3-to-1 and 4-to-1 mux.
> The thing is that in 2 level logic, the 3-to-1 MUX has
> lower cost than the other one. Am I correct?
>
> However, I do not know in real FPGA implemeatation,
> what is the cost difference between them?
As a rule of thumb you could say that the cost in FPGA is (independent
of the function) only determined by the number of inputs. The number of
maximum inputs per minimal Funktion depends on the technology.
If the smallest cell gots 5 inputs, there will be a clear difference
between 3-to-1 amd 4-to-1.
bye Thomas
--
Thomas Stanka
Bosch SatCom GmbH UC_RA/EMD4 s/UC-RA/BC
Gerberstr. 49 Tel. +49 7191 930-1690
Zi. 10/528 Fax. +49 7191 930-21690
Thomas.Stanka@de.bosch.com
Article: 33313Hi, I have also made this cable and the only problem I met was cable length. Xilinx advices wire connection between JTAG header and Parallel III electronics to be "as short as possible" and between electronics and LPT port no longer than 2m. I have placed electronics inside standard DSUB25 connector and according to Xilinx's schematic JTAG-electronics cable length musn't exceed 0,5m. Finally I got rid of all 100pF capacitors connected to JTAG signal lines and now my cable has 2m and works without reservation. I haven't tried to make it longer... Regards Daniel Nicolas Matringe wrote: > Hi > I've built a Xilinx Parallel cable according to the schematics available > on Xilinx's site and it doesn't work. When I use the original cable > everything is fine so my board is OK. I looked at the signals with an > oscilloscope and everything seems normal (I see TDI, TCK and TMS toggle > on the board), except that TDO stays high. Any idea? > > -- > Nicolas MATRINGE IPricot European Headquarters > Conception electronique 10-12 Avenue de Verdun > Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE > Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 33314
> Must the network card be connected to the internet for
> Leonardo to work?
No. Works just fine offline.
Martin
--
Whant to see the evolution of a Java processor?
http://www.jopdesign.com
Article: 33315Daniel Hañczewski a écrit : > > I have also made this cable and the only problem I met was > cable length. > [...] I got rid of all 100pF capacitors connected to JTAG > signal lines and now my cable has 2m and works without > reservation. I haven't tried to make it longer... Could be the problem. Thanks a lot -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 33316
In article <3B5BF9BA.47B237A9@de.bosch.com> Thomas Stanka <Thomas.Stanka@de.bosch.com> writes:
>Yi-Shin Li wrote:
>>
>> Hello,
>>
>> I am thinking the cost between 3-to-1 and 4-to-1 mux.
>> The thing is that in 2 level logic, the 3-to-1 MUX has
>> lower cost than the other one. Am I correct?
>>
>> However, I do not know in real FPGA implemeatation,
>> what is the cost difference between them?
>
>of the function) only determined by the number of inputs. The number of
>maximum inputs per minimal Funktion depends on the technology.
>If the smallest cell gots 5 inputs, there will be a clear difference
>between 3-to-1 amd 4-to-1.
Depends. With Altera's FLEX family each cell has 4 normal inputs
and in the cascade mode also a dedicated fifth input, making the
cost of both muxes identical.
First cell: Out1 <= a, if input="00"
b, if input="01"
else '0'; (4 inputs)
Second cell: Out <= c, if input="10"
<= d, if input="11"
OR Out1; (4 inputs plus fast OR cascade)
--
Problems 1) do NOT write a virus or a worm program
"A.K.Dewdney, The New Turing Omnibus; Chapter 60: Computer viruses"
Article: 33317I am on http://support.xilinx.com/support/techsup/sw_updates/31i/sw_f33i_pc.htm trying to download the Foundation 3.3i Software Updates for PC (3.3i service pack 8), but I cannot download these single files. Why?Article: 33318
Thanks Mike, this helped! khiltrop@gesytec.de wrote: > > Hi > > My Modelsim XE 5.3d claims > Incompatible modes for port abc > with port abc being an 'inout' port. > Is there a special trick I do not know about? How can I simulate > bidirectional ports? > I am using XILINX ISE 3.1i An INOUT design port can only be connected to another INOUT or IN port on the testbench. Make sure you have an output enable control on both sides and that the inout ports drive data or all Z based on that control. --Mike TreselerArticle: 33320
"Jrrvvf" <rtg@ff.xivc> wrote in message news:3B5B507D.4032E6D9@ff.xivc... > > > I have the Silo-3 Demo from "Verilog HDL_ by Samir Palnitkar > > > installed on two machines running Windows 2000 Pro. > > > One is a Dell Dimension XPS Pro200n, the other is a Dell 4100. > > > Silo runs on the XPS, but crashes with a memory access violation > > > as soon as I attempt to run a simulation on the 4100. This behavior > > > occurs with exam1a.s. (While Silo does run on the XPS, it crashed > > > while I was adjusting a window size. How stable is the demo version > > > of Silo?) > > > > > > Does anyone have any idea what might be causing this? > > > > As a wild guess - Windows 2000. The same program works ok here on Win98. > > The Silos executable bundled with that book is probably very very old, > back from the Win95 days. I have had no problems running an updated > Silos demo version under Win2000 Pro. Unfortunately, simucad.com > recently stopped handing out the free demo version. Now they require > you register for an evalulation version. I downloaded the Silos demo program but it reports fatal errors when I try to run any of the sample projects. I'd be willing to try the evaluation version But... For security reasons, I run my development software on a computer completely disconnected from the internet. Doing that makes registering software harder, sometimes *much* harder.Article: 33321
The arithmatic is just arithmatic. The synthesis tools figure out what constitutes a carry-out and a carry-in. In AHDL you can make "suggestions" based on the :NODE; or :CARRY; as typecast in the VARIABLES section in the example I gave. In aVerilog/VHDL synthesizer like Synplify the tool is often smart enough to figure out what constitutes a carry in the arithmetic equations but even then might need a little coaxing by manually instantiating a carry primitive (which I do often enough for carry-in signals). Getting familiar with the target architecture is important for high performance, low resource implementations. I recommend a good data-sheet read for anyone taking on FPGA design to know what the silicon can do. Russell Shaw wrote: > There's not much said about handling the carry-chain in the altera docs, > other than the acex data sheet. I assume that when a 'carry' type is on > the left side of an assignment, its always the MSB carry out, and when > on the right side, its always assumed to be a LSB carry-in. > > --RussellArticle: 33322
Environment: XC9500, Xilinx ISE 3.1i When I try to synthesize the code below I receive the error ERROR : (HDL__0051). Synchronous output enable not supported. When I change the 'Z' in the marked line to '0' it synthesizes just fine. Why? Thanks in advance, Clemens process(clk, enable) begin if (enable ='0') then D_out<=(others=>'Z'); elsif (clk'event and clk= '0') then if (load = '1') then D_out <= D_ltch; else D_out<=(others=>'Z'); -- <== change 'Z' to '0' OK ???? end if; end if; end process;Article: 33323
I've just built up a prototype of a simple prototyping system for the
Altera Flex 10K10. If there is any interest, I'll get some more boards
made. I'll be placing the design in the public domain, and making the
Gerbers available for anyone who wants to get their own PCB made.
The PCB is four-layers, 80mm X 100mm (half Eurocard). Unregulated DC
(8-12V) needs to be provided from a suitable PS, like a wall-wart.
There is an 'idiot' diode to prevent damage if the supply is round the
wrong way. A socket is provided for a 14-pin crystal oscillator
module. The Flex chip is configured via a standard Byteblaster header,
there is no provision for a configuration device. Most of the Flex I/O
and +5V is available via a 64-way DIN41612 plug, to which a suitable
Eurocard prototyping board may be attached.
I've put a picture on my web site:
http://www.geocities.com/leon_heller/flex.gif
Leon Heller
Article: 33324
>When I try to synthesize the code below I receive the error
>
>ERROR : (HDL__0051). Synchronous output enable not supported.
>
>When I change the 'Z' in the marked line to '0' it synthesizes just fine.
>Why?
>
>Thanks in advance,
>Clemens
>
>
>process(clk, enable)
>
>begin
> if (enable ='0') then
> D_out<=(others=>'Z');
> elsif (clk'event and clk= '0') then
> if (load = '1') then
> D_out <= D_ltch;
> else
> D_out<=(others=>'Z'); -- <== change 'Z' to '0' OK ????
> end if;
> end if;
>end process;
>
What kind of Flip-flop would yield a 'Z' onto its output?
What you need to do is use a regular FF that yields a '0' or '1' as output.
Follow that with a concurrent signal assignmet to infer a tri-state:
D_Output <= Qvector_FF when tri_condition = '0' else
(others => 'Z');
--------------------------------------------------------------------------
------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ... a Step-by-Step Process Using
VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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