Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 44775

Article: 44775
Subject: Re: 5V tolerance
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 30 Jun 2002 11:19:21 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> rickman wrote:
> 
> >
> >   Whenever I am asked to sign a
> > contract that contains language that I find objectionable, I balk no
> > matter how much I am told that "that is never enforced" or "that is only
> > for trouble makers" or what ever the excuse is.  The bottom line is -
> > make the contract say what you intend.
> >
> > So Xilinx, why DO you have a one year license if the software does not
> > stop working and you don't plan to stop anyone from using it?
> >
> > --
> 
> Well, this is a country that graduates far more lawyers than engineers.
> And they are always looking for something to do...
> 
> Peter Alfke, speaking fo himself, so Xilinx does not get sued.


Is there a statement somewhere in that cryptic comment?  

Is there some reason that Xilinx would be liable if the software license
did not time out?  If Xilinx thinks this opens them for liability, I
think they have too many lawyers smoking crack.  If you read the
responses here, you will see that there are clear cases where the
expiring license causes concern with potential customer's engineers in
addition to their lawyers.  

How many lost sales does it take to make up for an imaginary potential
law suit?  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 44776
(removed)


Article: 44777
Subject: Re: XESS / Digilent / Trenz Board Experience ? Help.
From: anon <anon@nowhere.net>
Date: Sun, 30 Jun 2002 19:01:19 GMT
Links: << >>  << T >>  << A >>
As far as I know, all of Xess's boards can be programmed through
parallel
port.

Xess's older XS40 boards (XC40x0XL parts) can only be programmed through
the parallel port, using Xess's XSTOOLs package.

Xess's newer Virtx/Spartan2 boards (you must check their website for 
exact model#s) can be programmed through the FPGA's JTAG port (using 
Xilinx's standard parallel DL cable, or USB-cable.)  Or you can use 
XSTOOLs package.

I, myself, have both the XS40-010XL+ (XC4010XL + 128kB) and the
XSV-300 v1.0 board.  The V1.1 board is compatible with Xilinx's
chipscope ILA.

> Its me again, I have looking for a board to buy for 3weeks now, and I think
> I am inclined towards the XESS Board. I want to hear whether from other
> users of this board or any other board. My only grim with this board is lack
> of USB interface and gate_count per $.

I'm guessing you are looking at Xess's XSA-50 or XSA-100?  The XSV
boards
have USB-interface, but are quite more expensive!

> Other boards I am considering are Digilab2 or Trenz(TE....)
> 
> Iwould also like to confirm whether FPGA can be programmed via USB/parallel
> port adapter.
> 
> Pls Help as I need to get on with things b4 Jul.
> 
> Cheers.
> 
> Femi

Article: 44778
Subject: Xilinx Virtex2-Pro: availability?
From: anon <anon@nowhere.net>
Date: Sun, 30 Jun 2002 19:02:57 GMT
Links: << >>  << T >>  << A >>
We'd love to get our hands on the RocketI/O (gigabit transceiver)
capable Virtex2-Pro chips...

problem is, does anyone have them in stock?  Engineering samples even?!?
Avnet told us '11 weeks lead time'...

Article: 44779
Subject: Re: Timed Licenses and version control ( was 5V tolerance )
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 01 Jul 2002 09:36:58 +1200
Links: << >>  << T >>  << A >>
rickman wrote:
> 
<paste>>
>>> I think people have misunderstandings of how the Xilinx software is
>>> licensed.  I am pretty sure I have read in this newsgroup postings from
>>> Xilinx representatives that the Xilinx software will continue to operate
>>> after the license has run out.  Only the support is ended.

> > Peter Alfke wrote:
> > That is correct.
> > The expiration of the software is only in the wording of the license agreement.
> > 
> > There is *no* physical licensing mechanism that might prevent a user from
> > continuing to maintain existing designs in the indefinite future, as long as
> > you need it, as long as you want. No problem!

> > >  rickman wrote:
> > >   Whenever I am asked to sign a
> > > contract that contains language that I find objectionable, I balk no
> > > matter how much I am told that "that is never enforced" or "that is only
> > > for trouble makers" or what ever the excuse is.  The bottom line is -
> > > make the contract say what you intend.
> > >
> > > So Xilinx, why DO you have a one year license if the software does not
> > > stop working and you don't plan to stop anyone from using it?
> >
> > Peter Alfke wrote:
> > Well, this is a country that graduates far more lawyers than engineers.
> > And they are always looking for something to do...
> >
> > Peter Alfke, speaking fo himself, so Xilinx does not get sued.
> 
> rickman wrote:
> Is there a statement somewhere in that cryptic comment?
> 
> Is there some reason that Xilinx would be liable if the software license
> did not time out?  If Xilinx thinks this opens them for liability, I
> think they have too many lawyers smoking crack.  If you read the
> responses here, you will see that there are clear cases where the
> expiring license causes concern with potential customer's engineers in
> addition to their lawyers.
> 
> How many lost sales does it take to make up for an imaginary potential
> law suit?

 Since I believe the  policy is partly driven by the third party 
components of Xilinx tools, perhaps a clear statement is needed 
that covers:

* ALL tool components, Xilinx and External, plus those External 
  companies' view of what a timed license really means/does.
* Any & All license files, and license tags that are date-correlated
  eg does some SW flip into the s l o w mode after a time ?
* Define and clarify 'maintain existing designs'
  is this somehow name locked - eg if a company starts with a global
  product, then finds they need a Europe / Asian / US model split, is
that
  a) an existing design ? - or - 
  b) Three new designs ? - or -
  c) A feeding trough for lawyers, 'looking for something to do' ?

 Combine this with the many problems that appear in 'new releases' on 
this news group, plus the 'moving goal posts' trend to prune old 
devices, and it becomes quite a struggle to manage a good version 
control.

 - jg

Article: 44780
Subject: Re: How can I preserve FFs in LeonardoSpectrum?
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Mon, 01 Jul 2002 09:20:10 +0200
Links: << >>  << T >>  << A >>
Kevin Brace wrote:
> 
> Does anyone know how I can preserve FFs in LeonardoSpectrum?

Hi
You can set the preserve_driver attribute
I used it to prevent LS from removing intentionnally duplicated logic and it
worked fine.
Look in the manual for the exact syntax in VHDL or Verilog

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 02      http://www.IPricot.com/

Article: 44781
Subject: Re: How can I preserve FFs in LeonardoSpectrum?
From: Laurent Gauch <laurent.gauch@amontec.com>
Date: Mon, 01 Jul 2002 10:42:32 +0200
Links: << >>  << T >>  << A >>
Hi,

Before try to keep the hierarchie of your design.
If you are working flatten with a big design, Leo can simplify complex 
feedback.
(you can isolate a part of you design using the 'ungroup' tcl function)

Laurent
www.amontec.com

Nicolas Matringe wrote:

> Kevin Brace wrote:
> 
>>Does anyone know how I can preserve FFs in LeonardoSpectrum?
>>
> 
> Hi
> You can set the preserve_driver attribute
> I used it to prevent LS from removing intentionnally duplicated logic and it
> worked fine.
> Look in the manual for the exact syntax in VHDL or Verilog
> 
> 


Article: 44782
Subject: re..filter design for fpga
From: mkalanuk@yahoo.co.uk (Alan McKitterick)
Date: 1 Jul 2002 02:00:01 -0700
Links: << >>  << T >>  << A >>
Hi Tom

Have a look at ONEoverT fron
www.tyder.com

They are giving away the VHDL module with which
you can create FIR, IIR, differentiators and
Hilbert Transformers. There is a case study 
which you can also download. Altera and Xilinx
will allow you to generate black box IP filters.
You can find the details on their web sites.

Hope this helps

Alan

Article: 44783
Subject: Re: 32KHz oscilator in CPLD
From: "Tuomo Auer" <tuomo.auer@hut.fi>
Date: Mon, 1 Jul 2002 14:42:06 +0300
Links: << >>  << T >>  << A >>
I once tried 32kHz oscillator with Altera's EPM7064S (7064, crystal, two
resistors, two capacitors). Connection was pretty identical that can be
found from datasheet of CD4060 counter chip. It worked and frequenzy of
oscillation seemed to be ok though any precision measurements was not done.

--
Tuomo Auer

"a.j." <andrej.jancura@tu-ilmenau.de> wrote in message
news:aff01m$e6n$1@piggy.rz.tu-ilmenau.de...
> Hi,
>
> few days ago the oscilator implementation with external RC has been
> discussed in the list. Now I'd like ask you, if it possible to make the
> oscilator only with external 32kHz crystal in Xilinx 95xx and CoolRunner
> series. Thank you.
>
> Andrej
>
>



Article: 44784
Subject: Altera Archive
From: Kai Eckert <stebu@gmx.de>
Date: Mon, 01 Jul 2002 14:25:55 +0200
Links: << >>  << T >>  << A >>
Hi!

I'm looking for a well-known game called Snake for the Altera Flex.
Where can I get this? Do you know a AHDL or VHDL archive, which may
contain that game?

Thnx in advance,
Werner

Article: 44785
Subject: Reconfiguring .SOF file
From: Holger Englert <englert@informatik.uni-wuerzburg.de>
Date: Mon, 01 Jul 2002 14:37:01 +0200
Links: << >>  << T >>  << A >>
I'd like to change the contents of the flex 10K internal memory EABs 
(LPM_RAM).
The EABs are connected with a .mif file and the design is compiled to a
.sof File.
Is it possible to modify the content of the EABs just by changing the
.sof-File (without recompiling)? Is a tool for this available?

Thanks for any help
Holger Englert


Article: 44786
Subject: combine the Verilog code
From: "Minlin Fan" <minlinf@hotmail.com>
Date: Mon, 1 Jul 2002 14:17:24 +0100
Links: << >>  << T >>  << A >>
Hello all,

I have  implemented some Verilog code for some specific parts on a circuit
board. Now I want to combine them into one piece of code and let the circuit
board work as a unit. Anyone can give me some advice in doing this?

Example: I have the following modules tested seperately:-
1) module m1(port lists)
2) module m2(port lists)
Now I want these two to be combined into one module, say moduel big_m(port
lists).
I am not sure how to use the port lists as the two modules m1 and m2 use
some of the ports at the same time. If I use them in one module will it mess
around the ports?

Cheers.
Minlin



Article: 44787
Subject: Re: How can I preserve FFs in LeonardoSpectrum?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Mon, 01 Jul 2002 09:38:55 -0500
Links: << >>  << T >>  << A >>


Nicolas Matringe wrote:
> 
> 
> Hi
> You can set the preserve_driver attribute
> I used it to prevent LS from removing intentionnally duplicated logic and it
> worked fine.
> Look in the manual for the exact syntax in VHDL or Verilog
> 


        I used the preserve_driver attribute, but LeonardoSpectrum still
merged equivalent (parallel) FFs into one FF which I don't want it to do
that.
Does LeonardoSpectrum even have a synthesis keyword that prevents
equivalent FF removal?


Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 44788
Subject: Can Coolrunner's be daisy chained?
From: "steve synakowski" <srs@twcny.rr.com>
Date: Mon, 01 Jul 2002 14:51:27 GMT
Links: << >>  << T >>  << A >>
Hi, I'm having one heck of a time trying to find out if I can daisy chain
coolrunner XPLA3 CPLD's.
Using impact 4.2WP0.x
I found this statement in the help.
Also, if so, is there any information on the configuration? I guess TDO-TDI,
and the rest in parallel?

-> I found this in the iMpact programming software help.
Slave-Serial mode is supported by all Xilinx FPGA families, but not Xilinx
CPLDs. It uses an external clock and allows for daisy-chain configurations.

Thanks,




Article: 44789
Subject: Re: blank CPLD
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 01 Jul 2002 16:09:03 +0100
Links: << >>  << T >>  << A >>


Falser Klaus wrote:

> In article <afhr7s$qgr$06$1@news.t-online.com>, mrandelzhofer@uumail.de
> says...
> >...
> > Xilinx recommends to switch off any clocks or fast signals on any pin for
> > programming the device.
> > In practice this seems to be necessary only for already programmed parts or
> > very full parts.
> ...
> Could you tell me please where you have read this?
> Until now I have alway programmed my CPLD's with the clock applied.
> I would like to know if this can lead to problems.
>
> Thanks
>
>

I've seen this somewhere as well and IIRC it was in some answer in the support
database. I too have never had any problems reprogramming Xilinx CPLDs while the
clocks are running. I think its less to do with the clocks themselves as with the
internal logic and I've always had a link to keep everything in reset with IOs
tri-stated while reprogramming. Just occasionally I've forgotten to insert the
link and, even less frequently, I've had a programming failure because of it.



Article: 44790
Subject: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
From: Matthias Neuroth <matthias@xilinx.com>
Date: Mon, 01 Jul 2002 16:16:32 +0100
Links: << >>  << T >>  << A >>
Steven,


the accuracy level is dependent on the qualifier status. For the
upcoming software release (5.1i), you can expect the following levels

   * 10% for Spartan-II, Virtex and Virtex-E parts
   * 20% for Spartan-IIe and Virtex-II parts

Please keep in mind that the accuracy of the tool depends on a number of
important factors. Some of these, for example activity settings data,
have to be supplied by the user (guess, simulation data, etc).

Matthias Neuroth

Steven Derrien wrote:

> Hi,
>
>   Since my last post did not get any answer, and before I give up
> I decided to try again ..
>
>   Are there any benchmark/figure/data regarding the accuracy of the
> Xpower tool ?
>
> Steven Derrien


Article: 44791
Subject: Re: combine the Verilog code
From: John_H <johnhandwork@mail.com>
Date: Mon, 01 Jul 2002 15:51:37 GMT
Links: << >>  << T >>  << A >>
When you instantiate the lower level modules (m1, m2) in your top level module,
you need to define the lower level ports in either an "Implicit Internal
Connection" (ordered format) which doesn't care about the lower level port
names, only the order, or an "Explicit Internal Connection" which uses the port
names you've defined.  I hate to see the implicit because it's too easy to miss
something - explicit allows me to see the names of the lower level ports.

The top level module can have names that are unrelated or even contradictory to
the names of the lower level modules.  The names can and often do change at the
transition between hierarchy levels.

An example might be:

module top ( sysClk, in, out );
input sysClk, in;
output out;
wire midsig;

m1 first_stage ( .clk(sysClk), .in1(in), .out(midsig) );
m2 last_stage ( .fastclk(sysClk), .in(midsig), .out(out) );

endmodule

The explicit callouts ".portname()" use top level wires within the parenthesis.
The top level wires can be any valid Verilog wire name without consideration for
the lower level module port names.  It all gets changed in the instantiation.

There's also another newsgroup, comp.lang.verilog, for your continued coding
pleasure.



Minlin Fan wrote:

> Hello all,
>
> I have  implemented some Verilog code for some specific parts on a circuit
> board. Now I want to combine them into one piece of code and let the circuit
> board work as a unit. Anyone can give me some advice in doing this?
>
> Example: I have the following modules tested seperately:-
> 1) module m1(port lists)
> 2) module m2(port lists)
> Now I want these two to be combined into one module, say moduel big_m(port
> lists).
> I am not sure how to use the port lists as the two modules m1 and m2 use
> some of the ports at the same time. If I use them in one module will it mess
> around the ports?
>
> Cheers.
> Minlin


Article: 44792
Subject: Re: Can Coolrunner's be daisy chained?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 1 Jul 2002 18:20:13 +0200
Links: << >>  << T >>  << A >>
"steve synakowski" <srs@twcny.rr.com> schrieb im Newsbeitrag
news:P%ZT8.78662$uk2.31093590@twister.nyroc.rr.com...

> Hi, I'm having one heck of a time trying to find out if I can daisy chain
> coolrunner XPLA3 CPLD's.

What do you mean with "daisy chained"?

> Using impact 4.2WP0.x
> I found this statement in the help.
> Also, if so, is there any information on the configuration? I guess
TDO-TDI,
> and the rest in parallel?

The JTAG port is just a JTAG port, which can be handled as such one.

> -> I found this in the iMpact programming software help.
> Slave-Serial mode is supported by all Xilinx FPGA families, but not Xilinx
> CPLDs. It uses an external clock and allows for daisy-chain
configurations.

CPLDs need no Configuration interface, since they are FLASH/EEPROM based.
Once programmed (via JTAG), they keep their configuration also after
power-off.

--
MfG
Falk





Article: 44793
Subject: Re: Can Coolrunner's be daisy chained?
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 01 Jul 2002 12:27:56 -0400
Links: << >>  << T >>  << A >>
steve synakowski wrote:
> 
> Hi, I'm having one heck of a time trying to find out if I can daisy chain
> coolrunner XPLA3 CPLD's.
> Using impact 4.2WP0.x
> I found this statement in the help.
> Also, if so, is there any information on the configuration? I guess TDO-TDI,
> and the rest in parallel?
> 
> -> I found this in the iMpact programming software help.
> Slave-Serial mode is supported by all Xilinx FPGA families, but not Xilinx
> CPLDs. It uses an external clock and allows for daisy-chain configurations.
> 
> Thanks,

Xilinx FPGAs can be programmed via several types of interfaces that are
just for configuration.  The CPLDs can only be configured via the JTAG
interface.  In general JTAG can be daisy chained.  But it is up to the
software to support this and I am not certain since I have not used it,
but I have been told that the Xilinx software supports multiple device
JTAG configuration.  In fact it should work with other devices in the
JTAG chain other than just Xilinx.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 44794
Subject: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
From: John Blaine <john.blaine@xilinx.com>
Date: Mon, 01 Jul 2002 17:32:33 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------710B0258975530A79200A7A2
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

Steven

No they are not worst case.

John

Steven Derrien wrote:

> Matthias Neuroth wrote:
> >
> > Steven,
> >
> > the accuracy level is dependent on the qualifier status. For the
> > upcoming software release (5.1i), you can expect the following levels
> >
> >    * 10% for Spartan-II, Virtex and Virtex-E parts
> >    * 20% for Spartan-IIe and Virtex-II parts
> >
> > Please keep in mind that the accuracy of the tool depends on a number of
> > important factors. Some of these, for example activity settings data,
> > have to be supplied by the user (guess, simulation data, etc).
>
> Are these worst case numbers ?
>
> Thanks,
>
> Steven derrien
>
> >
> > Matthias Neuroth
> >
> > Steven Derrien wrote:
> >
> > > Hi,
> > >
> > >   Since my last post did not get any answer, and before I give up
> > > I decided to try again ..
> > >
> > >   Are there any benchmark/figure/data regarding the accuracy of the
> > > Xpower tool ?
> > >
> > > Steven Derrien



Article: 44795
Subject: Re: blank CPLD
From: "M. Randelzhofer" <mrandelzhofer@uumail.de>
Date: Mon, 1 Jul 2002 19:05:39 +0200
Links: << >>  << T >>  << A >>
XAPP104, ITEMs No 7
http://www.xilinx.com/xapp/xapp104.pdf


MIKE



"Falser Klaus" <kfalser@IHATESPAMdurst.it> schrieb im Newsbeitrag
news:MPG.178a28eaf10666b5989689@151.99.250.3...
> In article <afhr7s$qgr$06$1@news.t-online.com>, mrandelzhofer@uumail.de
> says...
> >...
> > Xilinx recommends to switch off any clocks or fast signals on any pin
for
> > programming the device.
> > In practice this seems to be necessary only for already programmed parts
or
> > very full parts.
> ...
> Could you tell me please where you have read this?
> Until now I have alway programmed my CPLD's with the clock applied.
> I would like to know if this can lead to problems.
>
> Thanks
>
> --
> Klaus Falser
> Durst Phototechnik AG
> kfalser@IHATESPAMEdurst.it



Article: 44796
Subject: Re: Can Coolrunner's be daisy chained?
From: "steve synakowski" <srs@twcny.rr.com>
Date: Mon, 01 Jul 2002 17:12:10 GMT
Links: << >>  << T >>  << A >>

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:afq12k$g6f76$1@ID-84877.news.dfncis.de...
> "steve synakowski" <srs@twcny.rr.com> schrieb im Newsbeitrag
> news:P%ZT8.78662$uk2.31093590@twister.nyroc.rr.com...
>
> > Hi, I'm having one heck of a time trying to find out if I can daisy
chain
> > coolrunner XPLA3 CPLD's.
>
> What do you mean with "daisy chained"?

I mean programming multiple parts on a board with one cable connection.
Usually the data gets clocked through all of them in a big loop on the data
line.
I know about the requirement for the configuration memory for FPGA, and that
CPLD's don't need that.
I was thinking that maybe the 'slave-serial' might have to do something with
the programming af the CPLD also, maybe it has to do with only the FPGA
memory.
Thanks

>
> > Using impact 4.2WP0.x
> > I found this statement in the help.
> > Also, if so, is there any information on the configuration? I guess
> TDO-TDI,
> > and the rest in parallel?
>
> The JTAG port is just a JTAG port, which can be handled as such one.
>
> > -> I found this in the iMpact programming software help.
> > Slave-Serial mode is supported by all Xilinx FPGA families, but not
Xilinx
> > CPLDs. It uses an external clock and allows for daisy-chain
> configurations.
>
> CPLDs need no Configuration interface, since they are FLASH/EEPROM based.
> Once programmed (via JTAG), they keep their configuration also after
> power-off.
>
> --
> MfG
> Falk
>
>
>
>



Article: 44797
Subject: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 01 Jul 2002 10:41:07 -0700
Links: << >>  << T >>  << A >>
In CMOS, power consumption per node is proportional to the square of the supply
voltage (assuming full voltage swing), times the individual node capacitance,
times the frequency of that node's activity.
Xilinx can give you the first two factors with good accuracy.
The devil is in the node frequency. It is very difficult, if not impossible, to
capture the individual frequency of thousands ( make that tens of thousands) of
nodes. So it will be based on some generalizing estimates.
That is the ultimate limit to accuracy.
Simulation vectors do not necessarily have anything to do with average use
frequency.

Peter Alfke, Xilinx Applications

John Blaine wrote:

> Steven
>
> No they are not worst case.
>
> John
>
> Steven Derrien wrote:
>
> > Matthias Neuroth wrote:
> > >
> > > Steven,
> > >
> > > the accuracy level is dependent on the qualifier status. For the
> > > upcoming software release (5.1i), you can expect the following levels
> > >
> > >    * 10% for Spartan-II, Virtex and Virtex-E parts
> > >    * 20% for Spartan-IIe and Virtex-II parts
> > >
> > > Please keep in mind that the accuracy of the tool depends on a number of
> > > important factors. Some of these, for example activity settings data,
> > > have to be supplied by the user (guess, simulation data, etc).
> >
> > Are these worst case numbers ?
> >
> > Thanks,
> >
> > Steven derrien
> >
> > >
> > > Matthias Neuroth
> > >
> > > Steven Derrien wrote:
> > >
> > > > Hi,
> > > >
> > > >   Since my last post did not get any answer, and before I give up
> > > > I decided to try again ..
> > > >
> > > >   Are there any benchmark/figure/data regarding the accuracy of the
> > > > Xpower tool ?
> > > >
> > > > Steven Derrien


Article: 44798
Subject: Re: combine the Verilog code
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 01 Jul 2002 19:09:24 +0100
Links: << >>  << T >>  << A >>


John_H wrote:

> When you instantiate the lower level modules (m1, m2) in your top level module,
> you need to define the lower level ports in either an "Implicit Internal
> Connection" (ordered format) which doesn't care about the lower level port
> names, only the order, or an "Explicit Internal Connection" which uses the port
> names you've defined.  I hate to see the implicit because it's too easy to miss
> something - explicit allows me to see the names of the lower level ports.
>
> The top level module can have names that are unrelated or even contradictory to
> the names of the lower level modules.  The names can and often do change at the
> transition between hierarchy levels.
>
> An example might be:
>
> module top ( sysClk, in, out );
> input sysClk, in;
> output out;
> wire midsig;
>
> m1 first_stage ( .clk(sysClk), .in1(in), .out(midsig) );
> m2 last_stage ( .fastclk(sysClk), .in(midsig), .out(out) );
>
> endmodule
>
> The explicit callouts ".portname()" use top level wires within the parenthesis.
> The top level wires can be any valid Verilog wire name without consideration for
> the lower level module port names.  It all gets changed in the instantiation.
>
> There's also another newsgroup, comp.lang.verilog, for your continued coding
> pleasure.
>
>

If the OP uses emacs/xemacs the AUTOs in verilog-mode can help here and save a lot
of typing and tedious port mis-match errors. In the example above:

m1 first_stage(/*AUTOINST*/);

the ^C^A would get an explicit instantiation (assuming the m1 definition is in a
file m1.v in the same directory as top.v):

m1 first_stage (
.clk(clk),
.in1 (in1),
.midsig(midsig)
);

If, before the m1 instantiation, you also had a /*AUTOWIRE*/ then the ^C^A would
also add definitions for the signals connected to any output ports. For this to work
you need a disipline that modules input ports have the same name as the source
output port to which they are connected (but perhaps only a slice of the full
output). Even in the absence of that AUTOINST is a quick way of getting an
instantiation template which you can then edit.


Article: 44799
Subject: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Mon, 01 Jul 2002 11:12:03 -0700
Links: << >>  << T >>  << A >>
John,

To emphasize Peter's point (below),

How good are your simulation test vectors?

Where we find inaccuracy, we find lack of vectors.

Austin



John Blaine wrote:

> Steven
>
> No they are not worst case.
>
> John
>
> Steven Derrien wrote:
>
> > Matthias Neuroth wrote:
> > >
> > > Steven,
> > >
> > > the accuracy level is dependent on the qualifier status. For the
> > > upcoming software release (5.1i), you can expect the following levels
> > >
> > >    * 10% for Spartan-II, Virtex and Virtex-E parts
> > >    * 20% for Spartan-IIe and Virtex-II parts
> > >
> > > Please keep in mind that the accuracy of the tool depends on a number of
> > > important factors. Some of these, for example activity settings data,
> > > have to be supplied by the user (guess, simulation data, etc).
> >
> > Are these worst case numbers ?
> >
> > Thanks,
> >
> > Steven derrien
> >
> > >
> > > Matthias Neuroth
> > >
> > > Steven Derrien wrote:
> > >
> > > > Hi,
> > > >
> > > >   Since my last post did not get any answer, and before I give up
> > > > I decided to try again ..
> > > >
> > > >   Are there any benchmark/figure/data regarding the accuracy of the
> > > > Xpower tool ?
> > > >
> > > > Steven Derrien




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search