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Somebody else may comment on the Altera devices. With Xilinx Virtex you can do partial reconfiguration of individual or multiple frames, each a thin vertical strip (22 frames form one CLB column). So it will depend on the floorplanning, and on the location of the affected parameter locations. Any one frame can be read back, modified externally or internally, then written back. The change of the whole content of one frame will be "instanteneous", i.e. within a nanosecond (whether you change only one bit or the whole frame). Peter Alfke, Xilinx Applications =================================== Roberto Gallo wrote: > Hello again; > > I am developing one project that has many cores inside, but one of these > cores depends on dynamic parameters. At this point I have two possibilities: > 1st, program each parameter-dependent core inside my APEX20K200 and swicht > between as I need them. 2nd, option, the best, would be to reprogram only > *part* of my FPGA (kid of dynamic reconfiguration) depending on the > parameter. > Is there a good way to do that? or will I need to reprogram de entire > FPGA? > Letīs say that my static cores would use 70% of the FPGA and the > parameter-dependent ones would use each 20% while I could have as many as 10 > of these. > > Any clue will be appreciated. > Thank you. > > Roberto GalloArticle: 52051
Hi I am using avnet virtexE development board(ADS-XLX-VE-DEV) for my design prototyping. It has four devices in its JTAG chain,(ethnet,FPGA,video decoder, the other one I don't remember right now) when I use xilinx ise5 tools to configure the devices from my laptop, it fails most of the time, the tools complains about the chain,(it seems to be the video decoder),saying bit stream dosen't match etc. I have checked JTAG connection and the device configuration files and power supply carefully. The strange thing is some time it works when I quit the program and restart it again or turn off the power to the board and turn it on again, but most of time, it doesn't. So I wondered if someone had the same problem like this and could give some help or suggestions? -HongtuArticle: 52052
In article <3E384C05.C69BE503@xilinx.com>, Peter Alfke <peter@xilinx.com> wrote: >Somebody else may comment on the Altera devices. >With Xilinx Virtex you can do partial reconfiguration of individual or multiple >frames, each a thin vertical strip (22 frames form one CLB column). >So it will depend on the floorplanning, and on the location of the affected >parameter locations. >Any one frame can be read back, modified externally or internally, then written >back. The change of the whole content of one frame will be "instanteneous", >i.e. within a nanosecond (whether you change only one bit or the whole frame). I found this out from Ray Andraka: Also, in a Virtex, if your reconfiguration can be expressed as ONLY changing the contents of the LUTs, you can use SRL16s to shift in replacement values. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52053
Here's the application note in case anyone's interested in implementing partial reconfig on Xilinx part. (A detailed step by step instruction on what Peter has commented) http://support.xilinx.com/xapp/xapp290.pdf Regards, Wei Peter Alfke wrote: > Somebody else may comment on the Altera devices. > With Xilinx Virtex you can do partial reconfiguration of individual or multiple > frames, each a thin vertical strip (22 frames form one CLB column). > So it will depend on the floorplanning, and on the location of the affected > parameter locations. > Any one frame can be read back, modified externally or internally, then written > back. The change of the whole content of one frame will be "instanteneous", > i.e. within a nanosecond (whether you change only one bit or the whole frame). > > Peter Alfke, Xilinx Applications > =================================== > Roberto Gallo wrote: > > > Hello again; > > > > I am developing one project that has many cores inside, but one of these > > cores depends on dynamic parameters. At this point I have two possibilities: > > 1st, program each parameter-dependent core inside my APEX20K200 and swicht > > between as I need them. 2nd, option, the best, would be to reprogram only > > *part* of my FPGA (kid of dynamic reconfiguration) depending on the > > parameter. > > Is there a good way to do that? or will I need to reprogram de entire > > FPGA? > > Letīs say that my static cores would use 70% of the FPGA and the > > parameter-dependent ones would use each 20% while I could have as many as 10 > > of these. > > > > Any clue will be appreciated. > > Thank you. > > > > Roberto GalloArticle: 52054
Right you are! I did not want to overstay my welcome, considering I "gate crashed" an Altera question. One has become a little sensitive. :-) Peter ================== "Nicholas C. Weaver" wrote: > In article <3E384C05.C69BE503@xilinx.com>, > Peter Alfke <peter@xilinx.com> wrote: > >Somebody else may comment on the Altera devices. > >With Xilinx Virtex you can do partial reconfiguration of individual or multiple > >frames, each a thin vertical strip (22 frames form one CLB column). > >So it will depend on the floorplanning, and on the location of the affected > >parameter locations. > >Any one frame can be read back, modified externally or internally, then written > >back. The change of the whole content of one frame will be "instanteneous", > >i.e. within a nanosecond (whether you change only one bit or the whole frame). > > I found this out from Ray Andraka: > > Also, in a Virtex, if your reconfiguration can be expressed as ONLY > changing the contents of the LUTs, you can use SRL16s to shift in > replacement values. > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 52055
Hi, If you're using a Parallel-IV cable rather than a parallel-III cable from Xilinx I think now with the Parallel-IV you have the option of a ribbon cable or the flying leads. The software defaults to setting TCK at 5MHz if it detects a Parallel-IV cable but this is only good if using a ribbon cable. If flying leads you should try one of the clower settings. Hope it helps Derek <jianghongtu@hotmail.com> wrote in message news:b92f0d53.0301291403.3bdf9d11@posting.google.com... > Hi > I am using avnet virtexE development board(ADS-XLX-VE-DEV) for my > design prototyping. It has four devices in its JTAG > chain,(ethnet,FPGA,video decoder, the other one I don't remember right > now) when I use xilinx ise5 tools to configure the devices from my > laptop, it fails most of the time, the tools complains about the > chain,(it seems to be the video decoder),saying bit stream dosen't > match etc. I have checked JTAG connection and the device configuration > files and power supply carefully. The strange thing is some time it > works when I quit the program and restart it again or turn off the > power to the board and turn it on again, but most of time, it doesn't. > So I wondered if someone had the same problem like this and could give > some help or suggestions? > > > -HongtuArticle: 52056
Hey Antonio, Please see my comments below... Antonio Pasini wrote: > I'm at my first not trivial VHDL design, so probably this is really a stupid > question. > I tried to search FAQ, Xilinx website, and to experiment by myself, but now > I would like some suggestion from people more able than me.. I really tried to explain clock phase and how the requirement is calculated in the Timing Analyzer Help Topics. Please go to Help -> Help Topics. Looking at the contents look under Procedures -> Reports -> Understanding the Period Constraint. It explains how the requirement uses the arrival times of the source and destination clocks. > > Please take a look at this simple app; it's just the simplest source I could > post to show my problem. It's just an example, meaningless by itself. > I'm using ISE 5.1 + SP3, under XST; target is a Spartan IIE, XC2S100, -7. > > In my real app (video frame grabber/splitter/effects), I need to sample an > incoming digital video stream at every rising edge of "CLK_IN". > Internally I use a DLL to multiply it by two, to manage an sdram controller, > fifos, and video effects. > I need to know on wich of two consecutive rising edges of CLK 2X I have new > data coming from outside. > I'd prefer to use just CLK 2X signal in the whole design, and just use an > "enable" signal to mark edges to use for sampling external data, at half > CLK2X frequency. > > I know it's probably not the most elegant way, but... the 90 degrees clock > output (1X freq.) is low on CLK2X "sampling" rising edges, and high on "data > ready" CLK2X rising edges. I'm sure there are better way... but now I'm just > curious to understand why it doesn't works. Does it not work in the lab or does it not meet timing? > > If I use the CLK 90, and its inverted version, timing closure is okay. > If I use the CLK 270, and its inverted version, it fails timing closure. If you aren't using CLK270 as a clock, the timing tools don't know anything about it. I need to see the timing report to really figure out what is going on. > > Why ? CLK 90 and CLK 270 out from a DLL should one the inverted version of > the other, in first approx. > I tried to sample them with CLK2X... no avail. There might be a race condition or something like that going on. > > I'm using this simple .UCF constraint file: > > TIMESPEC "ts_clk_in" = PERIOD "clk_in_grp" 30 ns HIGH 50 %; # 27 Mhz > OFFSET = IN 10 ns BEFORE "clk_in"; # default pad to clk > OFFSET = OUT 16 ns AFTER "clk_in"; # default clk to out > NET "clk_in" TNM_NET = FFS "clk_in_grp"; > NET "clk_in" LOC = "p129"; # gck3 > > --------------------------- > > Seems that XST generates a "7.5 ns" requirement, but I don't understand why > just in one of the two cases. I am not sure what is going on. Again, I need to see the timing reports. > > That same requirement dissolves if I substitute the block ram with a bank of > FF. Why ? This should not matter either but I am not exactly sure what is going on. > > At the block ram input port, all signals are already synchronized to CLK2X; > why timing requirement should change so drastically ? I don't understand either since you aren't using CLK90 or CLK270 as a clock, just clock enables. > > With the same block ram that fails closure, if I generate the post P&R > timing report with > "advanced" and "verbose" option (so, it ignores the constraints), the "7.5 > ns" requirement disappears. The advanced option ignores all time constraints therefore it doesn't know the period of the CLKIN and it can't generated the new period of the CLK2X. This is why the 7.5ns disappears in the advanced option. In the verbose mode, the tools take the original 30ns period for the CLKIN and divides it by 2 to generate a 15ns clock period for CLK2X. My guess is there is a rising to falling edge path using CLK2X to generate the 7.5ns requirement. I need to see the timing reports to be sure. > > > I think I'm wrong in something very silly; perhaps the constraint > declarations... > > What's going on ?Article: 52057
Hi all,
It would be of great help if you could provide me with links from
where i can download models in verilog/vhdl for huffman coding scheme.
Thanks in advance
Regards
Rahul
Article: 52058Hi, I am a new to the RC100 board and would like to go some logging of the readings on the RC100 board. I tried using the Flash RAM, but so far I am unable to write into the Flash RAM and also upload the readings from the Flash RAM to my PC. I have tried the example given in the RC100 Function Library Manual. But I don't get the desired readings as well. Therefore I would like to find out how I can write values to the Flash RAM of the RC100 board and then upload these values to my PC for logging purposes. Thank you. Regards, StanleyArticle: 52059
Thanks Arash, I know this code works with ModelSim for functional verification but I really wanted to use the Quartus II environment for timing analysis of my existing design. I could write a .vec file but this means typing in all the other stimulus values which takes too long. Dave "Arash Salarian" <arash dot salarian at epfl dot ch> wrote in message news:<3e37fbc3$1@epflnews.epfl.ch>... > Hello, > > Generaly the simulator that comes with the vendor tools is not well suited > for such things. You'd better consider using something more advanced like > ModelSim. > > > "Dave Wilson" <da_wils@hotmail.com> wrote in message > news:6895fdb2.0301290641.fe11dd6@posting.google.com... > > Hello all, > > > > I'm having a problem reading some test data into my quartus ii design. > > > > The .txt file has a simple format of integers in a column :eg. > > > > 234 > > -3421 > > 21 > > etc .. . > > > > I created a new block in quartus for vhdl : > > > > LIBRARY ieee ; > > USE ieee.std_logic_1164.all; > > USE ieee.numeric_std.all; > > LIBRARY std ; > > USE std.textio.all; > > > > ENTITY Read_Vectors IS > > generic( > > Input_File : string := "c:\test_read_vectors_integer.txt" > > ); > > PORT( > > clk : IN std_logic; > > Ena : IN std_logic; > > Xout_Value : OUT signed (15 DOWNTO 0); > > ); > > END Read_Vectors ; > > ARCHITECTURE Version_1 OF Read_Vectors IS > > begin > > Read_in_Integer : process(clk, Ena) > > file X : TEXT open READ_MODE is input_file; > > variable L : line;-- line of file > > variable Xin_file_integer_value : Integer; > > begin > > if Ena = '0' then > > Xout_Value <=(others => '0'); > > elsif rising_edge(clk) and not endfile(X) then > > readline (X, L);--read input file > > read (L, Xin_file_integer_value); --read value from file > > Xout_Value <= to_signed(Xin_file_integer_value,16); > > end if; > > end process read_in_integer; > > end Version_1; > > > > My plan is to use Xout_Value as the input to my design. The problem is > > that I can't get this code to output the values under the quartus > > environment. Is there another way to achieve this ?Article: 52060
rahul_js53@yahoo.com (Rahul) wrote > It would be of great help if you could provide me with links from > where i can download models in verilog/vhdl for huffman coding scheme. What ist your application? Static Huffman Coding is dead simple. The trick is, to build it fast. We have a very fast static Huffman encoder that is ready to use. However, many applications require dynamic Huffman encoding. You can build code models that become arbitrarily complex to update. Anything specific that you want to encode/decode? Is this part of a JPG or MPEG application? Kolja Sulimma fpga.deArticle: 52061
Suppose I want to use one-hot encoding to implement a FSM, does it make sense if the register length is 192 (very long)?Article: 52062
You can start with an avalanche diode see http://positron.jfet.org/hw-rng.html or http://www.google.fr/search?num=3D100&hl=3Dfr&ie=3DUTF-8&oe=3DUTF-8&as_qd= r=3Dall&q=3Drandom+generator+noise+transistor&btnG=3DRecherche+Google&met= a=3D Roberto Gallo a =E9crit: > Hello gurus! >=20 > Does anyone have any ideia about how to create a *real* Random Numb= er > Generator using an APEX20K FPGA? If no, is there any IC that can do tha= t? > I would be very pleased if someone could give me at least some idea= s. >=20 >=20 > Thank you >=20 > Roberto Gallo >=20 >=20 >=20Article: 52063
What it could be? - When the element in the schematic editor was changed (removed one pin) the device continue to work as before change after implementation? - Or device begin works inproperly after adding the output control pin which do not connected anywhere (any change in scheme lead to different types of incorrect results in output of the device, and only sometimes it works properly)? (spartan 2, 2s150pq208, max freq 33 MHz)Article: 52064
"zhengyu" <zhengyu@attbi.com> wrote in message news:<nZ7_9.88966$rM2.46079@rwcrnsc53>... > Suppose I want to use one-hot encoding to implement a FSM, does it make > sense if the > register length is 192 (very long)? Sure, if you have plenty of registers. Since this tends to be the case with FPGAs, why not? 192 really isn't a very long chain anyhow. The alternative binary encoding would require decoding eight registers into the same 192 discrete states. It might save some area (less than you might think) but would cost a lot of propagation delay. So if you have plenty of area in your FPGA and are not trying to go for the ultimate in low dynamic power, one hot encoding will be fine.Article: 52065
I've looked through every datasheet I can think of and still can't come up with a clear answer to this. I've got a system that has a TI DSP processor, an EPC16, and an EPF50kE on board. On power-up the EPC16 programs the Flex10ke, but when the whole system is reset I want the flex to be reprogrammed. I'm actually taking the reset switch through the Flex10ke so that I can have some control over that signal at power-up, so what I'd like is some way to just use an output from the flex to initiate its own reconfiguration. However, I've been unable to glean if that is possible or not. I can't tell if this would be something I'd trigger via the flex or the EPC16 (I believe on Xilinx parts the programming device triggers the programming sequence), but I think it's something I trigger via the flex10ke. Is this possible, the datasheets seem to imply it is, but I can't really figure out how to do it. Thanks guys.Article: 52066
I have done a similar project and it does not work on every computer. 1. EPP signals are often not TTL compatible on some computers in EPP mode, 2. PCs motherboard chip set (or PP cable) does not work correctly on some PCs (e.g. when the transferred data change from 0x00 to 0xFF the EPP data_stobeN goes high even when waitN signal is still low) 3. some PC does not support EPP mode at all. 4. Transfer depends strongly on a PC you've got. You need not bother about the DMA - use a standard memory transfer unless your PC must do some other critical calculation. Good luck anyway Ernest Jamro Bob Fischer wrote: > I will be testing an FPGA design that is intended to drive a PC for > initial checkout and later to an embedded computer using parallel > port. I selected the EPP protocol as it looks like it can support > what I need to do. > > The FPGA will output 10 bytes of data to the PC each cycle of > operation. The data consists of five 14 bit values output in two > bytes each. The FPGA will be performing about 40,000 cycles per > second. Think of each cycle as a 25 us frame. Data collection (about > 4 us), processing (about 7-8 us) occurs for the first 11-12 us of each > frame. When the data is ready the parallel port Interrupt line is > asserted. > > The burst rate during the available 13 us data output portion is > around 770 Khz. The times have already been verified in the > simulations. For the simulation I used an 800 ns byte cycle. The > testbench emulates the PC by responding to the Interrupt, invoking the > byte cycle timing as expected from the PC by cycling the Data Strobe > line (400 ns low then 400 ns high for each byte). The FPGA responds > with Waits and presentation of data bytes at the time defined for the > EPP port. I used the timing found in web site > www.beyondlogic.org/epp/epp.htm > > The output of the FPGA is configured for TTL levels, slow transitions. > I intend to pipe the FPGA directly to the DB connector and through a > 3 ft parallel cable to the PC parallel port. > > In the PC we will DMA the data to memory and accumulate it for several > seconds. A display program will access that memory and generate > graphs, etc for visual analysis of the performance and results. > > Does this approach to PC interfaceing sound feasible? Has anyone out > there any prior experience they would like to share? Some Do's and > Don'ts? > > Bob Fischer > FPGA independent designerArticle: 52067
On Thu, 30 Jan 2003 23:06:10 +0100, Marc Van Riet <marcvanriet@yahoo.com> wrote:
>"Tim Olson" <mf0ttjk02@sneakemail.com> wrote in message
>news:<mf0ttjk02-20207E.09081329012003@central.isp.giganews.com>...
>>
>> A simple basic port [of gcc] (without working out all the subtle bugs) can be
>> done in a man-month or so. It depends upon how far you want to take it.
>> Also, you may want to ckeck msp430 port (mspgcc.sf.net) which is simple as
>well.
>>
>I've worked with the H8300. It's a great processor family, but waaayyyy more
>complicated than my core. The mps430 seems to be less complicated. I'm
>checking the ports out now to see if I can make sense of it.
I found "Porting GCC for Dunces" easy to read. But I haven't tried to
put it into practice. It covers the port to the ETRAX processor, which
may be about as simple as what you have in mind. Check it out.
ftp://ftp.axis.se/pub/users/hp/pgccfd/
- Larry
Article: 52068Hello, Well, you can export the post place&route verilog (usually runs much faster than VHDL on modelsim) version of the design (i.e. the gate level model) to ModelSim to have the timing analysis too. The other way is to use ModelSim (or even C) and write a program to generate that .vec file for you... Best Regards Arash "Dave Wilson" <da_wils@hotmail.com> wrote in message news:6895fdb2.0301300108.1f9a510d@posting.google.com... > Thanks Arash, > > I know this code works with ModelSim for functional verification but I > really wanted to use the Quartus II environment for timing analysis of > my existing design. > I could write a .vec file but this means typing in all the other > stimulus values which takes too long. > > Dave > > "Arash Salarian" <arash dot salarian at epfl dot ch> wrote in message news:<3e37fbc3$1@epflnews.epfl.ch>... > > Hello, > > > > Generaly the simulator that comes with the vendor tools is not well suited > > for such things. You'd better consider using something more advanced like > > ModelSim. > > > > > > "Dave Wilson" <da_wils@hotmail.com> wrote in message > > news:6895fdb2.0301290641.fe11dd6@posting.google.com... > > > Hello all, > > > > > > I'm having a problem reading some test data into my quartus ii design. > > > > > > The .txt file has a simple format of integers in a column :eg. > > > > > > 234 > > > -3421 > > > 21 > > > etc .. . > > > > > > I created a new block in quartus for vhdl : > > > > > > LIBRARY ieee ; > > > USE ieee.std_logic_1164.all; > > > USE ieee.numeric_std.all; > > > LIBRARY std ; > > > USE std.textio.all; > > > > > > ENTITY Read_Vectors IS > > > generic( > > > Input_File : string := "c:\test_read_vectors_integer.txt" > > > ); > > > PORT( > > > clk : IN std_logic; > > > Ena : IN std_logic; > > > Xout_Value : OUT signed (15 DOWNTO 0); > > > ); > > > END Read_Vectors ; > > > ARCHITECTURE Version_1 OF Read_Vectors IS > > > begin > > > Read_in_Integer : process(clk, Ena) > > > file X : TEXT open READ_MODE is input_file; > > > variable L : line;-- line of file > > > variable Xin_file_integer_value : Integer; > > > begin > > > if Ena = '0' then > > > Xout_Value <=(others => '0'); > > > elsif rising_edge(clk) and not endfile(X) then > > > readline (X, L);--read input file > > > read (L, Xin_file_integer_value); --read value from file > > > Xout_Value <= to_signed(Xin_file_integer_value,16); > > > end if; > > > end process read_in_integer; > > > end Version_1; > > > > > > My plan is to use Xout_Value as the input to my design. The problem is > > > that I can't get this code to output the values under the quartus > > > environment. Is there another way to achieve this ?Article: 52069
Dave Wilson wrote:
> Thanks Arash,
>
> I know this code works with ModelSim for functional verification but I
> really wanted to use the Quartus II environment for timing analysis of
> my existing design.
I use the Quartus static timing analyzer.
It does not require any stimulus.
> I could write a .vec file but this means typing in all the other
> stimulus values which takes too long.
Quartus does not support VHDL simulation.
Consider using synchronous design and static timing analysis
to verify timing.
Consider using a VHDL simulator first for
syntax and functional testing.
-- Mike Treseler
Article: 52070
Is there such a thing as an svf player that works with the xilinx
parallel cable (III)?
Uwe Bonnes wrote:
> Wayne <bigwayne@techie.com> wrote:
> : Never had any luck getting STAPL to work with Xilinx.
> : Altera STAPL works fine.
>
>
> Did you try with alteras jamplayer? I had to apply appended patch to get it
> to work with Xilinx generated STAPL files.
>
> Bye
>
> --- jamexec.c~ 2000-11-13 18:58:26.000000000 +0100
> +++ jamexec.c 2002-12-03 22:05:25.000000000 +0100
> @@ -816,6 +816,23 @@
> long *long_ptr = NULL;
> JAM_RETURN_TYPE status = JAMC_SUCCESS;
>
> + /* remove all white space */
> + while (statement_buffer[in_index] != JAMC_NULL_CHAR)
> + {
> + if ((!jam_isspace(statement_buffer[in_index])) &&
> + (statement_buffer[in_index] != JAMC_TAB_CHAR) &&
> + (statement_buffer[in_index] != JAMC_RETURN_CHAR) &&
> + (statement_buffer[in_index] != JAMC_NEWLINE_CHAR))
> + {
> + statement_buffer[out_index] = statement_buffer[in_index];
> + ++out_index;
> + }
> + ++in_index;
> + }
> + statement_buffer[out_index] = JAMC_NULL_CHAR;
> + in_index = 0;
> + out_index = 0;
> +
> while ((status == JAMC_SUCCESS) &&
> ((ch = statement_buffer[in_index]) != '\0'))
> {
>
Article: 52071Ryan Gammon <r.gammon@ns.sympatico.ca> wrote: : Is there such a thing as an svf player that works with the xilinx : parallel cable (III)? : Uwe Bonnes wrote: :> Wayne <bigwayne@techie.com> wrote: :> : Never had any luck getting STAPL to work with Xilinx. ... Ryan, is there any need to full quote my message? This quoting style makes the archives harder to search. naxjp http://member.nifty.ne.jp/nahitafu/naxjp/naxjp-e.html has some option regarding svf. I haven't tried it yet. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52072
Kate,
thanks for your suggestions.
In fact, the help pages of timing analyzer are very clearly written. Still
don't understand what happens...
Here is an extract of the timing report, when I enable the "NOTE 2" case
(the one that fails).
============================================================================
====
Timing constraint: TS_clk2x_int = PERIOD TIMEGRP "clk2x_int" ts_clk_in /
2.000000 HIGH 50.000 % ;
24 items analyzed, 9 timing errors detected.
Minimum period is 16.010ns.
----------------------------------------------------------------------------
----
Slack: -0.505ns (requirement - (data path - clock skew))
Source: bram1.B (RAM)
Destination: dout_12 (FF)
Requirement: 7.500ns <---------- why this ???? should
be 15 ns!
Data Path Delay: 8.005ns (Levels of Logic = 0)
Clock Skew: 0.000ns
Source Clock: clk2x rising at 22.500ns
Destination Clock: clk2x rising at 30.000ns
Data Path: bram1.B to dout_12
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB4_R0C0.DOB12 Tbcko 3.414 bram1
bram1.B
P125.O net (fanout=1) 3.528 ram_out<12>
P125.CLK Tioock 1.063 dout<12>
dout_12
------------------------------------------------- ---------------------
------
Total 8.005ns (4.477ns logic,
3.528ns route)
(55.9% logic, 44.1%
route)
What is really strange is:
- the blockram and the following flip flop are clocked by the same clock,
clk2x, with 15 ns period.
- substituting the blockram with FF all goes well.... !
- if I use, instead, CLK 90° output, negating it, all goes well, as you can
see below:
============================================================================
====
Timing constraint: TS_clk2x_int = PERIOD TIMEGRP "clk2x_int" ts_clk_in /
2.000000 HIGH 50.000 % ;
24 items analyzed, 0 timing errors detected.
Minimum period is 8.224ns.
----------------------------------------------------------------------------
----
[snip...]
----------------------------------------------------------------------------
----
Slack: 6.782ns (requirement - (data path - clock skew))
Source: bram1.B (RAM)
Destination: dout_12 (FF)
Requirement: 15.000ns
Data Path Delay: 8.218ns (Levels of Logic = 0)
Clock Skew: 0.000ns
Source Clock: clk2x rising at 0.000ns
Destination Clock: clk2x rising at 15.000ns
Data Path: bram1.B to dout_12
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tbcko 3.414 bram1.B
net (fanout=1) 3.741 ram_out<12>
Tioock 1.063 dout_12
---------------------------- ------------------------------
Total 8.218ns (4.477ns logic, 3.741ns route)
(54.5% logic, 45.5% route)
I'm really not qualified to state that, but seems a problem of timing
constraints.
> Does it not work in the lab or does it not meet timing?
I didn't try on the actual hw... hoping next days.
>
> > That same requirement dissolves if I substitute the block ram with a
bank of
> > FF. Why ?
>
> This should not matter either but I am not exactly sure what is going on.
Yes, I agree with you; should not matter...
> > At the block ram input port, all signals are already synchronized to
CLK2X;
> > why timing requirement should change so drastically ?
>
> I don't understand either since you aren't using CLK90 or CLK270 as a
clock,
> just clock enables.
Exactly.
Article: 52073Hi, How do you tell Quartus where to find the leonardo executable file so that it is able to launch it automatically? In the project settings, I assigned Leonardo as the synthesis tool but when I start the compiler, it cannot find Leonardo executable file. Thanks DavidArticle: 52074
All, I have noticed a difference between the xilinx floor planner tool and FPGA editor. In FPGA Editor the DCM's seem to be labeled (in a xc2v1000 part) DCM_X0Y0, DCM_X1Y0, DCM_X2Y0, DCM_X3Y0 (from left to right) and then on the top as DCM_X0Y1, DCM_X1Y1, DCM_X2Y1, DCM_X3Y1. I think that this is the correct notation, but when I open up the floor planner they are labeled as DCM_X0YO, DCM_X2Y0, DCM_X4Y0, DCM_X6Y0.......then on the top as DCM_X0Y1, DCM_X2Y1, DCM_X4Y1, DCM_X6Y1. This becomes a problem because I lock my DCM's to specific quadrants, and when i map one of them to DCM_X3Y0 it does not show up as being placed in the floor planner. Can anyone explain why this is? I am using Xilinx ISE version 5.1.02i. Also I am using engineering silicon, with the engineering silicon system variable set (XIL_BITGEN_VIRTEX2ES). Thanks in Advance, Mike
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