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Nope, this is Xilinx specific, and is the major advantage xilinx has over
altera's stratix. Stratix has small 512 bit memories associated with each
megalab which make up some but not all of the difference. You can insert keep
attributes on the outputs of each 16 deep rom to maintain the structure.
For the Dual port RAMs, you run into a problem reading and writing the same
address if the data is changing. See the Fast block ram updates thread where
this is currently being discussed.
Norbert Hermann Pramstaller - nhp wrote:
> Hi all,
>
> I work with the Spartan II and I need a small RAM (16x8). Due to the fact
> that one LUT provides a 16x1 synchronous RAM I only need 8 LUTs (2 CLBs)
> for the 16x8 RAM. By using this distributed LUT RAM I have all on-chip Block
> RAMs unused and that's what I want. But now my question: "Do other FPGAs,
> e.g. Altera, also provide this kind of LUT based RAM or is this feature
> Xilinx specific?
>
> Next I also need a ROM and as before I would like to implement it as a
> distributed ROM instead of using a Block RAM. During synthesis (ISE Webpack)
> XST detects the Rom but during optimization the ROM is replaced by Logic
> (MUXs). This depends on which values I define within the ROM. How can I turn
> off the optimisation for a single component in my VHDL code?
>
> Has somebody experience with Dual Port RAMs? I heard that concurrent reading
> and writing from/to the same address is problematic (not for simulation but
> for implementation)?
>
> Thx
>
> -Norbert
>
> --
> Norbert Hermann Pramstaller, Bakk.techn.
> Information and Communications Technology (ICT)
> Graz University of Technology
> Cell +43 664 1528612
> Cell +39 340 9833726
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52526Hi, I am trying to divide two 10 bit signed numbers, which represent fractional values. In order to use an integer divide, I scaled the numerator. However, this approach is producing very large register-register delays and I am getting clock skew warnings when I compile (Quartus with Flex 20k device). Does anybody have a suggestion for a good way to implement a fractional divide? Some of the floating point modules I've seen seem like overkill for this problem. jonArticle: 52527
Jon, how fast do you need the result? How many ns or clock ticks? Think of using the combinatorial multipliers available on some FPGAs... Peter Alfke, Xilinx Applications ============================= Jon Jacox wrote: > Hi, > > I am trying to divide two 10 bit signed numbers, which represent fractional > values. In order to use an integer divide, I scaled the numerator. However, > this approach is producing very large register-register delays and I am > getting clock skew warnings when I compile (Quartus with Flex 20k device). > Does anybody have a suggestion for a good way to implement a fractional > divide? Some of the floating point modules I've seen seem like overkill for > this problem. > > jonArticle: 52528
The multiplier can be done multi-cycle with a scaling accumulator, which
will get you a high clock rate but will take multiple clocks per multiply to
complete. You can pipeline the unrolled multiplier. If you use the partial
products approach (see my website), you get 2 bits per partial product, each
partial product output can be registered with the ff in that slice, then the
adder tree can also be pipelined at each layer.
Kuan Zhou wrote:
> Hi,
> I am designing a butterfly processor.But the issue is the professor
> wants to pipeline on each CLB stage so he can get the maximum speed.Since
> butterfly processor is manily consisted of adders and multipliers,I have
> to design the bit-level adder.The multiplier is made too big because the
> clock rate is the propogation delay of a single CLB.Does anyone have any
> suggestions?
>
> Thank you very much!
>
> sincerely
> -------------
> Kuan Zhou
> ECSE department
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52529Hal Murray wrote: > > >> Been a long time microcontroller man, but I'd really like to start > >> getting into fpga's. Can anyone recommend good starting places? Good > >> books? > > How much hardware background do you have? If not much, then try to > find a friend who does know hardware to give you a quick lesson. > You need to understand the timing limitations - what setup, hold, > and prop times mean. And about clock skew. You can probably do > it in 10-30 minutes at a white board. Work out a few examples, > like a counter or a state machine. Figure out how fast they will > run. (Look up the numbers for LS or HC chips.) I'm a technically a sophmore computer engineer (UMCP), although i'd already accumulated a sizable if slightly uneven electrical background knowledge before college. Admitantly, I'm more of a software guy. *duck* I understand the fundamentals of timing, although my applicable knowledge thereof is significantly lacking: see virtually non-existant. Sadly, its usually just a case of I plug in my 75 mhz oscillator and my microcontroller runs. MattArticle: 52530
I'm about to finish murking through the entry level courses. Already finished the one 200 level digital logic design course, whee, now i can build state machines, counters, and a variety of other useless nonesense. I realize this isnt really adequate for real FPGA design, but I'd like to get a head start. I have this sense that they'll take their fair share of time to understand even the basics of FPGA's at any decent level, and I think that getting a head start on that will allow me to turn the digital logic design courses I will soon be taking to use in the FPGA world. Is this at all true, or should I wait a semester or two before I begin learning? Thanks Matt Ray Andraka wrote: > > Depends on your hardware background. FPGA design _IS_ digital hardware > design, not programming. if you don't have a hardware background, the first > step is learn about digital design. There are important concepts to do with > timing, asynchronous operation, concurrency, etc that are quite foriegn to > the software world. You can get lucky and get something that works (at > least most of the time) without a firm basis, but you are alse very likely > to trip over one of these without even knowing it. Most of these are not > covered or are covered fairly far into an entry level digital logic design > course, so you really need to go a little deeper than introductory level > learning.Article: 52531
I'm working on a design that needs to output signals up to 155 MHz. I'm trying to use a Coolrunner II, but the output doesn't seem fast enough. I'm using 3.3V I/O and when I try to simply output my 155 MHz input clock, I get a waveform that stays up around 3.3V. It sort of wiggles a few tenths of a volt at the right frequency, but never even makes it below 3 V. I've uploaded a crude sketch showing the waveform here: http://www.fastclan.com/members/griz/155MHz.gif I've played around with adding a BUFG and/or an OBUF, but the output still looks the same. I've also tried using the LVTTL and 33LVCMOS output types, but again, it always looks the same. The only way I can get a more or less acceptable output is to us an open drain output with a *strong* pullup resistor (like 200 Ohms). I'm fairly sure that the clock is making it into the part OK, because I tried putting in a counter to divide down the clock, and those outputs looked OK. Does anyone know if a Coolrunner II (-5 speed grade 2C64VQ100) outputs should be able to work at this frequency? (The rise and fall times in the data sheet seem to indicate that it should.) Given the symptoms I describe, what might the problem be? Some sort of power issue? TIA -BrianArticle: 52532
Brian wrote: > > I'm working on a design that needs to output signals up to 155 MHz. > I'm trying to use a Coolrunner II, but the output doesn't seem fast > enough. > > I'm using 3.3V I/O and when I try to simply output my 155 MHz input > clock, I get a waveform that stays up around 3.3V. It sort of wiggles > a few tenths of a volt at the right frequency, but never even makes it > below 3 V. I've uploaded a crude sketch showing the waveform here: > http://www.fastclan.com/members/griz/155MHz.gif > > I've played around with adding a BUFG and/or an OBUF, but the output > still looks the same. I've also tried using the LVTTL and 33LVCMOS > output types, but again, it always looks the same. The only way I > can get a more or less acceptable output is to us an open drain output > with a *strong* pullup resistor (like 200 Ohms). > > I'm fairly sure that the clock is making it into the part OK, because > I tried putting in a counter to divide down the clock, and those > outputs looked OK. > > Does anyone know if a Coolrunner II (-5 speed grade 2C64VQ100) outputs > should be able to work at this frequency? (The rise and fall times in > the data sheet seem to indicate that it should.) Given the symptoms > I describe, what might the problem be? Some sort of power issue? CPLDs typically have a SLEW control bit, so you could check that ? The simplest test for what you describe is to lower the 155MHz IP clock - if the waveform appears/improves below a certain freq, then yes, you can confirm that with your settings the CR-II cannot output 155MHz. Most chips can clock faster than they can output. -jgArticle: 52533
Brian <usenet@carlsonclan.com> wrote: : I'm working on a design that needs to output signals up to 155 MHz. : I'm trying to use a Coolrunner II, but the output doesn't seem fast : enough. : I'm using 3.3V I/O and when I try to simply output my 155 MHz input : clock, I get a waveform that stays up around 3.3V. It sort of wiggles : a few tenths of a volt at the right frequency, but never even makes it : below 3 V. I've uploaded a crude sketch showing the waveform here: : http://www.fastclan.com/members/griz/155MHz.gif : I've played around with adding a BUFG and/or an OBUF, but the output : still looks the same. I've also tried using the LVTTL and 33LVCMOS : output types, but again, it always looks the same. The only way I : can get a more or less acceptable output is to us an open drain output : with a *strong* pullup resistor (like 200 Ohms). : I'm fairly sure that the clock is making it into the part OK, because : I tried putting in a counter to divide down the clock, and those : outputs looked OK. : Does anyone know if a Coolrunner II (-5 speed grade 2C64VQ100) outputs : should be able to work at this frequency? (The rise and fall times in : the data sheet seem to indicate that it should.) Given the symptoms : I describe, what might the problem be? Some sort of power issue? Some things: - make sure that your probe doesn't disturb the signal - What does the synthesis and timeing report tell you about speed - Did you tell the synthesizer and placer to go for speed - think about another IO Standard, using a lower swing (e.g. GTL) Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52534
I am working on the creation of a vision application and I need to create a card with a Spartan IIE or equivalent. I am looking for a tutorial that explain the needs of a such cards (Type of ROM, timings, start levels) ThanksArticle: 52535
Hello, I am trying to cause a break to occur by executing a VHDL statement, in Modelsim (I do not want to use breakpoints, they are not convenient/flexible enough IMHO). Assert statements are supposed to do something like this, but using severity ERROR just prints a message, without stopping, while FAILURE really kills Modelsim. Are there other ways? Thank you for your help, Frederic (fba@free.fr)Article: 52536
I have used the xilinx webpack to do a verilog design for a 9536XL I know this is probably RTFM but I coulnd't find it, how do I set the slew rate and switch it to low power mode (as opposed to high speed mode)? Thanks RalphArticle: 52537
Peter Wallace <pcw@karpy.com> wrote in message news:<pan.2003.02.08.16.50.09.431921.59634@karpy.com>... > On Thu, 06 Feb 2003 18:48:40 -0800, Theron Hicks (Terry) wrote: > > > Hi, > > I am looking at design upgrade of an existing instrumentation > > project. Currently the design talks over a high speed bus to a rather > > expensive (~$1600 US) parrallel digital input board. The data rate > > would be on the order of 50M bits per second not including any overhead. > > I do not think I want to go to an all FPGA based solution. Currently > > the FPGA in the system is the smallest Spartan2e series device. By the > > way, quantities are very small, on the order of less than 50 pieces per > > year. > > > > So here are my questions... > > > > 1. Does anyone happen to know what the USB2 or firewire is rated for > > in terms of the longest cable length? I had thought USB2 was limited to > > about 2 meters but I have seen USB cables about 5 meters long recently. > > A longer length interconnect would appear to be desireable. I know that > > ethernet is good for several hundred meters. That would be far beyond > > my needs. > > > > 2. Has anyone had any experience with either USB2 or 100mB or > > firewire as an interconnect to an FPGA based design? > > > > 3. Do you happen to have any recommendations as to a possible > > off-the-shelf solution (either a small board or a 1 or two chip > > solution, ideally something with a demo board available)? > > > > Thanks, > > Theron Hicks > > > Since it looks like you just need a point to point (full duplex?) link, > why not just use a 100BT Ethernet PHY. You do not need an Ethernet MAC in > your FPGA at all since you are only doing a simple point-point link, > just the simple machinery to send and recieve nibbles from the PHY... > > Using 100BT Ethernet physical layer has the advantage of long > inexpensive cables (50 meters?) and electrical isolation > > Not sure what the PLL sync delay in the PHY is so you probably > want to be sending fairly large packets to reduce the % of overhead... From a cost/speed perspective, I doubt you can do better than Peter's suggestion. In fact, for not much more money, you could probably run GbE (and maybe reduce the chance of your part going obsolete so soon). MarcArticle: 52538
Hi, You are welcome to check out the SJSU EE178 (Designing with Xilinx FPGAs) class website at http://www.engr.sjsu.edu/crabill/ This material is targeted at students who have completed an introduction to digital design and are familar with schematic design (no HDL or synthesis). We've been using the 2.1i student edition with some FPGA prototyping boards from Digilent, Inc. Next semester, we'll be moving up to 4.2i student edition and some more current hardware. Maybe some Verilog, too, for good measure. If you are looking for reading material, I think this stuff is more than adequate. You'll find some labs/projects that are reasonable and also entertaining. Sincerely, Eric Crabill Matthew Fowle wrote: > > I'm about to finish murking through the entry level courses. Already > finished the one 200 level digital logic design course, whee, now i can > build state machines, counters, and a variety of other useless > nonesense. > > I realize this isnt really adequate for real FPGA design, but I'd like > to get a head start. I have this sense that they'll take their fair > share of time to understand even the basics of FPGA's at any decent > level, and I think that getting a head start on that will allow me to > turn the digital logic design courses I will soon be taking to use in > the FPGA world. > > Is this at all true, or should I wait a semester or two before I begin > learning? > > Thanks > Matt > > Ray Andraka wrote: > > > > Depends on your hardware background. FPGA design _IS_ digital hardware > > design, not programming. if you don't have a hardware background, the first > > step is learn about digital design. There are important concepts to do with > > timing, asynchronous operation, concurrency, etc that are quite foriegn to > > the software world. You can get lucky and get something that works (at > > least most of the time) without a firm basis, but you are alse very likely > > to trip over one of these without even knowing it. Most of these are not > > covered or are covered fairly far into an entry level digital logic design > > course, so you really need to go a little deeper than introductory level > > learning.Article: 52539
Ok for my senior design class id like to build a digital voice/sound recorder. Most people in my class seem to be very good at analog componets so they are building it using discrete componnts to make the lpf and sample/hold. I wanted to know if it would be possible to do this project using a fpga (sorta like a dsp). If so Id also like to know how much of it would be able to be done with it So as to limit my components. I am going to have to buy the Altera UP-1X board for another class and was also wondering if i would be able to use this board for this project. Thanks BTW any help in the way of advice or links i could get on this project would be great (i dont really know much about analog)Article: 52540
Easy! (if you've spent the last 2 years on and off working with the PCI bus :-) This is off the top of my head as my spec is at work but... I think (no warranties giiven etc) The latency timer timer is something the OS programs into the function to tell it the maximum number of clocks it may use the bus before it's supposed to give it up (if it has lost a grant - if it still has the grant then it can carry on freely) The Min Grant is something you as a designer of the function hard code into the register set to give the OS a hint as to what you would like your latency timer to be - likewise the max latency (this is the bit I'm not sure of without checking my spec) is a hint to the OS of what it should set the other latency timers in the system too. e.g. imagine a fifo in your function that is getting filled, you want to tell the OS how long you would like the bus for in order to empty it from full. You also want to tell it how long other people are allowed to use the bus for before your fifo will be full and therefore will have to have the bus again - specifying a max latency will cover this option too! Hope that helps/is correct - I'll try and remember to check tomorrow Chris "praveen" <praveenkumar1979@rediffmail.com> wrote in message news:ff8a3afb.0302100437.4fa2fc1d@posting.google.com... > Hello Sirs/friends > I wanted to know the difference between latency timer, min_gnt > register and max_lat_register in the configuration register. This all > are with regard to master. what is the weightage of each bit in that > register. > > please reply > waiting for reply > Thanks in advance > praveenArticle: 52541
Ok for my senior design class id like to build a digital voice/sound recorder. Most people in my class seem to be very good at analog componets so they are building it using discrete componnts to make the lpf and sample/hold. I wanted to know if it would be possible to do this project using a fpga (sorta like a dsp). If so Id also like to know how much of it would be able to be done with it So as to limit my components. I am going to have to buy the Altera UP-1X board for another class and was also wondering if i would be able to use this board for this project. Thanks BTW any help in the way of advice or links i could get on this project would be great (i dont really know much about analog)Article: 52542
> > I know this is probably RTFM but I coulnd't find it, how do I set the slew > rate and switch it to low power mode (as opposed to high speed mode)? > You create a user constraints file and use the "slow" and "pwr_mode" constraints. See the following: http://toolbox.xilinx.com/docsan/xilinx5/manuals.htm and select "Libraries Guide" then "Architecture Specific Information". Select the appropriate family and then scroll to the bottom. It will list the constraints an has link to them. OR... you can add them to your verilog source. Detailed examples are shown for either method. It is really quite painless. Regards, MattArticle: 52543
oh yeah, I forgot to mention that you can set fast/slow from the constraints editor... it's under "ports" and then "I/O configuration options" check box. I didn't see anything for power mode though. "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:QGz2a.84084$F63.1737506@news.xtra.co.nz... > I have used the xilinx webpack to do a verilog design for a 9536XL > > I know this is probably RTFM but I coulnd't find it, how do I set the slew > rate and switch it to low power mode (as opposed to high speed mode)? > > Thanks > Ralph > >Article: 52544
On Wed, 12 Feb 2003 22:30:53 +0100, "Frederic Bastenaire" <frederic.bastenaire@wanadoo.fr> wrote: >Hello, > >I am trying to cause a break to occur by executing a VHDL statement, in >Modelsim (I do not want to use breakpoints, they are not convenient/flexible >enough IMHO). >Assert statements are supposed to do something like this, but using severity >ERROR just prints a message, without stopping, while FAILURE really kills >Modelsim. >Are there other ways? Modelsim allows you to select the "severity level" used to break the simulation, so instead of just printing a message it will stop simulating. BTW, FAILURE shouldn't "really kill Modelsim;" you should be able to continue the simulation with run -continue Regards, Allan.Article: 52545
You are doing it right! Go for the head start, it will help reinforce what you
are learning in your classes and at the same time you will be getting some
practical hands on. The timing isn't going to bite you on simple designs.
Asynchronous interfaces likely will, but then it will be an excellent learning
experience in a controlled environment. Much better here, than finding out (or
not) on a product that has already shipped to customers. BTW, those state
machines and counters become important when you start doing real things, perhaps
not the simple cases you've done, but those still encapsulate much of what real
designs do.
Matthew Fowle wrote:
> I'm about to finish murking through the entry level courses. Already
> finished the one 200 level digital logic design course, whee, now i can
> build state machines, counters, and a variety of other useless
> nonesense.
>
> I realize this isnt really adequate for real FPGA design, but I'd like
> to get a head start. I have this sense that they'll take their fair
> share of time to understand even the basics of FPGA's at any decent
> level, and I think that getting a head start on that will allow me to
> turn the digital logic design courses I will soon be taking to use in
> the FPGA world.
>
> Is this at all true, or should I wait a semester or two before I begin
> learning?
>
> Thanks
> Matt
>
> Ray Andraka wrote:
> >
> > Depends on your hardware background. FPGA design _IS_ digital hardware
> > design, not programming. if you don't have a hardware background, the first
> > step is learn about digital design. There are important concepts to do with
> > timing, asynchronous operation, concurrency, etc that are quite foriegn to
> > the software world. You can get lucky and get something that works (at
> > least most of the time) without a firm basis, but you are alse very likely
> > to trip over one of these without even knowing it. Most of these are not
> > covered or are covered fairly far into an entry level digital logic design
> > course, so you really need to go a little deeper than introductory level
> > learning.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 52546Hi, You can put the RLOCs in a separate constraints file (.NCF) that will be read in during the translate (ngdbuild) stage. Inferred components may not have consistent names between synthesis runs, so it is suitable for use only on instantiated components. Depending on how much optimisation your design requires it may be easier to use Area Groups to help the PAR. These constrain a set of primitives to a region in the chip, allowing you to floorplan the design at a high level. RLOCs are better suited to small critical blocks that need to be placed in a specific way to route at maximum speed. cheers, Chris "Peter Baltazarovic" <baltazarovic@"nospam"ncode.sk> wrote in message news:<b2dd7g$5i6$1@at-vie-newsmaster01.nextra.at>... > Hi, > > is it possible to floorplan design written in verilog/Mentor HDL > Designer? I use Leonardo for synthesis and Xilinx ISE 4.2 for > Transl/Map/P&R. My problem is that I have to add new functionality to > existing design (Spatan2-150 ) and I need to make existing design run > faster. The design takes now 80% of FPGA. I know that I can assign RLOCs to > instantiated components like LUTs, FFs, IOBs ... but how can I do this in > Verilog? Is there any way to tell P&R tools that: "I want this 64x16 RAM to > be placed here and this counter there." ? I don't like the work that > automatical PAR does. And I noticed that it does different place each time i > PAR the design. I need to have control of PAR proces. > > Can anybody help? > > > All answers are greatly appreciated. > > > PeterArticle: 52547
www.opencores.org have a hardware divider which would be suitable with some modifications Chris "Jon Jacox" <jjacox@NULLpmdi.com> wrote in message news:<Lsw2a.240803$Yo4.9500000@news1.calgary.shaw.ca>... > Hi, > > I am trying to divide two 10 bit signed numbers, which represent fractional > values. In order to use an integer divide, I scaled the numerator. However, > this approach is producing very large register-register delays and I am > getting clock skew warnings when I compile (Quartus with Flex 20k device). > Does anybody have a suggestion for a good way to implement a fractional > divide? Some of the floating point modules I've seen seem like overkill for > this problem. > > jonArticle: 52548
hello, i am working with an old vhdl library which is only available in xnf format. my problem is now that the xilinx WebPack Classic (4.2i) only supports edif files as input. i know that on the commandline the ngdbuild executable accepts also xnf files, but i would prefer to work with the IDE. now my first question is if there is a program which can convert the xnf files into edif files. i did already a search on google but did not find a downloadable executable. and my second question is whether i loose some information when i convert to edif? many thanks for any hints! -- Christian SchuheggerArticle: 52549
Dear Frederic,
On Wed, 12 Feb 2003, Frederic Bastenaire wrote:
> I am trying to cause a break to occur by executing a VHDL statement, in
> Modelsim (I do not want to use breakpoints, they are not convenient/flexible
> enough IMHO).
> Assert statements are supposed to do something like this, but using severity
> ERROR just prints a message, without stopping, while FAILURE really kills
> Modelsim.
> Are there other ways?
Perhaps you can use the "when"-command. It performs a user defined action when
the conditions are met.
Example:
"when { /testbench/STOP_VSIM == '1' } { stop }"
Best wishes,
Lars.
--
GnuPG public key:
http://www.ida.ing.tu-bs.de/~larsu/larsu_ida_ing_tu-bs_de.key
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