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Messages from 53425

Article: 53425
Subject: Xilinx ISE sometimes seems to use old edf-file
From: "Andreas Purde" <purde@ei.tum.de>
Date: Thu, 13 Mar 2003 11:37:05 +0100
Links: << >>  << T >>  << A >>
Hi,

has anybody made similar experiences:

Xilinx ISE (Version 5.1i) sometimes seems to use an old version of my
edf-file generated by Synplicity. Only removing the file from the project
and then adding it again helps.

Thank you very much.

Andi



Article: 53426
Subject: Re: Bus Functional Model
From: Andreas Gieriet <andreas.gieriet@externsoft.ch>
Date: Thu, 13 Mar 2003 13:23:53 +0100
Links: << >>  << T >>  << A >>
Brendan Lynskey schrieb:
> 
> Generally an RTL model, right? No timing info?
> 

BFMs are used in verification where one wants to have other components talking
to the unit-under-test (UUT). Since the "other" components serve as
communication counterparts only to the UUT, they can be quite simple.

I usually design them as behavioural models (in contrast to RTL), i.e., I don't
model the HW - I model the *behaviour*, regardless of how such a HW would look
like - it's not physically built anyway.

The only relevant function of the BFM is talking on the bus - one can add
more or less intelligent content to the talk, though ;-)

Cheers

Andi

--
Andreas Gieriet             mailto:andreas.gieriet@externsoft.ch
eXternSoft GmbH             http://www.externsoft.com/
Zurlindenstrasse 49         phone:++41 1 454 3077
CH-8003 Zurich/SWITZERLAND  fax:  ++41 1 454 3078

Article: 53427
Subject: AMD Temp Specs
From: "ArtO" <arm777@(spam-not)sockets.net>
Date: Thu, 13 Mar 2003 07:05:08 -0600
Links: << >>  << T >>  << A >>
Can anyone tell me some spechs for AMD processors in terms of heat ranges.
I plan on building a system with a 2200 or 2400 CPU and a GeForce4200 video
card.  At this point I am trying to find a case.  I like the Antec Sonata,
but am a little concerned about heat dissapation with only one (though
large) fan.

I'm looking for ambient system temps, and specific processor temps or any
other info I can find.  Someone using this case (I know it's very new) would
be great.

Thanks in advance

Art



Article: 53428
Subject: Re: [Xilinx] Looking for Parallel Cable III ...
From: pgayer@hotmail.com (Pat G.)
Date: 13 Mar 2003 05:22:03 -0800
Links: << >>  << T >>  << A >>
I have done this using the schematic given, but still am not able to
configure my PLD using JTAG. I am using a serial cable instead of the
Ribbon cable to connect to my board. Does this make a difference? it
is only 1.8m long. I receive an error 1208: check scan-chain, power
supplies and cable connections.
Any ideas?????






"Noddy" <g9731642@campus.ru.ac.za> wrote in message news:<1047541744.960502@skink.ru.ac.za>...
> Why don't you build one yourself? It will, for a start, be between 50 and
> 100 times cheaper, and should only take you about half an hour or so to put
> together (just need a couple HC125 tristate buffers)... the schematic is
> floating around somewhere...
> 
> adrian
> 
> 
> 
> Markus Meng <meng.engineering@bluewin.ch> wrote in message
> news:3e7035f9_4@corp.newsgroups.com...
> > Hi all,
> >
> > where can I get or buy the 'good old' simple JTAG Download Cable
> > type "Parallel Cable III"?
> >
> > Xilinx does support it but does not sell it anymore ...
> >
> > markus
> >
> > --
> > Mit freundlichen Grüssen
> > Markus Meng
> >
> > P.S. Achtung wir haben eine neue FAX-Nummer
> > ********************************************************************
> > ** Meng Engineering        Telefon    056 222 44 10               **
> > ** Markus Meng             Natel      079 230 93 86               **
> > ** Bruggerstr. 21          Telefax    056 222 44 34 <-- NEU !!    **
> > ** CH-5400 Baden           Email      meng.engineering@bluewin.ch **
> > **                         Web        www.meng-engineering.ch     **
> > ********************************************************************
> > ** You cannot create experience. You must undergo it. Albert Camus**
> >
> >
> >
> >
> >
> >
> >
> > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
> > http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
> > -----==  Over 80,000 Newsgroups - 16 Different Servers! =-----

Article: 53429
Subject: Re: [Xilinx] Looking for Parallel Cable III ...
From: Jens Hildebrandt <jens.hildebrandt@etechnik.uni-rostock.de>
Date: Thu, 13 Mar 2003 14:22:09 +0100
Links: << >>  << T >>  << A >>
If you insist on buying a Parallel Cable III instead of building one yourself 
(as others suggested and I would suggest, too) go to Avnet. They sell a Parallel 
Cable similar in shape to the original Xilinx cable for $99, IIRC.

HTH,
Jens

Markus Meng wrote:
> Hi all,
> 
> where can I get or buy the 'good old' simple JTAG Download Cable
> type "Parallel Cable III"?
> 
> Xilinx does support it but does not sell it anymore ...
> 
> markus
> 
> --
> Mit freundlichen Grüssen
> Markus Meng
> 
> P.S. Achtung wir haben eine neue FAX-Nummer
> ********************************************************************
> ** Meng Engineering        Telefon    056 222 44 10               **
> ** Markus Meng             Natel      079 230 93 86               **
> ** Bruggerstr. 21          Telefax    056 222 44 34 <-- NEU !!    **
> ** CH-5400 Baden           Email      meng.engineering@bluewin.ch **
> **                         Web        www.meng-engineering.ch     **
> ********************************************************************
> ** You cannot create experience. You must undergo it. Albert Camus**
> 
> 
> 
> 
> 
> 
> 
> -----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
> http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
> -----==  Over 80,000 Newsgroups - 16 Different Servers! =-----


Article: 53430
Subject: Re: [Xilinx] Looking for Parallel Cable III ...
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Thu, 13 Mar 2003 15:35:04 +0200
Links: << >>  << T >>  << A >>
Yes... you might start by using a parallel cable...or are you just talking
in generic terms? (I presume you are still plugging into parallel port on
CPU!). Does your board have the parallel cable header on it? If you are
going to make the header, probably a good idea to put it as close to the
chip as possible. The length of the cable shouldn't make much of a
difference, as long as you don't set the JTAG clock too quickly (and cause
packet collisions...). What board are you using? Is this by any chance the
digilent board? (plugging a "serial" cable into the board sounds very
familiar)

adrian


Pat G. <pgayer@hotmail.com> wrote in message
news:3b7d0733.0303130522.7162b339@posting.google.com...
> I have done this using the schematic given, but still am not able to
> configure my PLD using JTAG. I am using a serial cable instead of the
> Ribbon cable to connect to my board. Does this make a difference? it
> is only 1.8m long. I receive an error 1208: check scan-chain, power
> supplies and cable connections.
> Any ideas?????
>
>
>
> "Noddy" <g9731642@campus.ru.ac.za> wrote in message
news:<1047541744.960502@skink.ru.ac.za>...
> > Why don't you build one yourself? It will, for a start, be between 50
and
> > 100 times cheaper, and should only take you about half an hour or so to
put
> > together (just need a couple HC125 tristate buffers)... the schematic is
> > floating around somewhere...
> >
> > adrian
> >
> >
> >
> > Markus Meng <meng.engineering@bluewin.ch> wrote in message
> > news:3e7035f9_4@corp.newsgroups.com...
> > > Hi all,
> > >
> > > where can I get or buy the 'good old' simple JTAG Download Cable
> > > type "Parallel Cable III"?
> > >
> > > Xilinx does support it but does not sell it anymore ...
> > >
> > > markus
> > >
> > > --
> > > Mit freundlichen Grüssen
> > > Markus Meng
> > >
> > > P.S. Achtung wir haben eine neue FAX-Nummer
> > > ********************************************************************
> > > ** Meng Engineering        Telefon    056 222 44 10               **
> > > ** Markus Meng             Natel      079 230 93 86               **
> > > ** Bruggerstr. 21          Telefax    056 222 44 34 <-- NEU !!    **
> > > ** CH-5400 Baden           Email      meng.engineering@bluewin.ch **
> > > **                         Web        www.meng-engineering.ch     **
> > > ********************************************************************
> > > ** You cannot create experience. You must undergo it. Albert Camus**
> > >
> > >
> > >
> > >
> > >
> > >
> > >
> > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
> > > http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
> > > -----==  Over 80,000 Newsgroups - 16 Different Servers! =-----



Article: 53431
Subject: Homemade Xilinx Parallel JTAG Download Cable
From: pgayer@hotmail.com (Pat G.)
Date: 13 Mar 2003 05:46:46 -0800
Links: << >>  << T >>  << A >>
Hi, 
I'm currently trying to configure a CPLD (XC9536 PC44) on my PCB using
the ISE Webpack software (Win 2k), through the JTAG interface, using a
homemade Xilinx parallel download cable. This cable is based on the
xilinx.com schematics. After making the cable, the software recognises
the cable is connected to the parallel port, but will not allow me to
configure my device, displaying the error shown below.
I followed the schematics, but i have used a serial printer cable to
connect the parallel port to the cable i have made. This homemade
cable is then connected to my JTAG pins on my PCB.
Is it ok to use this serial cable?
I have already checked all power supplies.
ANY IDEAS PLEASE????????


ERROR:iMPACT:1208-'1': Boundary-scan chain test failed at bit position
'1'.
A problem may exist in the hardware configuration. Check that the
cable, scan-chain, and power connections are intact, that the scan
chain configuration matches the actual hardware, and that the power
supply is adequate and delivering the correct voltage.

Article: 53432
Subject: Re: Homemade Xilinx Parallel JTAG Download Cable
From: "Giuseppe³" <miaooaim@inwind.it>
Date: Thu, 13 Mar 2003 15:24:37 +0100
Links: << >>  << T >>  << A >>

I fix a similar problem with IJC-2 JTAG cable in the follow mode:

In my board I've put a capacitor of 100pF nearest the TDO pin.
Then I've open the JTAG interface and remove the capacitor labeled C1.

In my opinion the R9-C1 filter is too big.

Hope to be usefull
Giuseppe

"Pat G." <pgayer@hotmail.com> ha scritto nel messaggio
news:3b7d0733.0303130546.27fd4900@posting.google.com...
> Hi,
> I'm currently trying to configure a CPLD (XC9536 PC44) on my PCB using
> the ISE Webpack software (Win 2k), through the JTAG interface, using a
> homemade Xilinx parallel download cable. This cable is based on the
> xilinx.com schematics. After making the cable, the software recognises
> the cable is connected to the parallel port, but will not allow me to
> configure my device, displaying the error shown below.
> I followed the schematics, but i have used a serial printer cable to
> connect the parallel port to the cable i have made. This homemade
> cable is then connected to my JTAG pins on my PCB.
> Is it ok to use this serial cable?
> I have already checked all power supplies.
> ANY IDEAS PLEASE????????
>
>
> ERROR:iMPACT:1208-'1': Boundary-scan chain test failed at bit position
> '1'.
> A problem may exist in the hardware configuration. Check that the
> cable, scan-chain, and power connections are intact, that the scan
> chain configuration matches the actual hardware, and that the power
> supply is adequate and delivering the correct voltage.



Article: 53433
Subject: Re: AMD Temp Specs
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Thu, 13 Mar 2003 09:44:53 -0500
Links: << >>  << T >>  << A >>
On Thu, 13 Mar 2003 08:05:08 -0500, ArtO wrote:

> Can anyone tell me some spechs for AMD processors in terms of heat
> ranges. I plan on building a system with a 2200 or 2400 CPU and a
> GeForce4200 video card.  At this point I am trying to find a case.  I
> like the Antec Sonata, but am a little concerned about heat dissapation
> with only one (though large) fan.
> 
> I'm looking for ambient system temps, and specific processor temps or
> any other info I can find.  Someone using this case (I know it's very
> new) would be great.
> 
> Thanks in advance
> 
> Art
 
You'll find all of that on AMD's site

http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs

AMD specs max junction temp at 85C. You'll have to look at you cooler
manufacturer's site to determine the rise for you particular cooler.

Article: 53434
Subject: Re: The structure of the multiplier
From: Ray Andraka <ray@andraka.com>
Date: Thu, 13 Mar 2003 15:18:36 GMT
Links: << >>  << T >>  << A >>
The coregen multipliers use the computed partial products technique
described on the multipliers page (under DSP) on my website.

Peng Cong wrote:

> Hello
>     I'm working on a research project that use Xilinx Virtex FPGA,
> I use the Coregen tool to generate multiplier, it works very well.
>     But I wonder where can I find the details about the structure
> of the multiplier.
>     Thanks for any advance.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53435
Subject: Re: RESET --- Synchronous Vs Asynchronous
From: Ray Andraka <ray@andraka.com>
Date: Thu, 13 Mar 2003 15:27:33 GMT
Links: << >>  << T >>  << A >>
It is because an asynchronous reset is by definition asynchronous to your
clock.  The important event for reset is not the application of reset,
rather it is the release of reset.  An async reset released near a clock
edge will be seen by some flip-flops in the circuit at the current edge,
by others at the next edge.  Unless you are very careful, you can easily
get into an unintended state.  A second issue is that the reset
propagation path does not stop at the flip-flop you are resetting because
it affects the flip-flop immediately.  Instead, it propagates through the
logic after the flip-flop until it encounters a clocked input to a
flip-flop.  This can make timing verification difficult, especially
considering many of the timing analysis tools do not consider the reset
path through a flip-flop.

With FPGAs, the reset distribution delays can be greater than a clock
period, so even global synchronous resets need to be treated with care.

Thomas Stanka wrote:

> Peter Alfke <peter@xilinx.com> wrote:
>
> > > which reset is better synchronous or asynchronous
> >
> > Synchronous is better if:
>
> could you be so kind and explain why you (and others in thios thread)
> think that synchronous reset ist better?
>
> Reset is IMO a feature to ensure, your cirquit starts in a
> deterministic behavior and when ever necessary can be put back in this
> state by an external controller.
> Especially during power up, you have no garantie of a determinsitic
> clock so you lack a deterministic synchronous reset, while an
> asynchronous reset during powerup is very easy.
> No I like to know, what drawbacks exist, that I don't have in mind.
>
> bye Thomas

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 53436
Subject: Re: footprints
From: Lizard Blizzard <NOSPAM@rsccd.org>
Date: Thu, 13 Mar 2003 08:01:12 -0800
Links: << >>  << T >>  << A >>
Why are you posting to so many off-topic groups?


Mike Hubert wrote:
> Hi,

> I am about to get started on the design of a board containing two Xilinx 
> FPGAs: a Virtex II, and a VirtexII Pro, both in FG256 packages.

> I am looking for a footprint source for these components... may it be a 
> friendly individual, or a company. I checked with ECS and they don't have 
> them. I know designing them myself wouldn't be too much of a pain but the 
> fact of the matter is that we are extremely pressed for time and have to 
> save every minute I can!

> Any tips would be greatly appreciated.

> Thanks

> Mike Hubert
> Xiphos Technologies Inc.

> Montreal, Canada


-- 
----------------(from OED Mini-Dictionary)-----------------
PUNCTUATION - Apostrophe
Incorrect uses: (i) the apostrophe must not be used with a plural
where there is no possessive sense, as in ~tea's are served here~;
(ii) there is no such word as ~her's, our's, their's, your's~.

Confusions: it's = it is or it has (not 'belonging to it'); correct
uses are ~it's here~ (= it is here); ~it's gone~ (= it has gone);
but ~the dog wagged its tail~ (no apostrophe).
----------------(For the Apostrophe challenged)----------------
 From a fully deputized officer of the Apostrophe Police!


Article: 53437
Subject: Re: Cyclone power up problem
From: gregs@altera.com (Greg Steinke)
Date: 13 Mar 2003 08:13:20 -0800
Links: << >>  << T >>  << A >>
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<TP5aa.79536$AV5.998926@news.chello.at>...
> I've built a board with the Cyclone from Altera. First board was ok, but on
> some of the following there was a problem with startup of the Cyclon.
> 
> For the core voltage (1.5V) I use a drop-down regulator from Linear
> Technology (LTC3405) as described in the app. note (AN257). But the core
> voltage did not reach the 1.5V. The regulator stopped at 0.5 - 0.8 V. I
> examined the problem by building an extern regulator.
> 
> Starting the regulator without load and than attaching the VCCINT pins from
> the FPGA leads to a successfull start. The output capacitor (4u7) supplies
> enough initial current.
> 
> Measuring the current during startup yields to following results:
> First few us the Cyclone needs about 0.7A! Falling down to 200 mA and
> staying there for about 15 us (I think for internal startup). After that it
> dropps to a few mA.
> The LCT3405 is a 300 mA regulator with a peak current of about 650 mA. It
> can not deliver this peak current during it's own start.
> 
> Just wanted to tell this story (of hidden problems of a new family) for
> others who want to work with this new (still exciting) FPGAs to not run into
> the same troubles.
> 
> Martin Schoeberl

Martin,
The highest power-up current requirement that we have characterized
for the Cyclone family is 420 mA. This is more than the LTC3405 can
supply, and we are modifying AN257 accordingly. Also, we will document
the requirement for power-up current in the Cyclone datasheet. I'm not
sure why you are seeing more current than we saw - in some cases the
decoupling caps can also take some transient current as they charge
up, but I would not think that this would be 300 mA.
Later posts indicate that you have solved this problem. If you have
any other questions about this feel free to contact me.
Sincerely,
Greg Steinke
Altera Corporation
gregs@altera.com

Article: 53438
Subject: Re: write a single byte in to DRAM
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Thu, 13 Mar 2003 16:28:38 +0000
Links: << >>  << T >>  << A >>
On Thu, 13 Mar 2003 07:07:25 GMT, "zhengyu" <zhengyu@attbi.com> wrote:

>Hello,
>
>  I am just wondering if it is possible to write a single byte in memory,
>then write another single byte right next to it.
>Normally I would pre-append two bytes into a word of 32 bit wide, then do a
>single write to the memory. But is it possible to write it byte by byte,
>instead all at once.  Assuming 32 bit memory bus width.
>

www.micron.com has data sheets for a variety of DRAM types.

Look up the functionality of the DQM control signals.

- Brian


Article: 53439
Subject: Re: Help understanding 7408 and gate chip
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Thu, 13 Mar 2003 16:28:46 +0000
Links: << >>  << T >>  << A >>
On Thu, 13 Mar 2003 00:27:33 GMT, "Glen Herrmannsfeldt"
<gah@ugcs.caltech.edu> wrote:

>
>"john jakson" <johnjakson@yahoo.com> wrote in message
>news:adb3971c.0303111811.5737b3ac@posting.google.com...
>(snip question about TTL and ESD protection)
>>
>> In fact TTL was so tough as old boots, there are Fairchild stories
>> that Chinese fabs used to make ripoff TTL in fabs where the air
>> conditioning was an open window.
>>
>> By the way this is the wrong NG, and the wrong century.
>
>Which newsgroup do you suggest, comp.arch.ttl?

oh goody...

can we have a comp.arch.tube as well?

- Brian


Article: 53440
Subject: Re: Help understanding 7408 and gate chip
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Thu, 13 Mar 2003 08:44:34 -0800
Links: << >>  << T >>  << A >>
Brian,

Already have a place for "hollow state devices"......

http://home.wxs.nl/~frank.philipse/frank/frank.html

Austin

Brian Drummond wrote:

> On Thu, 13 Mar 2003 00:27:33 GMT, "Glen Herrmannsfeldt"
> <gah@ugcs.caltech.edu> wrote:
>
> >
> >"john jakson" <johnjakson@yahoo.com> wrote in message
> >news:adb3971c.0303111811.5737b3ac@posting.google.com...
> >(snip question about TTL and ESD protection)
> >>
> >> In fact TTL was so tough as old boots, there are Fairchild stories
> >> that Chinese fabs used to make ripoff TTL in fabs where the air
> >> conditioning was an open window.
> >>
> >> By the way this is the wrong NG, and the wrong century.
> >
> >Which newsgroup do you suggest, comp.arch.ttl?
>
> oh goody...
>
> can we have a comp.arch.tube as well?
>
> - Brian


Article: 53441
Subject: Re: [Xilinx] Looking for Parallel Cable III ...
From: kolja@bnl.gov (Kolja Sulimma)
Date: 13 Mar 2003 08:57:15 -0800
Links: << >>  << T >>  << A >>
If you want to built your own parallel downbload cable search this
newsgroups to read about the problems with the Xilinx schematic and
how to fix them.

Most important: Select a HC125 with a low threshold voltage and use a
resistor between input and output of the buffers to build a
schmitt-trigger.

Kolja Sulimma

Article: 53442
Subject: Re: Buying memory for FPGA...
From: kolja@bnl.gov (Kolja Sulimma)
Date: 13 Mar 2003 09:03:39 -0800
Links: << >>  << T >>  << A >>
For 15€ you get a Fujitsu micrcontroller with 256KByte Flash.
For 30€ you get a 64MHz, 32-Bit Processor with 768kB Flash.
Price for a single piece, no lead time.

You can write your own software to make it JTAG-programmable, or you
implement PPP and upload your bitstreams via FTP ;-)

Does anybody besides me think that the FPGA configuration flash-ROMs
are overpriced?

Kolja Sulimma

zumbita00@yahoo.es (Pepito Perez) wrote in message news:<441d2f16.0303121138.568f4a23@posting.google.com>...
> Hello,
> 
>     I bought while ago two FPGA from Altera, they are called APEX and
> ACEX, their distributor sent me both FPGA, but... they came without
> memory, i have talked to them and they said they could sell me memory,
> and it is almost as expensive as FPGA. They gave me this prices:
> 
> EPC1PC8 or EPC2LC20    for EP1K50,(ACEX)
> EPC2LC20               for EP1K100.(APEX)
> 
> EPC2LC20.Altera
> -price 21,59 eu.
> - This one is JTAG programable.
> 
> EPC1PC8.Altera.
> -price 7,12 eu.
> 
> Are this good prices ? Add sending and taxes...its in euro, almost
> like dollar.
> 
> Anyways, it's the first time i buy this things, i don't know if they
> are being nice or being too smart...what do you think ?
> 
> Could I use another memory for my FPGA ? What tipe would you recommend
> me ?
> 
> Thank you !

Article: 53443
Subject: Re: Homemade Xilinx Parallel JTAG Download Cable
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 13 Mar 2003 18:04:19 +0100
Links: << >>  << T >>  << A >>
"Giuseppe³" <miaooaim@inwind.it> schrieb im Newsbeitrag
news:b4q49b$227b6i$1@ID-61213.news.dfncis.de...
>
> I fix a similar problem with IJC-2 JTAG cable in the follow mode:
>
> In my board I've put a capacitor of 100pF nearest the TDO pin.
> Then I've open the JTAG interface and remove the capacitor labeled C1.
>
> In my opinion the R9-C1 filter is too big.

IMHO the schematics of the parallel-III cable is a little bit senseless. I
added two Schmitt triggers (74HC14) BEFORE the TCK line. The input to the
first schmitt-trigger is filterd by a RC filter consisting of 330 Ohms and 1
nF. This works well on a 3m long cable. Since there are 4 more buffers free
inside the chip, I buffer TDI and TMS the same way. But TCK (which becomes
CCLK in serial slave mode) is by far the most critical signal. So keep the
connetion from the 74HC125 (tristate driver) to the TCK pin on the board
short, lets say < 10cm (4 inch for the non-SI guys ;-)

--
MfG
Falk





Article: 53444
Subject: Re: [Xilinx] Looking for Parallel Cable III ...
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Thu, 13 Mar 2003 18:07:37 +0100
Links: << >>  << T >>  << A >>
"Noddy" <g9731642@campus.ru.ac.za> schrieb im Newsbeitrag
news:1047562681.664309@skink.ru.ac.za...
> Yes... you might start by using a parallel cable...or are you just talking
> in generic terms? (I presume you are still plugging into parallel port on
> CPU!). Does your board have the parallel cable header on it? If you are
> going to make the header, probably a good idea to put it as close to the
> chip as possible. The length of the cable shouldn't make much of a
> difference, as long as you don't set the JTAG clock too quickly (and cause
> packet collisions...). What board are you using? Is this by any chance the

Guys, be carefull. Clock frequncy is NOT the critical point, its edge rate
(rise/fall time). And the parallel port delivers damm POOR signals. These
slow, noisy, glitch signals mess yup the PLD (FPGHAs as well as CPLDs) since
these chips are DAMM!!! fast and DO react to ns wide glitches. Do use
schmitt-triggers to clean up at least the clock signal, As I said in my
other posting.

--
MfG
Falk





Article: 53445
Subject: Re: RESET --- Synchronous Vs Asynchronous
From: Mike Treseler <tres@fluke.com>
Date: Thu, 13 Mar 2003 09:55:19 -0800
Links: << >>  << T >>  << A >>


Clyde R. Shappee wrote:
> Is this kind of what you have in mind?   I have been doing synchronous 
> resets for a while, but based on your post, I bullet proofed it a little...
> Here is a component that takes an asynchronous reset and asserts it 
> asynchronously, but deasserts it synchronously.

Yes. That's what I had in mind.
If you fix up the :in and :out on the ports,
it will even compile.

     -- Mike Treseler


Article: 53446
Subject: Re: Adding delay to a signal?
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 13 Mar 2003 10:07:12 -0800
Links: << >>  << T >>  << A >>
In Virtex-II you can specify a clock delay of n/256 of the clock period
( limited to a granularity of ~50 picoseconds ). That solves your problem.
For most other delays the ratio between max and min is >2, which makes
any compensation attempts pretty useless. 

Peter Alfke, Xilinx Applications 
=====================
Igor Orlovich wrote:
> 
> I have a project which need sto interface to a system with fairly rigid
> timing specs. As a result I need to delay my signals coming that way a
> certain number of nS whiich is not a multiple of any clock I have in the
> chip. Is there any way I can add some propagation delay/gate delay and not
> have it optimized out by the XST tools. Or alternatively, is there a way to
> specify not only the max delay between signals, but also the min one?
> Thanks for any suggestions

Article: 53447
Subject: Re: RESET --- Synchronous Vs Asynchronous
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 13 Mar 2003 10:17:52 -0800
Links: << >>  << T >>  << A >>
Thomas, the classical problem that has been debated here "ad nauseam":
The leading edge of  asynchronous reset during power-up is o.k.
But the trailing edge will not reach all flip-flops at the same time,
since it is not distributed with low skew,( and even if it were, its
arrival could still straddle a clock edge).
So you inevitably end up with some, but not all flip-flops staying reset
beyond a certain clock edge. This can have bad consequences, especially
in one-hot state machines ( just as an example).

Peter Alfke
================================
Thomas Stanka wrote:
> 
> Peter Alfke <peter@xilinx.com> wrote:
> 
> > > which reset is better synchronous or asynchronous
> >
> > Synchronous is better if:
> 
> could you be so kind and explain why you (and others in thios thread)
> think that synchronous reset ist better?
> 
> Reset is IMO a feature to ensure, your cirquit starts in a
> deterministic behavior and when ever necessary can be put back in this
> state by an external controller.
> Especially during power up, you have no garantie of a determinsitic
> clock so you lack a deterministic synchronous reset, while an
> asynchronous reset during powerup is very easy.
> No I like to know, what drawbacks exist, that I don't have in mind.
> 
> bye Thomas

Article: 53448
Subject: Altera Sourcing
From: khimbittle@cliftonREMOVEsystems.com (KB)
Date: Thu, 13 Mar 2003 18:18:34 GMT
Links: << >>  << T >>  << A >>
hello folks ... being more of a xlinix user of recent years and not
purchasing altera we are considering using altera for some new designs
... but I see the altera website lists only arrow under US
distribution ... so does this mean EVERYONE buys ALL of their altera
parts from arrow ?  or am I missing something ... it seems the single
distributor model would be a reason NOT to move to altera since I am
sure the  only reason we ( small company ) get good pricing on xilinx
is because there are three big local distributors in town ( plus
internet distributors ) who all carry xilinx ... and I think we get
good pricing because of this .. mmmm any thoughts, thanks KB



Article: 53449
Subject: What is the diff between FPGA and CPLD?
From: santa19992000@yahoo.com (Santa)
Date: 13 Mar 2003 10:24:12 -0800
Links: << >>  << T >>  << A >>
Guys,

what is FPGA?. Also what is the difference between FPGA, CPLD and
ASIC?. Especially the functionality diff between ASIC and FPGA?.
Thanks in advance.



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