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Xilinx Application Note 151 talks about partial reconfiguration with SelectMAP or JTAG interfaces; does this mean that's not possible to do partial reconfiguration with a serial interface? Lorenzo Dal BelloArticle: 58626
Austin Lesea wrote: > All, > > Please take advantage of the fact that we have IBIS models, and there are IBIS simulators out there! > > Any such question can be easily answered by simulating the IO standard, the pcb traces, and the loading at the end of > the traces. Can anybody recommend a good starting point for this sort of stuff? I'm heading into a board design with fairly (very?) unusual topology - none of the examples in the SI/EMC books I've got seem particularly appropriate, so I'm thinking I'll need to do some simulations, but don't really know how to get started. Cheers, JohnArticle: 58627
"Michael Petry" <micpetry@web.de> ha scritto nel messaggio news:oprs0r81ezsntlns@news.dlan.cinetic.de... > I'm looking for a programing interface (cheap, > selfmade)for a xilinx FPGA > (e.g. XCS10-3). Parallel programmer IV costs 99$ on the Xilinx web shop, and programs everything, including the new configuration flashes. I think it's worth the price: you can indeed build an interface from yourself (there is a schematic on Xilinx site), but it will cost 10-20$ just of components, plus the time you will put in it. -- LorenzoArticle: 58628
"Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> ha scritto nel messaggio news:bg5cbd$6rk$1$8302bc10@news.demon.co.uk... > I quite like Mark Zwolinski's book "Digital System Design > with VHDL" > (Prentice-Hall). It's aimed at undergraduates but it's > very clear > and good to read, and quite focused about what does and > doesn't > make sensible hardware. If you are really interested in > creating > hardware, you may also care to look at Andrew Rushton's > "VHDL for > Logic Synthesis" (Wiley); personally I like the style, > and it's > particularly good on design for synthesis. Do you know some books more focused to a specific vendor (i.e. Xilinx)? I have a couple of "generic" VHDL books, but often I have to spend a lot of time seeking some "vendor dependent" informations here and there on the Internet. A comprehensive guide would be very useful. > - VHDL is strongly typed, and obsessive about static > compile-time checks. This often leads to what many > perceive to be excessive verbosity. [...] One drawback of VHDL compared to "pure software" languages is the lack of multi-line comments. Maybe the inventor of VHDL thought that one line would have been just enough for everything. :) -- LorenzoArticle: 58629
John, I recommend you get Mentor's Hyperlynx IBIS simulation tools. These are some of the best value/$ tools that are out there. Once you have these tools, you can do what if simulations of what you think you want to do, and see if it works. After you finish the layout, you can extract the pcb parameters, and model the actual traces, and see if that works, and make the necessary changes to make it work well before the board is fabricated. After the board is built, and you find a problem (should not happen if you simulated everything, but maybe you missed one path...) then you can see how to fix it without having to hack the pcb. Austin John Williams wrote: > Austin Lesea wrote: > > All, > > > > Please take advantage of the fact that we have IBIS models, and there are IBIS simulators out there! > > > > Any such question can be easily answered by simulating the IO standard, the pcb traces, and the loading at the end of > > the traces. > > Can anybody recommend a good starting point for this sort of stuff? > > I'm heading into a board design with fairly (very?) unusual topology - > none of the examples in the SI/EMC books I've got seem particularly > appropriate, so I'm thinking I'll need to do some simulations, but don't > really know how to get started. > > Cheers, > > JohnArticle: 58630
Paul Leventis wrote: >>How specific to Altera is this book? > > Not at all. I am mostly exposed to Xilinx kit at the moment so it makes sense to continue with that initially. Thank you very much for your insight Paul. I have played with VHDL before but never had the opportunity or reason to learn that I do now - software is my main interest but I want to be able to understand hardware and hardware engineers(!) at the most in depth possible level. > Looking through the book again for the first time in a few years, my take on > it is that it is first a book about digital design (intro to digitial logic, > arithmetic techniques, FSMs, etc.) and only an intro to VHDL, with the most > useful/basic subset of the language introduced. Sounds quite reasonable though. I studied Computer Science but perhaps really would have benefitted from a mixture of Electronic Engineering... > Once you go through that book, a more thorough reference on the VHDL itself > would be useful to flush out your knowledge of the complete language. I am quite sure I will play on your good nature further and ask for advice at that point! :-). Jon.Article: 58631
Hi, Thanks to those who responded with regard to my book recommendations post previously. I should now like to ask if anyone knows what is the current state of play with regard to the Handel C compiler? Jon.Article: 58632
Hi Jon, Jon Masters wrote: > I should now like to ask if anyone knows what is the current state of > play with regard to the Handel C compiler? AFAIK it is still in active development, as part of Celoxica's DK suite. Queries about Handel-C here in comp.arch.fpga seem to be on the decrease - no idea why that is. The concensus seems to be that there may certainly be a value in synthesis tools from C-like languages, however to design good hardware you need to write your Handel-C with a hardware design in mind *from the outset*. That is, if you just take random C code, don't expect to produce great hardware just by cranking it through the Handel-C synthesis tools. At this point the HDL gurus jump in and say "well if you have to think about hardare design from the beginning, you might as well just write the thing in VHDL/Verilog/whatever". So, maybe Handel-C should be thought of as an HDL with C-like syntax. I have philosophical issues with a synthesisable HDL that permits language constructs like pointers. Here's an example. Last I looked, Handel-C permits pointer variables, and pointer dereferencing. Say you declare an array of some 10 elements of a datatype (let's say bytes for convenience). byte myarray[10]; byte *ptr = myarray; AFAIK this is all legal and synthesisable Handel-C syntax. Now, you can dereference ptr, and you can also increment it. So far I'm happy, the synthesis tools can just implement the array as an addressable register or something like that. However, what happens when you increment "ptr" past the last element in the array, and then dereference it? Then you face the fact that it's not *really* a pointer, it's just a syntactic construct that *looks* like a pointer, and in limited set of circumstances will *act* like a pointer. Right about now my brain caves in thinking about what it would really mean to have a pointer in an FPGA... Anyway sorry I digress... I haven't had time to explore Handel-C in any depth, although the lab here has a license for DK1.1 or whatever it is up to now. If you are part of a university I think Celoxia are pretty generous with licenses. They have a hardware board (RC1000?) that goes with it, presumably with lots of reference designs showing off the highlights of Handel-C and so on. Hope I'm not misrepresenting anyone with my summary! :) JohnArticle: 58633
Presumably, this is for an FPGA application. If you are using one of the newer
ones, you can use the dedicated multipliers provided you haven't already used
them up for something else. To construct a multiplier in the fabric, I'd suggest
you visit the multipliers page on my website for a tutorial on the structures
that make sense for an FPGA. That should at least give you a starting point.
prasad wrote:
> I am designing QAM chip.
> I want know hardware for 2's complement parallel multiplier(12bit by 12 bit).
> can any body know plz help me.
> Thank you and best regards.
> prasad
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 58634Hi Austin, Austin Lesea wrote: > I recommend you get Mentor's Hyperlynx IBIS simulation tools. These are some of the best value/$ tools that are out there. Thanks, I'll check it out. The uni may already have a license - that would be nice! > After you finish the layout, you can extract the pcb parameters, and model the actual traces, and see if that works, and > make the necessary changes to make it work well before the board is fabricated. Do you know of any packages that can do SI modelling across connector structures, for example modelling mezzanine / daughter board architectures? Here's why I ask: we're considering stackable memory "modules" for the platform we're developing (think PC104+ for FPGAs and you're part way there), but I've been warned off trying to put SDRAM (pref. DDR) anywhere except on the main board nice and close to the FPGA. Obviously this problem can be solved - case in point being commodity DDR SDRAM modules in desktop PCs. But whether mere mortals can do it - that's what I need to know before we get too far into the design. Cheers, JohnArticle: 58635
"Jason Berringer" <look_at_bottom_of@email.com> wrote in message news:kJCVa.3413$Cx4.543634@news20.bellglobal.com... > Hello, I have attached a portion of code for a binary to bcd counter, 20 > bits parallel input, and a 24 bit BCD output parallel. Although internally > it converts it to serial to go through the conversion. I'm attempting the > shift and add three (if greater than or equal to 5) method, but I am having > some problems. It works great on the simulator (Aldec Active HDL) and I can > synthesize it but when I put it on the chip I'm getting some odd things. I > am using 16 input toggle switches and i debounced pb switch as a load > switch, and my outputs are LEDs. When I set this up on the board my outputs > go as follows: The attachment didn't come through. Can you just include some of the code in the body, instead of an attachment? -- glenArticle: 58636
Hi,
I was wondering if someone could help me with -ve delay number
associated with a DCM in the TRCE report. How is this number
calculated ? If I try to do a timing simulation of this
design, how can I calculate this delay before-hand ?
Thanx in advance.
---- Ab.
I am attaching a sample path report below.
--------------------------------------------------------------------------
Clock Path: clk_PN to t2
Location Delay type Delay(ns) Physical
Resource
Logical
Resource(s)
-------------------------------------------------
-------------------
IOB.I Tiopi 0.653 clk_PN
clk_PN
d1_u1
DCM.CLKIN net (fanout=1) e 0.100 d1_clk_int
DCM.CLK0 Tdcmino -2.131 d1_u2
d1_u2
BUFGMUX.I0 net (fanout=1) e 0.100 d1_clk_dcm
BUFGMUX.O Tgi0o 0.465 d1_u3
d1_u3.GCLKMUX
d1_u3
SLICE.CLK net (fanout=3) e 0.100 c1
-------------------------------------------------
---------------------------
Total -0.713ns (-1.013ns
logic, 0.300ns route)
--------------------------------------------------------------------------------
Article: 58637"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:MzFVa.9078$cF.2637@rwcrnsc53... > > "Jason Berringer" <look_at_bottom_of@email.com> wrote in message > news:kJCVa.3413$Cx4.543634@news20.bellglobal.com... > > Hello, I have attached a portion of code for a binary to bcd counter, 20 > > bits parallel input, and a 24 bit BCD output parallel. Although internally > > it converts it to serial to go through the conversion. I'm attempting the > > shift and add three (if greater than or equal to 5) method, but I am > having > > some problems. It works great on the simulator (Aldec Active HDL) and I > can > > synthesize it but when I put it on the chip I'm getting some odd things. I > > am using 16 input toggle switches and i debounced pb switch as a load > > switch, and my outputs are LEDs. When I set this up on the board my > outputs > > go as follows: > > The attachment didn't come through. Can you just include some of the code > in the body, instead of an attachment? OK, it did come through but I was looking in the wrong place. Still, it is often easier just to include it. I am much better at reading verilog than VHDL, but it doesn't look right to me. Though I think I don't understand the algorithm, I think it needs to be more complicated than that, though if you do an iterative algorithm it might not be so hard. How many clock cycles does it take to get the data from input to output? How many different values did you put through the simulator in testing? -- glenArticle: 58638
Hi, I am currently trying to perform a readout from FPGA to a LINUX PC using parallel port. I have implemented the state-machine for EPP communication in the FPGA and it works well however the system is slow. I think this is because EPP devices are supposed to negotiate the best available transfer mode during initialization but the FPGA is not currently setup to do that. As a result, I had to fall back on software emulation of the data transfer handshaking. I was wondering if anyone has experience performing readout from FPGA using EPP. My aim is to get 1MByte/sec communication. Any help would be appreciated. Thanks, -Yash _______________________________________________________________________________ Yash Bansal High Energy Physics University of California, Davis _______________________________________________________________________________Article: 58639
Here is the code (after my text) instead of an attachment in case others
cannot read it.
It takes (or should take) 20 to 21 clock cycles to get the data from the
input to the output. I put a few numbers through the simulation the only
correct values are 0 and 1, all other tested were incorrect. I'm pretty sure
it's a simple error that I'm not catching, I just can't see it at present.
Most of the stuff that I have done has been a bit more simple than this. The
algorithm works from a sample I've seen (no code just an explanation). Start
by shifting the most significant bit of your binary number into the least
significant bit of your "units" bcd value, when the number in the "units"
value is 5 or greater add 3 to it. Shift again, if the value is 5 or greater
add 3 to it, the values will continue to spill over to the "tens",
"hundreds", "thousands", etc. You must add 3 to each of the bcd digits if
any is five or greater, by the last shift (same number of shifts as your
input binary value (in my case 20 bits)) you'll have the bcd representation.
The example I mentioned above was for a microcontroller.
Code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bin2bcd is
port(
clk : in std_logic;
reset : in std_logic;
load_data : in std_logic;
data_in : in std_logic_vector(19 downto 0);
data_ready : out std_logic;
data_out : out std_logic_vector(23 downto 0)
);
end bin2bcd;
architecture behaviour of bin2bcd is
signal ser_out_s : std_logic;
signal shift_en_s : std_logic;
signal data_ready_s : std_logic;
signal count_s : std_logic_vector(4 downto 0);
signal bin_in_s : std_logic_vector(19 downto 0);
signal bcd_out_s : std_logic_vector(23 downto 0);
begin
process (reset, clk) begin
if reset = '1' then
count_s <= (others => '0');
shift_en_s <= '0';
data_ready_s <= '0';
elsif rising_edge(clk) then
if load_data = '1' then
count_s <= (others => '0');
shift_en_s <= '1';
elsif count_s = "10011" then
count_s <= (others => '0');
shift_en_s <= '0';
data_ready_s <= '1';
else
count_s <= count_s +1;
data_ready_s <= '0';
end if;
end if;
end process;
process (reset, clk) begin
if reset = '1' then
bin_in_s <= (others => '0');
elsif rising_edge(clk) then
if load_data = '1' then
bin_in_s <= data_in;
end if;
if shift_en_s = '1' then
bin_in_s <= bin_in_s(18 downto 0) & '0';
end if;
end if;
end process;
ser_out_s <= bin_in_s(19);
process (reset, clk, load_data)
variable bcd_value : std_logic_vector(23 downto 0);
begin
if reset = '1' or load_data = '1' then
bcd_value := (others => '0');
elsif rising_edge(clk) then
if shift_en_s = '1' then
bcd_value := bcd_value(22 downto 0) & ser_out_s;
bcd_out_s <= bcd_value;
if bcd_value(3 downto 0) >= "0101" then
bcd_value(3 downto 0) := bcd_value(3 downto 0) + "0011";
end if;
if bcd_value(7 downto 4) >= "0101" then
bcd_value(7 downto 4) := bcd_value(7 downto 4) + "0011";
end if;
if bcd_value(11 downto 8) >= "0101" then
bcd_value(11 downto 8) := bcd_value(11 downto 8) + "0011";
end if;
if bcd_value(15 downto 12) >= "0101" then
bcd_value(15 downto 12) := bcd_value(15 downto 12) + "0011";
end if;
if bcd_value(19 downto 16) >= "0101" then
bcd_value(19 downto 16) := bcd_value(19 downto 16) + "0011";
end if;
if bcd_value(23 downto 20) >= "0101" then
bcd_value(23 downto 20) := bcd_value(23 downto 20) + "0011";
end if;
end if;
end if;
end process;
process (reset, clk) begin
if reset = '1' then
data_out <= (others => '0');
data_ready <= '0';
elsif rising_edge(clk) then
if data_ready_s = '1' then
data_out <= bcd_out_s;
end if;
data_ready <= data_ready_s;
end if;
end process;
end behaviour;
"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
news:GLFVa.9117$cF.3056@rwcrnsc53...
>
> "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
> news:MzFVa.9078$cF.2637@rwcrnsc53...
> >
> > "Jason Berringer" <look_at_bottom_of@email.com> wrote in message
> > news:kJCVa.3413$Cx4.543634@news20.bellglobal.com...
> > > Hello, I have attached a portion of code for a binary to bcd counter,
20
> > > bits parallel input, and a 24 bit BCD output parallel. Although
> internally
> > > it converts it to serial to go through the conversion. I'm attempting
> the
> > > shift and add three (if greater than or equal to 5) method, but I am
> > having
> > > some problems. It works great on the simulator (Aldec Active HDL) and
I
> > can
> > > synthesize it but when I put it on the chip I'm getting some odd
things.
> I
> > > am using 16 input toggle switches and i debounced pb switch as a load
> > > switch, and my outputs are LEDs. When I set this up on the board my
> > outputs
> > > go as follows:
> >
> > The attachment didn't come through. Can you just include some of the
code
> > in the body, instead of an attachment?
>
> OK, it did come through but I was looking in the wrong place. Still, it
is
> often easier just to include it.
>
> I am much better at reading verilog than VHDL, but it doesn't look right
to
> me. Though I think I don't understand the algorithm, I think it needs to
be
> more complicated than that, though if you do an iterative algorithm it
might
> not be so hard. How many clock cycles does it take to get the data from
> input to output? How many different values did you put through the
> simulator in testing?
>
> -- glen
>
>
Article: 58640To understand the negative delay, it is necessary to understand what the DCM is doing for you in the system. When the DCM is used in the standard way (IBUFG->DCM->BUFG with feedback to CLKFB, and CLKHOUT_PHASE_SHIFT=NONE), the DCM is de-skewing the clock insertion; it is attempting to ensure that the arrival time of the internal clock at the slice and IOB flip-flops is in phase with the arrival of the clock at the pin of the chip (i.e. at the .I input of the IOB). In essence, what it does is adds enough delay so that the sum of the delay through the IOB, the DCM, the IBUFG, and the dedicated clock routing (back to the CLKFB of the DCM) adds up to an integral number of clock periods. Since the clock is periodic, it is irrelevent to report the number of clock periods it adds up to (which is probably 3 or 4), so it reports the DCM time as a negative amount to bring the sum to 0 clock cycles - it should be close to 0ns (-0.713ns in this case). The fact that it is not zero is (almost certainly) correct. In order to have more manageable I/O timing in the default situation, Xilinx has tweaked the performance of the DCM to pull the clock back slightly - this has the effect of increasing the setup time requirement to the IOB flop (Tpsdcm), and reducing the hold time (Tphdcm), making it negative for the Virtex family. Negative hold times make syncronous interfaces "easier" to implement. To run an accurate, full timing simulation, this delay must be annotated onto the DCM as a delay path from the CLKIN to the CLK0. Since simulators cannot deal with negative propagation delays (although static timing analysis tools can), you might have to add a full clock period to the delay to be annotated - so at 100MHz (10ns), you would annotate 9.287 onto this path. If you get this value wrong, then all the IOB timing will be incorrect in your simulation. As for calculating it in advance, it should always be almost exactly the same value for a given process/temperature/voltage (PVT).. The actual value will depend on the delay through the IBUFG (which is a constant at a given PVT), the delay through the dedicated routing to the CLKIN of the DCM (the path from every IBUFG to all reachable DCMs is balanced, and hence should be a constant), the delay through the BUFG, and the delay through the dedicated routing back to the CLKFB, which are also constants at a given PVT. Since Xilinx has set the DCM to result in a -0.713ns effective delay, and all the components are constant, the Tdcmino should also be a constant for a given PVT when CLKOUT_PHASE_SHIFT=NONE. If CLKOUT_PHASE_SHIFT is not NONE, then the phase delay of the DCM will be added to Tdcmino (CLKOUT_PHASE*Tper/256). Avrum "Ab Ran" <aran_jan@yahoo.com> wrote in message news:b7c69989.0307291801.5724477b@posting.google.com... > Hi, > > I was wondering if someone could help me with -ve delay number > associated with a DCM in the TRCE report. How is this number > calculated ? If I try to do a timing simulation of this > design, how can I calculate this delay before-hand ? > > Thanx in advance. > > ---- Ab. > > > I am attaching a sample path report below. > > -------------------------------------------------------------------------- > > Clock Path: clk_PN to t2 > Location Delay type Delay(ns) Physical > Resource > Logical > Resource(s) > ------------------------------------------------- > ------------------- > IOB.I Tiopi 0.653 clk_PN > clk_PN > d1_u1 > DCM.CLKIN net (fanout=1) e 0.100 d1_clk_int > DCM.CLK0 Tdcmino -2.131 d1_u2 > d1_u2 > BUFGMUX.I0 net (fanout=1) e 0.100 d1_clk_dcm > BUFGMUX.O Tgi0o 0.465 d1_u3 > d1_u3.GCLKMUX > d1_u3 > SLICE.CLK net (fanout=3) e 0.100 c1 > ------------------------------------------------- > --------------------------- > Total -0.713ns (-1.013ns > logic, 0.300ns route) > > -------------------------------------------------------------------------- ------Article: 58641
"Subroto Datta" <sdatta@altera.com> wrote in message news:qXuUa.3036$NV3.1143@newssvr31.news.prodigy.com... > Multicycle paths are paths between registers that intentionally take more > than one clock cycle to become stable. For example a register may need to > trigger a signal every second or third rising clock edge. > > A False path is any path that is not relevant to a circuit's operation. > > A good description of both multicycle and false paths can be found in the > following Timing Analysis App Note: > > http://www.altera.com/literature/an/an123.pdf > > Subroto Datta > Altera Corp. From a conceptual standpoint, these definitions are mostly correct. But be aware that different CAD-tool vendors (Synopsys, Cadence, etc.) may treat the *operational* meanings of false-path differently.. In Synopsys's case, their application manuals have clear examples when to use 'set_disable_timing' versus 'set_false_path.' The problem with set_false_path is that it can (unintentionally) affect more than just timing-constraints. > > > > "LIJO" <lijo_eceNOSPAM@hotmail.com> wrote in message > news:bftlvd$iao78$1@ID-159866.news.uni-berlin.de... > > Hi, > > Can anyone tell me what is Multi Cycle path and False path? > > > > thanks > > Lijo > > > > > > > > > > >Article: 58642
This solution record will answer this... http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=13024 Ab Ran wrote: > Hi, > > I was wondering if someone could help me with -ve delay number > associated with a DCM in the TRCE report. How is this number > calculated ? If I try to do a timing simulation of this > design, how can I calculate this delay before-hand ? > > Thanx in advance. > > ---- Ab. > > I am attaching a sample path report below. > > -------------------------------------------------------------------------- > > Clock Path: clk_PN to t2 > Location Delay type Delay(ns) Physical > Resource > Logical > Resource(s) > ------------------------------------------------- > ------------------- > IOB.I Tiopi 0.653 clk_PN > clk_PN > d1_u1 > DCM.CLKIN net (fanout=1) e 0.100 d1_clk_int > DCM.CLK0 Tdcmino -2.131 d1_u2 > d1_u2 > BUFGMUX.I0 net (fanout=1) e 0.100 d1_clk_dcm > BUFGMUX.O Tgi0o 0.465 d1_u3 > d1_u3.GCLKMUX > d1_u3 > SLICE.CLK net (fanout=3) e 0.100 c1 > ------------------------------------------------- > --------------------------- > Total -0.713ns (-1.013ns > logic, 0.300ns route) > > --------------------------------------------------------------------------------Article: 58643
Hi. I am new to VHDL and FPGA. May I ask what is the difference between behavioral and other simulation? What would have caused the result in behavioral simulation to be different from other simulations? (That is the problem I am having now. One of the message is WARNING:NetListWriters:431 - Design does not contain hierarchical blocks with KEEP_HIERARCHY property. Hierarchy will not be retained. ) Which simulation would approximate most closely the behavior when the code is loaded into the FPGA? I am using Xilinx Webpack 5.2 03i. Thank you =)Article: 58644
wpiman@aol.com (MS) wrote in message news:<f0ddfdfb.0307290544.67df0380@posting.google.com>... > We got a ball park cost for our timeframe and volume. I should have > said this up front. > > Yeah- I knew it would be a wild guess- the drop in the price of > processor is probably a safe model to follow. > > Thanks to everyone- including the vendors---- > > MS One additional source of info would be to get the fab costs for the 8"/12" wafers from say TSMC or UMC and try to figure the production costs of your FPGA and possibly your own design committed to an ASIC directly for comparison. I am not saying this is easy. Off top of head you can visit say MOSIS and other shared mask foundries (including TSMC, UMC, Chartered for shuttle runs)and get $ estimates for any technology you like from 2u down to 0.13u for any die size any process but only 40 parts. For MOSIS, fab could be IBM, TSMC and many others. They may have mini volume runs as well. If you have an ASIC friendly design that isn't state of the art FPGA hostaged, there are folks who will ASIC your FPGA designs. You will trade lower per vol parts cost for very much higher NREs upfront. X & A know this so they have ways to lower your FPGA costs too, such as partials that work for your specific bitfile (ok as long as your bitfile is final) or as fixed FPGAs. For something like .18u the cost always seem to be $50K-$100K IIRC for only 40 samples in hand depending on die size (about 1cm IIRC). Factor $100K over 40 parts and FPGAs start to look pretty cheap even in very high vols. Also consider all the goodies you don't have to design, then FPGAs start to look priceless. But if your design really is just a bucket load of gates and Ram blocks, and you have IP that is outside FPGA domain ie mixed signal, its still possible (barely) to go ASIC. Bear in mind that FPGA on .13u will only perform as well as an ASIC on a .5u down to .25u depending on numerous factors. Even if an ASIC could perform as well on a .5u, the resulting die size would probably come to same size of silicon so wafer cost would still be same per area, but less for process. But the sweet spot would be .18 or .2 ie 1-2 generations behind, faster cheap, but upfront NRE. just more info to play with.Article: 58645
Lan, while XST is not supported for the ml300_embedded_* design shipping with ML300/V2PDK 1.5 it will work with the Verilog version but not work with VHDL. However, you will have to remove some peripherals from the system by modifying flow.cfg and changing the yes/no table at the end of the file. The default setup for the ml300_embedded_verilog design is the one that is part of the ML300 ACE files, ie. Linux will boot even if there are devices like AC97 and others that are not directly supported by Linux. flow.cfg is the central file for all configurations, tools, SW, peripherals, etc. - Peter Lan Nguyen wrote: > Hi Peter, > > I've got the Developer's Kit V2PDK VP4. I wanted to run the reference > designs and test the results via the serial port. I tried and got > nothing in the HyperTerminal. > > Does XST work for the synthesis ? If so, what modifications do I have > to make ? > > (I was told that the only way is to get Synplify synthesis tool) > > Thanks > > Lan > > Peter Ryser <ryserp@xilinx.com> wrote in message news:<3F1F1FE4.B2A8FCB1@xilinx.com>... > > Yes, it does. The reference design actually comes with the MLD (Microprocessor > > Library Definition) technology that allows you to automatically generate a BSP > > for Linux consisting of Xilinx layer 0 and 1 drivers according to the hardware > > definition (MHS). When you generate the libraries from the system_linux.xmp > > project file you will get this BSP. > > > > The BSP will also contain necessary patches to the Linux kernel to make the > > design work with MontaVista Linux 3.0 (FYI: the only thing that needs to be > > patched is the code for the Xilinx interrupt driver since the interrupt > > controller from V2PDK and EDK are different) > > > > - Peter > > > > > > tk wrote: > > > > > Hi Peter, > > > > > > I would like to ask if the reference design support > > > MontaVista Linux Pro 3.0 ? > > > > > > Thanks very much! > > > > > > tk > > > > > > Peter Ryser wrote: > > > > > > > Antti, > > > > > > > > the EDK reference design for ML300 contains > > > > - 1 PPC 405 > > > > - 1 PLB DDR > > > > - 1 PLB bus with arbiter > > > > - 1 PLB2OPB bridge > > > > - 1 PLB BRAM controller with 32 KB BRAM attached > > > > - 1 OPB Uart > > > > - 2 OPB GPIO > > > > - 1 OPB 10/100 Ethernet (interrupt driven) > > > > - 1 OPB IIC > > > > - 1 OPB System ACE CF > > > > > > > > There is no touchscreen, PS/2, TFT, parallel port and AC97. Adding these > > > > peripherals to the design is planned for a later release that will most > > > > likely happen towards the end of the year. > > > > > > > > There is some documentation in the zip file that lists the peripherals and > > > > explains the design. > > > > Again, please contact your Xilinx FAE if you would like to get access to > > > > this design. > > > > > > > > Thanks, > > > > - Peter > > > > > > > > > > > > > > > > Antti Lukats wrote: > > > > > > > >> Peter Ryser <ryserp@xilinx.com> wrote in message > > > >> news:<3F1846C0.776CD1F5@xilinx.com>... > > > >> > > > > >> > If you want to work with EDK please contact your FAE and ask him to get > > > >> > you access to the EDK reference design for ML300. He will be able to > > > >> > get you access to the design. > > > >> > > > >> Hi Peter, > > > >> > > > >> when we received the EDK + DDR project, I also asked to be notified > > > >> when a better EDK ref. design will be available, and so far have not > > > >> got any more info, could you please enlight us what additional cores > > > >> are available in the EDK ref. design you mentioned? > > > >> > > > >> ASFAIK TFT and Touchscreen are not implemented (or hopefully are now?) > > > >> I have still having trouble to get EDK to work correctly using the > > > >> obsoleted TFT ref. design - eg. display is looking in stripes 8 pixels > > > >> missing after 8 ok pixels - if the problem is fixed and ref design > > > >> availabl would be greate. > > > >> > > > >> anttiArticle: 58646
Tk, removing peripherals in V2PDK are as simple as modifying flow.cfg and commenting changing the yes/no table at the end of the file. Of course, if you remove PCI from the hardware you will also have to remove PCI support from the Linux kernel. - Peter tk wrote: > Hi, > > I'm now finding the way to contact "my FAE" ..... > > I really hope that Peter can me a copy of it ... > bcoz I've spent one week modifying the reference > design (just wanna remove the AC97 and PCI) > but failed .... the Linux can't boot ...... > > tk > > "Antti Lukats" <antti@case2000.com> wrote in message > news:80a3aea5.0307272123.2567fa16@posting.google.com... > > hln01@uow.edu.au (Lan Nguyen) wrote in message > news:<70360b52.0307271802.7509c4db@posting.google.com>... > > > Hi Peter, > > > > > > I've got the Developer's Kit V2PDK VP4. I wanted to run the reference > > > designs and test the results via the serial port. I tried and got > > > nothing in the HyperTerminal. > > > > > > Does XST work for the synthesis ? If so, what modifications do I have > > > to make ? > > > > > > (I was told that the only way is to get Synplify synthesis tool) > > > > Hi Lan, > > > > yes and no - > > V2PDK was targetted for synplify synthesis but you can use portions > > of the reference platforms also with XST synthesis > > > > --- flow.cfg --------- > > # Synthesis (Synplify) > > #SYN_TOOL = synplify > > #SYN_CMD = synplify # synplify / synplify_pro > > # add -batch to SYN_OPT to invoke synplify in batch mode (non-GUI) > > #SYN_OPT = # inferred (synplify): <none> > > > > # Synthesis (XST) > > SYN_TOOL = xst > > SYN_CMD = xst > > SYN_OPT = -hierarchy_separator / -keep_hierarchy Yes -opt_level 2 > > -opt_mode area -iobuf no # inferred (xst): <none> > > > > ----- end cut --- > > above is the modified flow.cfg > > > > > > notice: you can use XST for the simple vhdl design only for the > > embedded_vhdl it will not work, only verilog version works and there > > you need to disable most of the peripherelas (at the end of flow.cfg) > > to get it to fit into VP7 > > > > antti > > PS has anybody seen the ref. design Peter has talking about?Article: 58647
Antti, Ethernet should work, even with XST. Did you see any problems with having Ethernet enabled? - Peter PS: I'll see what I can do with respect to the EDK reference design for ML300... Antti Lukats wrote: > "tk" <tokwok@hotmail.com> wrote in message news:<bg2n50$b1e$1@www.csis.hku.hk>... > > Hi, > > > > I'm now finding the way to contact "my FAE" ..... > > > > I really hope that Peter can me a copy of it ... > > bcoz I've spent one week modifying the reference > > design (just wanna remove the AC97 and PCI) > > but failed .... the Linux can't boot ...... > > hm,, using XST Verilog following peripheral can be used > > USER_USE_DDR = yes # use "no" for no DDR, "yes" to include DDR Controller > USER_USE_TFT = yes # use "no" for no TFT, "yes" to include TFT Display > USER_USE_IIC = no # use "no" for no IIC, "yes" to include IIC > USER_USE_U450 = yes # use "no" for no U450, "yes" to include 16450 Uart > USER_USE_U550 = yes # use "no" for no U550, "yes" to include 16550 Uart > USER_USE_PCI = no # use "no" for no PCI, "yes" to include PCI > USER_USE_AC97 = yes # use "no" for no AC97, "yes" to include AC97 > USER_USE_ENET = no # use "no" for no Enet, "yes" to include Enet > USER_USE_PS2 = no # use "no" for no PS/2, "yes" to include PS/2 > USER_USE_SPI = no # use "no" for no SPI, "yes" to include SPI > USER_USE_TSD = yes # use "no" for no TSD, "yes" to include Touch Screen > USER_USE_PP = no # use "no" for no PP, "yes" to include Parallel Port > USER_USE_SACE = yes # use "no" for no SACE, "yes" to include System ACE > USER_USE_ILA = no # use "no" for no ILA, "yes" to include ILA > USER_USE_BGI = no # use "no" for no BGI, "yes" to include OPB-PLB Bridge > > this defenetly works, and I guess it should be ok for linux boot? > ok, if you want networking then you are out luck with XST but as you > got synplify there should not be problems? > > antti > PS if you get hold on your FAE please let me know too! > I am trying to get hold of mine but so far getting no response at all :(Article: 58648
vchen@uiuc.edu wrote: > Hi. I am new to VHDL and FPGA. May I ask what is the difference between > behavioral and other simulation? What would have caused the result in > behavioral simulation to be different from other simulations? > (That is the problem I am having now. One of the message is > WARNING:NetListWriters:431 - Design does not contain hierarchical blocks > with KEEP_HIERARCHY property. Hierarchy will not be retained. ) > > Which simulation would approximate most closely the behavior when the > code is loaded into the FPGA? I am using Xilinx Webpack 5.2 03i. > Thank you =) Also, when I tried to keep the hierarchy, illegal connection for the pad net occur. Anyone has suggestion to what causes all these discrepencies? (It synthesize with no warnings...)Article: 58649
Hi!
How do you readout in Linux? Are you using a device driver or plain
inp(0x37A)? With the latter you will not get more than 500 KByte/s (At
least, that's what I experienced).
--
Dirk Dörr
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