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Hi I have to select between 2 frequencies and modulate one of those 2. I tried to implement BUFGMUX and when i translated it, I got an error stating that the symbol BUFGMUX is not supported to Spartan 2. I would appreciate any suggestions. Regards Rajesh rajes_kumar@yahoo.comArticle: 67251
Hi all, I had posted a query to use BUFGMUX in spartan. I would like to detail my query a bit more.. I have to select one clock buffer( either the clock from CLKDLL-CLKDV or the clock from external PLL) and I used BUFGMUX to select between those 2. I use spartan 2 device and when i tried to translate, I have gotten errors which are cited below.. ******* Checking timing specifications ... WARNING:XdmHelpers:625 - No instances driven from signal "mod_clk_x2_clk_mod2x_dll" are valid for inclusion in TNM group "mod_clk_x2_clk_mod2x_dll". A TNM property on a pin or signal marks only the flip-flops, latches and/or RAMs which are directly or indirectly driven by that pin or signal. <none> (no matching synchronous elements driven by clkdll outputs) WARNING:XdmHelpers:644 - No appropriate elements were found for the TNM group "mod_clk_x2_clk_mod2x_dll". This group has been removed from the design. ERROR:XdmHelpers:650 - The period specification "TS_clk_gck1" is invalid because the "mod_clk_x2_clk_mod2x_dll" group was removed. Checking expanded design ... ERROR:NgdBuild:604 - logical block 'mod_freq_modfreq_mux' with type 'bufgmux' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'bufgmux' is not supported in target 'spartan2'. *********** Could anyone help me in this regard.. Thanks in advance. Regards RajeshArticle: 67252
dear sir / madam Currently I need binary bit stream file(configuration file) examples (any applications are okay) for analysis.........Can somebody tell me how I can obtain them? greetingsArticle: 67253
Thanks ... My purpose is to implement a True Random Number Generator like Viktor Fischer in his article "True Random Number Generator in Reconfigurable Devices" http://www.kemt.fei.tuke.sk/publication/Drutarovsky/ches2002.pdf . I know I can change the counters values but I don't know the out-spec limits of the PLL such as : -input frequency min max (out-spec) -minimum frequency of VCO (out spec) -Specifications of the loop-filter inside the VCO The altpll primitive is the same for ALTERA Stratix and Cyclone devices. I use Cyclone FPGA and I don't know what parameters concern Cyclone (cauz Stratix PLLs are much more parameterable) ...Article: 67254
hi, i think about developing a way to use the testbench my designer wrote, in my software developing environment. e.g. as a "demo mode" when no real-hardware is available, for demonstration purposes. using a vhdl2c converter would be enough if I had one! kind regards, thomasArticle: 67255
Hi Rajesh, you try to use a BUFGMUX in a Spartan 2. These devices only have normal BUFGs. That's why the error. Cheers, Martin Rajesh Murugesan wrote: > Hi all, > > I had posted a query to use BUFGMUX in spartan. I would like to detail > my query a bit more.. I have to select one clock buffer( either the > clock from CLKDLL-CLKDV or the clock from external PLL) and I used > BUFGMUX to select between those 2. I use spartan 2 device and when i > tried to translate, I have gotten errors which are cited below.. > ******* > Checking timing specifications ... > WARNING:XdmHelpers:625 - No instances driven from signal > "mod_clk_x2_clk_mod2x_dll" are valid for inclusion in TNM group > "mod_clk_x2_clk_mod2x_dll". A TNM property on a pin or signal marks > only the > flip-flops, latches and/or RAMs which are directly or indirectly > driven by > that pin or signal. > <none> (no matching synchronous elements driven by clkdll outputs) > WARNING:XdmHelpers:644 - No appropriate elements were found for the > TNM group > "mod_clk_x2_clk_mod2x_dll". This group has been removed from the > design. > ERROR:XdmHelpers:650 - The period specification "TS_clk_gck1" is > invalid because > the "mod_clk_x2_clk_mod2x_dll" group was removed. > Checking expanded design ... > ERROR:NgdBuild:604 - logical block 'mod_freq_modfreq_mux' with type > 'bufgmux' > could not be resolved. A pin name misspelling can cause this, a > missing edif > or ngc file, or the misspelling of a type name. Symbol 'bufgmux' is > not > supported in target 'spartan2'. > *********** > > Could anyone help me in this regard.. > > Thanks in advance. > > Regards > Rajesh >Article: 67256
john wrote: > Hi, > > Is somebody know how to increase the jitter in a PLL integrated in a FPGA ?? > > Thanks in advance... For thr Altera PLL just power it up, that will do the trick :-) --- jakabArticle: 67257
We used Tenison's VTOC product with great success on our last ASIC designed in
verilog. It is a very powerful tool for co-simulation and co-development. Not
sure if it supports VHDL or not... the website just says RTL to C. See
http://www.tenison.com/index.html.
Mark
T. Irmen wrote:
> hi,
>
> i think about developing a way to use the testbench my designer wrote, in my
> software developing environment. e.g. as a "demo mode" when no real-hardware
> is available, for demonstration purposes.
>
> using a vhdl2c converter would be enough if I had one!
>
> kind regards,
> thomas
>
>
Article: 67258Steve Casselman wrote: > "Magnus Danielson" <magda@netinsight.net> wrote in message > news:404c4a28$1@fnewsa.telia.net... > > The 8B/10B (or any other xB/yB) encoding is there so that you transmit an > equal number of ones and zeros. This keeps the transceivers from saturating > one way or the other. Almost true. For the 8B/10B encoding it is certainly true, with its running disparity you ensure the DC balance i.e. equal balance between 0s and 1s. In SDH/SONET you use scrambling with a PRBS to acheive DC balance (an approximation) and in the 64B/66B (10GE) you also use scrambling, but only for 64 bits while the other two bits (sync) is set in a separate encoder/decoder block. It is this block which I want to bypass since it creates an obstacle for my application. I can't use the sync bits arbitrarilly, they must DC balance on their own (in 10GE they are either 01 or 10). So, I still need to know where these bits show up on my Rocket I/O. Cheers, Magnus - who defeated the SDH/SONET scrambler with a customized ping!Article: 67259
merlin1974@gmx.at (millim) wrote in message news:<8e53c613.0403080739.aa1236b@posting.google.com>... > I am trying to find an efficient and simple way to protect > prototypes from cloning. > > One idea relies on using the serial number of the FPGA device, > because in any prototyping phase only a hand full devices are > present. But is there an embedded hardware register in the FPGA device, > which contains a unique serial number? unique serials numbering does cost money as it some short of laser marking unless there is nonvolatile memory, and FPGA dont normally have NV mem. high FPGA have battery backup ram to store 3DES key to decrypt the bitstream. in other cases you need to use some other special techniques to protect and RAM based FPGA anttiArticle: 67260
Altera has a simple "Security Bit" that is supposed to keep other programmers from being able to read your config from either the FPGA or its config device. I have no idea how secure this actually is in practice. I guess it might at least throw up a hurdle to to some? Ken "millim" <merlin1974@gmx.at> wrote in message news:8e53c613.0403080739.aa1236b@posting.google.com... > I am trying to find an efficient and simple way to protect > prototypes from cloning. > > One idea relies on using the serial number of the FPGA device, > because in any prototyping phase only a hand full devices are > present. But is there an embedded hardware register in the FPGA device, > which contains a unique serial number? > > regardsArticle: 67261
hi all, I am a undergraduate studying VLSI and Magic manul layout. My professor have asked us to design an FPGA chip using Magic. I am confused in how to build the switch box and look up table. Could anyone kindly recommend some website or books that gives detail explanation on these stuff. Thanks a lot. Regards, TongArticle: 67262
That's hitting below the belt!
I think the motivation here is for randomness. I'd use a digital random number
generator though, and just seed it with some random event. You might do consider
using a ring oscillator implemented in the fabric (which will be sensitive to
temperature, process and supply voltage) along with your externally applied clock
to get a random seed.
Jakab Tanko wrote:
> john wrote:
> > Hi,
> >
> > Is somebody know how to increase the jitter in a PLL integrated in a FPGA ??
> >
> > Thanks in advance...
> For thr Altera PLL just power it up, that will do the trick :-)
> ---
> jakab
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67263
What is the maximum N you need to handle? Shuffle networks can be
extremely fast, but they also grow exponentially with set size.
sree wrote:
> Hi,
> i am new to FPGA's and vhdl.i need to design a sorter of N numbers 32
> bit each.i know sorting algorithms bubble sort.But i found that in
> fpga's we can do bit comparision parallel and there are fast sort
> methods i can use.i saw a couple but not sure how to implement on
> virtex-II xc2v1000 which has a 100MHz clock.If some body have an
> hardware discrption or digital schematic please let me know.i
> appreciate their help
> thank you
> sree
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67264John, Viktor said that his design failed some of the NIST FFT tests. His comment was that the tests have a known bug. In our research, we have not found that to be true, and have a number of TRNG designs that "pass" the entire NIST suite without any issues. We arew not ready to publish these as yet, as there is a lot more work to do. When we attempted to duplicate the PLL design, we saw terrible results from the FFT set of tests in the NIST suite. It seems that the design is very picky, and prone to bad behavior(spoofing). My comment about modulating the power and ground, would of course just make things far worse. I know our results do not agree with those in the paper. Per Viktor's presentation, we applied the test suite on a few tens of megabits collected before any logic that is intended to "improve" the characterisitics of the bit stream. Austin john wrote: > Thanks ... > > My purpose is to implement a True Random Number Generator like Viktor > Fischer in his article "True Random Number Generator in Reconfigurable > Devices" http://www.kemt.fei.tuke.sk/publication/Drutarovsky/ches2002.pdf > . > > I know I can change the counters values but I don't know the out-spec > limits of the PLL such as : > -input frequency min max (out-spec) > -minimum frequency of VCO (out spec) > -Specifications of the loop-filter inside the VCO > > The altpll primitive is the same for ALTERA Stratix and Cyclone > devices. I use Cyclone FPGA and I don't know what parameters concern > Cyclone (cauz Stratix PLLs are much more parameterable) ...Article: 67265
Simple. Spartan-2 does not have BUFGMUX silicon. Don't use the BUFGMUX and you won't get errors. Or, use Spartan-3. "Rajesh Murugesan" <rajes_kumar@yahoo.com> wrote in message news:5b293f11.0403090210.4bb03992@posting.google.com... > Hi all, > > I had posted a query to use BUFGMUX in spartan. I would like to detail > my query a bit more.. I have to select one clock buffer( either the > clock from CLKDLL-CLKDV or the clock from external PLL) and I used > BUFGMUX to select between those 2. I use spartan 2 device and when i > tried to translate, I have gotten errors which are cited below.. > ******* > Checking timing specifications ... > WARNING:XdmHelpers:625 - No instances driven from signal > "mod_clk_x2_clk_mod2x_dll" are valid for inclusion in TNM group > "mod_clk_x2_clk_mod2x_dll". A TNM property on a pin or signal marks > only the > flip-flops, latches and/or RAMs which are directly or indirectly > driven by > that pin or signal. > <none> (no matching synchronous elements driven by clkdll outputs) > WARNING:XdmHelpers:644 - No appropriate elements were found for the > TNM group > "mod_clk_x2_clk_mod2x_dll". This group has been removed from the > design. > ERROR:XdmHelpers:650 - The period specification "TS_clk_gck1" is > invalid because > the "mod_clk_x2_clk_mod2x_dll" group was removed. > Checking expanded design ... > ERROR:NgdBuild:604 - logical block 'mod_freq_modfreq_mux' with type > 'bufgmux' > could not be resolved. A pin name misspelling can cause this, a > missing edif > or ngc file, or the misspelling of a type name. Symbol 'bufgmux' is > not > supported in target 'spartan2'. > *********** > > Could anyone help me in this regard.. > > Thanks in advance. > > Regards > RajeshArticle: 67266
The GSR net is asynchronous. No matter how slow your clock is, unless you synchronize the reset to the
clock OUTSIDE OF THE FPGA, you can't guarantee all flip-flops in the design will see the release of
reset on the same clock edge. This is because without syncronization to the clock, there is no
guarantee the release of reset won't happen close enough to a clock edge to make some flip-flops see it
before the clock edge, and others after the clock edge. You can't synchronize it inside the FPGA
because GSR affects all the flip-flops. A side issue is the fact that the GSR net is very slow compared
to the speed the rest of the FPGA logic can operate at.
William Wallace wrote:
> Jeff Cunningham <jcc@sover.net> wrote in message news:<m8I2c.274$_43.199987@newshog.newsread.com>...
> > William Wallace wrote:
> > > THE IMPORTANCE OF PROVIDING A RESET THAT LEAVES THE RESET
> > > SYNCHRONOUSLY EVEN IF IT DRIVES THE ASYNCHRONOUS RESET...
> >
> > You cannot rely on async reset at startup for initializing one hot state
> > machines and the like...
>
> Please explain why. Meanwhile, releasing the asynchronous reset
> synchronously, and ensuring that the reset path delay and setup is
> less than a clock period, would work.
>
> Please re-read my original post, and tell me exactly where I am wrong.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67267
Eh, what? Unfortunately anonymos...
Each first level LUTs detects (output High) that exactly one of its inputs
is High.
The second tier LUT detects that exactly one of the first-tier LUT outputs
is high, which mans that there is exactly one High input.
Agreed ?
Peter Alfke
> From: user@domain.invalid
> Newsgroups: comp.arch.fpga
> Date: Tue, 09 Mar 2004 05:24:26 GMT
> Subject: Re: Release asynchrounous resets synchronously
>
> Peter Alfke wrote:
>> LUTs are very efficient "illegal state" detectors.
>> Let's say you have a 16-state one-hot machine. Four LUTs can each detect
>> "exactly one of my inputs is High", and a fifth LUT does the same with the
>> four LUT outputs. So 5 LUTs can detect any illegitimate 16-bit code. Take it
>> from there...
>
> Eh, what? So the first tier LUT compute f, where
> f(a,b,c,d) = 1 iff a+b+c+d = 1, else 0.
> For the 5th LUT we have the same property that a legal 16-state would
> map exactly one of the four first tier LUTs to 1, thus it sounds like
> what you have in mind is something like this:
>
> f({f(s[3:0]), f(s[7:4]), f(s[11:8]), f(s[15:12])})
>
> but this could accept states like 16'b1111_1110_1100_0001.
>
> I don't see how you can detect legal states with only five four-input LUTs.
>
>
> Peter, the FPGA reset question has come many times. What does Xilinx
> recommend in general? Async-reset+Sync-release, all-sync, or all-async?
> Which uses fewest resources?
>
> Thanks,
>
> Tommy
>
Article: 67268cdufourfour@yahoo.ca (john) wrote in message news:<79cc958c.0403090243.5aa02b63@posting.google.com>... > Thanks ... > > My purpose is to implement a True Random Number Generator like Viktor > Fischer in his article "True Random Number Generator in Reconfigurable > Devices" http://www.kemt.fei.tuke.sk/publication/Drutarovsky/ches2002.pdf > . > > I know I can change the counters values but I don't know the out-spec > limits of the PLL such as : > -input frequency min max (out-spec) > -minimum frequency of VCO (out spec) > -Specifications of the loop-filter inside the VCO > > The altpll primitive is the same for ALTERA Stratix and Cyclone > devices. I use Cyclone FPGA and I don't know what parameters concern > Cyclone (cauz Stratix PLLs are much more parameterable) ... John, A couple of ideas: 1. Stratix Enhanced PLLs have a Spread-Spectrum clocking feature. This provides a 0.5% down spread modulation. So if you put in a 100 MHz clock, the output will vary from 99.5 MHz to 100 MHz. This is somewhat like jitter. I'm not sure how useful it will be for random numbers however since the behavior is predictable. 2. Stratix Enhanced PLLs have a PLL reconfiguration function. You can change the values of the various counters as the device is operating. You could use this to switch between two clock output frequencies for example. 3. Stratix Enhanced PLLs have a Clock Switchover. If you switch from one clock input to the other, the PLL takes some time to respond and the frequency output is variable until the PLL relocks. The Cyclone PLL is simpler and does not have these features. A non-pll option for randomness would be to construct a ring oscillator out of LEs. The FMAX will vary over process-voltage-temperature, so this may be useful to generate random numbers. Sincerely, Greg Steinke gregs@altera.com Altera CorporationArticle: 67269
Hi,
If i remember right the altpll has specification for 15 Mhz low side.
regards
"SneakerNet" <nospam@nospam.org> schreef in bericht
news:Ow43c.6282$Nc3.101499@news.xtra.co.nz...
> Hello Ppl
>
> I have actually already asked this question before but I need help again.
>
> I'm using a Nios Development Board (50MHz Oscillator, FPGA = Cyclone
> EP1C20F400C7). I'm using Quartus II v4.0 Build 190
> I need to generate a clock speed of 12.5MHz. While I have my own vhdl code
> that can do this, I can't use the ALTPLL to do this for me.
>
> How can i do this? When I try to generate a speed of 12.5MHz using
> MegaFunction Wizard in Quartus it complains ('Post divider max count
> exceeded')
> Does this mean there is a lower limit? Is there a way to achieve this
speed
> using ALTPLL and the above specs?
>
> Thanks
>
>
Article: 67270You can do the clock muxing in the fabric. Years ago I published a circuit, now also in TechXclusives ( Six Easy Pieces, #6). Unfortunately, the simple 2-flip-flop schematic does not make it into this ng... Peter Alfke 6. Asynchronous switching between two unrelated clocks Asynchronously switching between two unrelated clock frequencies will produce runt pulses and glitches that make the system unreliable. The circuit shown below ( well, it does not show...go to TechXclusives) illustrates a solution to these problems. When the SELECT input is stable (either High or Low), the two control flip-flops are in opposite states, and one of the two clock inputs drives the clock output. When the SELECT input changes, there is no immediate impact until after the next falling edge of the originally-selected clock source, which also resets its control flip-flop. The Output Clock signal will then stay Low beyond the next falling edge of the newly selected clock, which sets its control flip-flop, causing the newly selected clock to drive the Output Clock. Any clock-switching starts when the originally selected clock goes Low, and the Output Clock then stays Low until the newly selected clock has first gone Low and then High again. There can never be a runt pulse or output glitch. If the timing of the SELECT input causes a control flip-flop to go metastable, this has no impact since the Output Clock is driven Low by the input clock (irrespective of the control flip-flop). Metastability must resolve itself within the clock Low time. Modern flip-flops resolve metastability in less than 2 ns (see the "Metastability Delay and Mean Time Between Failure in Virtex-II Pro FFs" TechXclusive from October, 2002). This circuit assumes rising-edge triggering, and it requires both clocks to be free-running. ================================== > From: "John_H" <johnhandwork@mail.com> > Organization: Xerox Officeprinting NewsReader Service > Reply-To: "John_H" <johnhandwork@mail.com> > Newsgroups: comp.arch.fpga > Date: Tue, 09 Mar 2004 16:20:45 GMT > Subject: Re: Reg..How to use BUFGMUX in Spartan 2 family > > Simple. > > Spartan-2 does not have BUFGMUX silicon. > > Don't use the BUFGMUX and you won't get errors. Or, use Spartan-3. > > > "Rajesh Murugesan" <rajes_kumar@yahoo.com> wrote in message > news:5b293f11.0403090210.4bb03992@posting.google.com... >> Hi all, >> >> I had posted a query to use BUFGMUX in spartan. I would like to detail >> my query a bit more.. I have to select one clock buffer( either the >> clock from CLKDLL-CLKDV or the clock from external PLL) and I used >> BUFGMUX to select between those 2. I use spartan 2 device and when i >> tried to translate, I have gotten errors which are cited below.. >> ******* >> Checking timing specifications ... >> WARNING:XdmHelpers:625 - No instances driven from signal >> "mod_clk_x2_clk_mod2x_dll" are valid for inclusion in TNM group >> "mod_clk_x2_clk_mod2x_dll". A TNM property on a pin or signal marks >> only the >> flip-flops, latches and/or RAMs which are directly or indirectly >> driven by >> that pin or signal. >> <none> (no matching synchronous elements driven by clkdll outputs) >> WARNING:XdmHelpers:644 - No appropriate elements were found for the >> TNM group >> "mod_clk_x2_clk_mod2x_dll". This group has been removed from the >> design. >> ERROR:XdmHelpers:650 - The period specification "TS_clk_gck1" is >> invalid because >> the "mod_clk_x2_clk_mod2x_dll" group was removed. >> Checking expanded design ... >> ERROR:NgdBuild:604 - logical block 'mod_freq_modfreq_mux' with type >> 'bufgmux' >> could not be resolved. A pin name misspelling can cause this, a >> missing edif >> or ngc file, or the misspelling of a type name. Symbol 'bufgmux' is >> not >> supported in target 'spartan2'. >> *********** >> >> Could anyone help me in this regard.. >> >> Thanks in advance. >> >> Regards >> Rajesh > >Article: 67271
Peter Alfke wrote: > Eh, what? Unfortunately anonymos... Sorry, Tommy Thorn, tommy at numba-tu dot com. > Each first level LUTs detects (output High) that exactly one of its inputs > is High. > The second tier LUT detects that exactly one of the first-tier LUT outputs > is high, which mans that there is exactly one High input. > Agreed ? Did you actually read what I wrote? It doesn't work. Take for example 16'b1111_1110_1100_0001, only one of the nibbles has exactly one bit high, so the first tier LUTs goes 0 0 0 1, which has exactly one bit set and your scheme would say that's a valid state. You need to distinguish 0, 1, and more, thus use roughly twice the LUTs. Thanks, TommyArticle: 67272
Peter Alfke wrote: > Eh, what? Unfortunately anonymos... Sorry, Tommy Thorn, tommy at numba-tu dot com. > Each first level LUTs detects (output High) that exactly one of its inputs > is High. > The second tier LUT detects that exactly one of the first-tier LUT outputs > is high, which mans that there is exactly one High input. > Agreed ? Did you actually read what I wrote? It doesn't work. Take for example 16'b1111_1110_1100_0001, only one of the nibbles has exactly one bit high, so the first tier LUTs goes 0 0 0 1, which has exactly one bit set and your scheme would say that's a valid state. You need to distinguish 0, 1, and more, thus use roughly twice the LUTs. Thanks, TommyArticle: 67273
You need to ask Samsung ... Kelvin @ SG wrote: >well, maybe that is why i couldnt simulate the Samsung SmartMedia model with >Modelsim... >How do I find out which is the right simulator? > >Best Regards, >Kelvin > > > > >Paulo Dutra <Paulo.Dutra@xilinx.com> wrote in message >news:c2isnh$dqi2@cliff.xsj.xilinx.com... > > >>Are u refering to the `protect and `endprotect compiler directives? >>Looking at the IEEE spec there's >>no definition of these compiler directives. It's use I have only seen >>associated with simulation >>models targeted toward a specific simulator.. As the >>encryption/decryption I would assume is proprietary. >>Thus, you cannot compile in XST. >> >>I found this text in the ModelSim user guide: >> >>Though other simulators have a `protect directive, the algorithm >>ModelSim uses to encrypt >>source files is different. Hence, even though an uncompiled source file >>with `protect is >>compatible with another simulator, once the source is compiled in >>ModelSim, you could >>not simulate it elsewhere. >> >> >>Kelvin @ SG wrote: >> >> >> >>>Hi, there: >>> >>>Can Xilinx XST synthesize encrypted verilog source codes? For example the >>>following style... >>>What is the software to do this encryption? >>> >>>Best Regards, >>>Kelvin >>> >>> >>> >>> >>> >>> >>> > > > >Article: 67274
konerusreeram@yahoo.com (sree) wrote in message news:<195eee74.0403090047.1e494af9@posting.google.com>... > Hi, > i am new to FPGA's and vhdl.i need to design a sorter of N numbers 32 > bit each.i know sorting algorithms bubble sort.But i found that in > fpga's we can do bit comparision parallel and there are fast sort > methods i can use.i saw a couple but not sure how to implement on > virtex-II xc2v1000 which has a 100MHz clock.If some body have an > hardware discrption or digital schematic please let me know.i > appreciate their help > thank you > sree Do you need all 32 values at the same time such that you're processing N values on *every* clock expecting the sorted values with a few clock cycles latency, a new sorted list on every clock? Is your time less critical? Do you need one value at a time from highest to lowest or vice-versa? Do you just need the value or do you need to know which entry it was in the original list? As a for-instance, the bitonic sort will give a great parallel sort algorithm providing a list of N sorted elements every clock but with a huge amount of resources to accommodate the parallelism. BlockRAMs are great for doing manipulation of the large numbers for comparisons between 2 entries every clock cycle making them handy for some sort algorithms. If you read the values in one at a time, some of the sorting can be performed as you build up your array rather than waiting until it's fully in place. So - state your needs.
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