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Messages from 68000

Article: 68000
Subject: Re: Bus width between registers in IIR
From: Ray Andraka <ray@andraka.com>
Date: Wed, 24 Mar 2004 07:54:33 -0500
Links: << >>  << T >>  << A >>
FPGA arithmetic can be specified to the exact number of bits, not multiples of two
bits.  The difference with FPGAs is you don't need to carry around extra bits to
make the accumulator a multiple of some word size.  Still, that does not
practically affect the IIR filter design appreciably.  You have the same
quantization effects to worry about whether you use a microprocessor with fixed
point or an FPGA with fixed point.


>



--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 68001
Subject: Re: study verilog or vhdl?
From: "Kelvin" <kelvin8157@hotmail.com>
Date: Wed, 24 Mar 2004 21:00:40 +0800
Links: << >>  << T >>  << A >>
I would recommend starting with Verilog...Verilog code is simpler, more
concise...
Once you are fluent with Verilog, learning VHDL becomes easy...Google with
"Verilog tutorial"
and you will see a big list of interesting websites...

Kelvin











"Jack" <dreamguy007@hotmail.com> wrote in message
news:b7c82826.0403232250.4e3fbf5e@posting.google.com...
> hi. i'm just starting out with fpga. maybe this question has popped up
> many times. which one is more useful in the industry: verilog or vhdl?
> which one do you recommend for starter?
>
> i'm also learning with a goal to implement dsp in hardware.



Article: 68002
Subject: Re: study verilog or vhdl?
From: Phil Hays <Spampostmaster@comcast.net>
Date: Wed, 24 Mar 2004 13:00:54 GMT
Links: << >>  << T >>  << A >>
On 23 Mar 2004 22:50:34 -0800, dreamguy007@hotmail.com (Jack) wrote:

>hi. i'm just starting out with fpga. maybe this question has popped up
>many times. which one is more useful in the industry: verilog or vhdl?
>which one do you recommend for starter?
>
>i'm also learning with a goal to implement dsp in hardware.

VHDL is more useful.

Verilog is somewhat easier to start to learn than VHDL, and is
somewhat harder to master than is VHDL.

Some geographic areas use more of one than the other.  Some types of
business use more of one or the other.  Finding out what is used where
you want to work might be the best idea.


--
Phil Hays
Phil_hays at posting domain should work for email


Article: 68003
Subject: Re: Quartus with AMD64 processors?
From: "Subroto Datta" <sdatta@altera.com>
Date: Wed, 24 Mar 2004 14:43:27 GMT
Links: << >>  << T >>  << A >>

"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message
news:40615177$0$31711$fa0fcedb@lovejoy.zen.co.uk...
> > Hi Nial,
> >
> > Quartus II 4.1 will be qualified to work on Opteron processors with
> > Red Hat Enterprise and Red Hat 8.0. In the meantime there are two
> > scripts that can be easily modified to avoid the problem. Here are the
> > details on the changes to make it work on an Opteron.
>
> Subroto,
>
> I'll be installing Win2K, has everything always worked under
> Windows? (From what Paul says above I think the answer's yes).
>
>
> Nial.
>
>

Yes, our products are tested to the best of our ability on the OS platforms
we claim are supported. We fully support support WinNT 4 SP6, Win2K
(Professional) and Windows XP.

- Subroto Datta
Altera Corp.



Article: 68004
Subject: Re: Quartus with AMD64 processors?
From: "Subroto Datta" <sdatta@altera.com>
Date: Wed, 24 Mar 2004 14:52:49 GMT
Links: << >>  << T >>  << A >>

"Petter Gustad" <newsmailcomp5@gustad.com> wrote in message
news:m3fzbyiph9.fsf@scimul.dolphinics.no...
> "David Brown" <david@no.westcontrol.spam.com> writes:
>
> > Why are you so specific about the Linux distribution?  I can fully
> > understand that you only test and support Quartus under specific
> > distributions, but having your scripts specifically check for
pre-defined
> > versions seems like you are going out of your way to make life hard for
> > users.  If you need specific features (say, a particular version of
tcl),
> > then make a single "check installation" script that checks the features
> > required - and lets the user continue anyway, since maybe some parts
work
> > even if there are problems.
>
> I agree!!! (see http://tinyurl.com/22c86). I think it makes perfect
> sense that a company only *qualify* a specific distribution, but I
> hate to see that it checks for a specific string to match
> /etc/redhat-release and quits with a message saying «unsupported
> system» when it would most likely run on lets say a SuSE distribution.
>
> I've seen scripts checking dozens of permutations of
> /etc/redhat-relese, various uname outputs etc. to figure out if they
> are running on an X86 or IA64 based Linux. One could have included two
> small hello world style precompiled binaries (compiled with the same
> options, libraries, and features as the target application). One would
> give the expected output, the other would crash (with cannot execute
> binary or similar).
>
>
> Petter
>
> -- 
> A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?
> A: Top-posting.
> Q: What is the most annoying thing on usenet and in e-mail?

Hi Petter,

  I have given pointers in an an earlier post in this thread to what needs
to be modified if anyone would like to try Quartus on a non-supported Linux
platform. The changes are very minor, you can do them yourself  and try
them.

- Subroto Datta
Altera Corp.



Article: 68005
Subject: Re: Quartus with AMD64 processors?
From: "Subroto Datta" <sdatta@altera.com>
Date: Wed, 24 Mar 2004 15:05:29 GMT
Links: << >>  << T >>  << A >>

"Subroto Datta" <sdatta@altera.com> wrote in message
news:j8h8c.39754$Q31.12668@newssvr16.news.prodigy.com...
>
> "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message
> news:40615177$0$31711$fa0fcedb@lovejoy.zen.co.uk...
> > > Hi Nial,
> > >
> > > Quartus II 4.1 will be qualified to work on Opteron processors with
> > > Red Hat Enterprise and Red Hat 8.0. In the meantime there are two
> > > scripts that can be easily modified to avoid the problem. Here are the
> > > details on the changes to make it work on an Opteron.
> >
> > Subroto,
> >
> > I'll be installing Win2K, has everything always worked under
> > Windows? (From what Paul says above I think the answer's yes).
> >
> >
> > Nial.
> >
> >
>
> Yes, our products are tested to the best of our ability on the OS
platforms
> we claim are supported. We fully support support WinNT 4 SP6, Win2K
> (Professional) and Windows XP.
>
> - Subroto Datta
> Altera Corp.
>
>

Nial,

   I missed an important point. Quartus has been tested on all the above
Windows OS's have been tested on 32 bit Intel processors. We have customers
who use it with 32 bit Athlon boxes running the same Windows systems, and to
date we have not heard of any incompatibility.

- Subroto Datta
Altera Corp.



Article: 68006
Subject: Re: PCI Development Board
From: "Spike" <me.hates:spam@me.net>
Date: Wed, 24 Mar 2004 15:09:45 GMT
Links: << >>  << T >>  << A >>

"Andy Peters" <Bassman59a@yahoo.com> skrev i meddelandet
news:9a2c3a75.0403231442.1c57e5ee@posting.google.com...
> "Spike" <me.hates:spam@me.net> wrote in message
news:<YgD7c.53175$mU6.222519@newsb.telia.net>...
> > Thanks for you tip, I'll take it under consideration.
> >
> > Has anyone tried this one:
http://www.plxtech.com/tools/rdk/9030rdk-lite.htm
>
> I didn't use the RDK, but I did do a board based on the 9030.  I wrote
> a pretty damn complete bus-functional model of the 9030's local bus
> (PLX wanted it but we wouldn't give it to 'em).  It all came together
> quite easily.
>
> > Does PLX PCI chips require some sort of EEPROM to store PCI
configuration
> > space or any other information, if so what kind of ROM is needed?
>
> Yes, you'll need a serial EEPROM.  It holds not only the PCI
> configuration info, but some other configuration info used by the chip
> (things like local-bus sizes, wait state info, chip-select info, etc.)
>  Download the data sheets from PLX and everything will be revealed.
>
> -a

A real newbie question: What is the difference between PCI Master/Slave
device?

Thanks alot!

//SPike



Article: 68007
Subject: Re: PCI Development Board
From: "Spike" <me.hates:spam@me.net>
Date: Wed, 24 Mar 2004 15:12:44 GMT
Links: << >>  << T >>  << A >>
Also, what does "SMARTarget I/O Accelerator" mean or is it just what PLX
calls the 9030?

//SPike



Article: 68008
Subject: Re: Quartus with AMD64 processors?
From: Petter Gustad <newsmailcomp5@gustad.com>
Date: 24 Mar 2004 16:15:40 +0100
Links: << >>  << T >>  << A >>
"Subroto Datta" <sdatta@altera.com> writes:


>   I have given pointers in an an earlier post in this thread to what needs
> to be modified if anyone would like to try Quartus on a non-supported Linux
> platform. The changes are very minor, you can do them yourself  and try
> them.

Thank you for sharing the script fix I will try make the patch when I
get my timeslice on the Opterons again. 

Petter

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 68009
Subject: PULL-UPs on Xilinx-FPGA
From: "Matija" <matija.habek@fer.hr>
Date: Wed, 24 Mar 2004 16:22:31 +0100
Links: << >>  << T >>  << A >>
Hi,

how can I drive pull-up on external inout port (using VHDL)
Thanks
Regards, Matija



Article: 68010
Subject: Re: Fried a XC2S200!
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 24 Mar 2004 07:30:11 -0800
Links: << >>  << T >>  << A >>
Antti,

There is the possibility of "infant mortality" which is where an oxide 
or junction defect is just not bad enough to cause a failure until some 
short time (but much longer than any time spent here at Xilinx) after 
the part has been turned on and is in use.

The process qualification certifies that these defects are to be below a 
certain point, and the testing that is done assures some acceptable 
quality level, but there is nothing to prevent one from getting an 
occasional out-lier that becomes toast.

If you burn in a part for too long, you are actually shortening the life 
by any early stresses.  If you burn in for too short a period, you have 
done nothing but wasted the electricity to power them (no customer 
benefit, and made costs go up!).  So, the quality is more related to the 
process (which we monitor closely).

I would call in to the hotline, and get an RMA, and the instructions for 
proper removal of the device.  Once the part is properly removed, it can 
be sent back for failure analysis.  You may also have some warranty if 
this is a new part, and a replacement may be issued thru your disti 
(depends on many factors, but if new, then this should be the deal).

We can not prevent an occasional defect from destroying the occasional 
part, but we can respond, and get you running again.

As for the IO diodes, they can handle close to 200 mA for short 
durations and not even feel any pain.  Just look at the IBIS files for 
the diode curves.  The 10 mA is for recommended operating conditions. 
Any more than that, and you have failed to design your signal integrity 
properly (unless it is the massive thump allowed by the PCI bus - which 
is a SI "compromise" and guaranteed by the PCI specs that we also adhere 
to meeting).  And with 1000 IOs, at 10 mA each, that would be 10 amperes 
  of current, so no, you can not do that.  And the IO clamp is only 
enabled for certain IO standards, so without the clamp to Vcco, remember 
Vpin cannot be allowed to go beyond the data sheet absolute maximum 
voltage limits!

This sounds like a complete crowbar caused by a defect, not something 
that was done to the chip, as it would have had to be something pretty 
ugly to cause this problem.

On the other hand, a Failure Analysis may tell you something that you 
did not know (something is lurking in your board that kills FPGAs).

Austin

Antti Lukats wrote:
>>: Usually a good data sheet will have a spec for how much current you
>>: can safely dump into the clamp diodes.  The footnote below the
>>: Absolute Max Ratings table says 10 mA.
>>
>>: 2K7 on (5-3) V is under 1 mA.  I'd be surprised if that damaged the
> 
> chip.
> 
>>: One way to kill chips is to do something that triggers latchup.
>>: Have you put a scope on all the IO signals?  Could a wire have slipped
>>: while you weren't watching and dumped a lot of current into an IO pin?
>>
>>As these chips were used chips, unsoldered, then sold and reused by Anti,
>>they have  quite a long history of possible (miss-)treatment...
>>
>>Bye
> 
> 
> there are no clamp diodes in XC2S200E !!!
> the 2k7 resistors pulls the FPGA pin to 5V, but I assume there is almost no
> current. that is surprising!
> 
> The FPGA in question is brand new soldered to 6 layer PCB it was running a
> Microblaze program when during that it started to heat!
> there was no one around to drop any wires onto it
> 
> I am still wondering why I have this dead FPGA
> 
> antti
> 
> 

Article: 68011
Subject: Re: cheapest & best FPGA???
From: Rene Tschaggelar <none@none.net>
Date: Wed, 24 Mar 2004 16:33:32 +0100
Links: << >>  << T >>  << A >>
network lines wrote:

> who has the lowest price
> FPGA development kit with hardware and software included?
> Most affordable?
> Best Bang for the buck?
> So, I can learn how to program FPGAs..
> please post here..

This is the wrong question.
There is design software. Some of it, perhaps with reduced
functionality, is freely down loadable.
Then you need some time to become familiar with the
software, not to be underestimated.
As to the actual FPGA chips, there are different approaches,
depending on the number of gates/Flipflop and the speed
you require.
Unless you design for greater series, the cost of the
actual FPGA is negligible compared to the cost involved
from the design of the hardware around the FPGA and the
software inside the FPGA.

What size and speed did you have in mind ?

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 68012
Subject: Re: How many times can I burn an FPGA?
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 24 Mar 2004 07:36:47 -0800
Links: << >>  << T >>  << A >>
Martin,

How many times have you been burned by a download?

On the brighter side, if the first download doesn't succeed, download 
something different and try again!

Someone I know well once said to me that the main advantage of an FPGA 
is that it enables the engineer to make mistakes faster.  The faster 
they can make mistakes, the faster they can fix them, and the sooner the 
product makes it to market at any given quality level.  Lot of truth in 
that.  After you have done the best job you can, simulated, made test 
benches, emulated, etc. there is still the "unk unk" factor (unknown 
unknowns) and the faster they are resolved, the better.

Up, down, of course it is all relative.

It is related to the royal "we" in that the FPGA is obviously the center 
of the universe, and the but stream is sent to it in a third person 
formal sort of way.

We need a break....

Austin

Martin Euredjian wrote:

> "Hendra Gunawan" wrote:
> 
> 
>>typically how many times can I burn/download an FPGA before it becomes
>>unreliable.
> 
> 
> Burn.  Only once.  After the smoke is removed they are no longer usable.
> 
> Download. As in bit-pattern loading on power-up, no limit.
> 
> 
> Sometimes I wonder about this terminology.  When was the last time someone
> "burned" a bit pattern into a chip, really? A couple of decades ago?  Also,
> shouldn't "download" really be "upload"?   :-)
> 
> 
> 

Article: 68013
Subject: Mandrake 10 and Xilinx
From: salman sheikh <sheikh@pop500.gsfc.nasa.gov>
Date: Wed, 24 Mar 2004 11:02:18 -0500
Links: << >>  << T >>  << A >>
Hello,

Has anybody had any success with Mandrake 10 Linux and installing the 
latest Xilinx ISE 6.2 tools on such an OS.

I keep getting errors related to GLIBC_2.0 and libraries called 
commdlg44.so, whose origin lbrary package I am not too sure on...

Any help would be immensely appreciated.


Salman

Article: 68014
Subject: Re: IBUFDS -> BUFG
From: Tony <tonym_98@nospam_hotmail.com>
Date: Wed, 24 Mar 2004 16:06:45 GMT
Links: << >>  << T >>  << A >>
Ok, I still get the same errors, even using the correct MGT quadrant
this time.

What could cause the nets to be driven by multiple signals?

Thanks,
Tony


********VHDL********:  (same error with/without using the BUFG,
USER_CLK_i correctly dissapears from the netlist if not driven by a
BUFG)

    diff_clk_buff_i : IBUFGDS_LVDS_25  
    port map (
        I  => TOP_BREF_CLK_P,
        IB => TOP_BREF_CLK_N,
        O  => TOP_BREF_CLK_i
    );

    -- Bufg used to drive user clk on global clock net
    --user_clock_bufg_i : BUFG  
    --port map (
    --    I  => TOP_BREF_CLK_i,
    --    O  => USER_CLK_i
    --);
    USER_CLK_i <= TOP_BREF_CLK_i;

...
	refclksel_lane_0_i              <= '0';
	lane_0_mgt_i : GT_CUSTOM
...
                    RXUSRCLK => USER_CLK,
                    RXUSRCLK2 => USER_CLK,
                    TXUSRCLK => USER_CLK,
                    TXUSRCLK2 => USER_CLK,
                    BREFCLK => TOP_BREF_CLK,
                    BREFCLK2 => tied_to_ground_i,
                    REFCLK => tied_to_ground_i,
                    REFCLK2 => tied_to_ground_i,
                    REFCLKSEL => refclksel_lane_0_i,
...



********system.ucf********  (same error setting the BREF_CLK_P/N net
locations or not)

# Timing Contraints for the MGT Recovered clock. These period
constraints should match the 
# period used for your MGT reference clock (REFCLK, REFCLK2, BREFCLK
or BREFCLK2). This
# constraint controls the routing between each MGT's REC_CLK port and
the phase align
# module for that lane

NET
plb_gigacore_1/plb_gigacore_1/USER_LOGIC_I/auroracore_i/lane_0_mgt_i/RXRECCLK
PERIOD=6.4 ns;
...
# Sample user clock constraint
# NET plb_gigacore_1/plb_gigacore_1/USER_LOGIC_I/USER_CLK_i PERIOD =
6.4 ns;
NET plb_gigacore_1/plb_gigacore_1/USER_LOGIC_I/TOP_BREF_CLK_i PERIOD =
6.4 ns;
...
# 156.25 MHz Diff Crystal Connection
# NET BREF_CLK_P IOSTANDARD = LVDS_25;
# NET BREF_CLK_N IOSTANDARD = LVDS_25;
NET BREF_CLK_P  LOC=B14;
NET BREF_CLK_N  LOC=C14;
NET RXN LOC=A4;
NET RXP LOC=A5;
NET TXN LOC=A7;
NET TXP LOC=A6;
# Place lane_0_mgt_i at location X3Y1
INST
plb_gigacore_1/plb_gigacore_1/USER_LOGIC_I/auroracore_i/lane_0_mgt_i
LOC=GT_X3Y1;

INST
plb_gigacore_1/plb_gigacore_1/USER_LOGIC_I/auroracore_i/lane_0_mgt_i
REF_CLK_V_SEL            = 1;



*******system.mhs********
...
 PORT BREF_CLK_P = BREF_CLK_P, DIR = IN
 PORT BREF_CLK_N = BREF_CLK_N, DIR = IN
 PORT RXP = RXP, DIR = IN
 PORT RXN = RXN, DIR = IN
 PORT TXP = TXP, DIR = OUT
 PORT TXN = TXN, DIR = OUT
...
BEGIN plb_gigacore
...
 PORT RXP = RXP
 PORT RXN = RXN
 PORT TXP = TXP
 PORT TXN = TXN
 PORT TOP_BREF_CLK_P = BREF_CLK_P
 PORT TOP_BREF_CLK_N = BREF_CLK_N
END

*******ERRORSs********
ERROR:NgdBuild:455 - logical net 'BREF_CLK_N_IBUF' has multiple
drivers. The
   possible drivers causing this are:
     pin O on block ibuf_245 with type IBUF,
     pin PAD on block BREF_CLK_N_IBUF with type PAD
WARNING:NgdBuild:463 - input pad net 'BREF_CLK_N_IBUF' has an illegal
input
   buffer
ERROR:NgdBuild:466 - input pad net 'BREF_CLK_N_IBUF' has illegal
connection.
   Possible pins causing this are:
     pin O on block ibuf_245 with type IBUF
ERROR:NgdBuild:455 - logical net 'BREF_CLK_P_IBUF' has multiple
drivers. The
   possible drivers causing this are:
     pin O on block ibuf_244 with type IBUF,
     pin PAD on block BREF_CLK_P_IBUF with type PAD
WARNING:NgdBuild:463 - input pad net 'BREF_CLK_P_IBUF' has an illegal
input
   buffer
ERROR:NgdBuild:466 - input pad net 'BREF_CLK_P_IBUF' has illegal
connection.
   Possible pins causing this are:
     pin O on block ibuf_244 with type IBUF


Article: 68015
Subject: Re: PULL-UPs on Xilinx-FPGA
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 24 Mar 2004 16:35:44 GMT
Links: << >>  << T >>  << A >>
"Matija" <matija.habek@fer.hr> wrote in news:c3s994$p5$1@bagan.srce.hr:

> Hi,
> 
> how can I drive pull-up on external inout port (using VHDL)
> Thanks
> Regards, Matija
> 
> 
> 

Here's a simple snippet that uses a pullup to implement an open-collector 
bidirectional I/O.


entity foo is
port(
    	foo_pin: inout std_logic;
    	foo_cntrl: in std_logic
);
end entity foo;

architecture arch of foo is
	component pullup port(O: out std_logic); end component;
    	signal foo_pin_in: std_logic;
begin
	u0: pullup port map(O=>foo_pin); -- place pullup on foo_pin
	foo_pin <= LO when foo_cntrl='0' else 'Z'; -- open-collector output
    	foo_pin_in <= foo_pin; -- read the value on foo_pin input
end architecture arch;


-- 
|| Dr. Dave Van den Bout   XESS Corp.                 (919) 363-4695 ||
|| devb@xess.com           PO Box 33091                              ||
|| http://www.xess.com     Raleigh NC 27636 USA   FAX:(919) 367-2946 ||

Article: 68016
Subject: Re: cheapest & best FPGA???
From: "Jean Nicolle" <j.nicolle@sbcglobal.net>
Date: Wed, 24 Mar 2004 18:55:13 GMT
Links: << >>  << T >>  << A >>
Cheapest FPGA board seems to be
http://www.fpga4fun.com/board_pluto.html

but look here for more choices
http://www.fpga-faq.com/FPGA_Boards.shtml

Jean



Article: 68017
Subject: Spartan-3 Mapping error with ISE 6.1i
From: c.chen@gmx.de (Chao)
Date: 24 Mar 2004 11:46:39 -0800
Links: << >>  << T >>  << A >>
Hi, everybody.

I am using Memec Spartan-3 3s400pq208-4 device. Now I want to route
own system reset signal to Pin 207 which is available on board. But
the ISE 6.1i mapping process failed and gave me this message:
"ERROR:MapLib:681 - LOC constraint P207 on PROGRAMn_IP is invalid: No
such site on the device. To bypass this error set the environment
variable 'XIL_MAP_LOCWARN'." I do not know whether someone has idea
how to solve it. Thanks in advance.

yours: CC

Article: 68018
Subject: Re: Fried a XC2S200!
From: "Antti Lukats" <antti@case2000.com>
Date: Wed, 24 Mar 2004 12:14:12 -0800
Links: << >>  << T >>  << A >>
> : Usually a good data sheet will have a spec for how much current you
> : can safely dump into the clamp diodes.  The footnote below the
> : Absolute Max Ratings table says 10 mA.
>
> : 2K7 on (5-3) V is under 1 mA.  I'd be surprised if that damaged the
chip.
>
> : One way to kill chips is to do something that triggers latchup.
> : Have you put a scope on all the IO signals?  Could a wire have slipped
> : while you weren't watching and dumped a lot of current into an IO pin?
>
> As these chips were used chips, unsoldered, then sold and reused by Anti,
> they have  quite a long history of possible (miss-)treatment...
>
> Bye

there are no clamp diodes in XC2S200E !!!
the 2k7 resistors pulls the FPGA pin to 5V, but I assume there is almost no
current. that is surprising!

The FPGA in question is brand new soldered to 6 layer PCB it was running a
Microblaze program when during that it started to heat!
there was no one around to drop any wires onto it

I am still wondering why I have this dead FPGA

antti



Article: 68019
Subject: Re: Bus width between registers in IIR
From: "Sam \(rép. sans -no-sp-am\)" <totalsam-no-sp-am@hotmail.com>
Date: Wed, 24 Mar 2004 21:22:17 +0100
Links: << >>  << T >>  << A >>
Thank you for all these answers !

The only thing I would know is how many bits wide should I take for the
intermediate results when I use an IIR filter. The input data is 24 bit.
Should I use more than 24 bits to calculate the partial products, or not ?

Thank you !

Sam



Article: 68020
Subject: Re: Bus width between registers in IIR
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 24 Mar 2004 21:09:31 GMT
Links: << >>  << T >>  << A >>
Ray Andraka wrote:

> FPGA arithmetic can be specified to the exact number of bits,
 > not multiples of two bits.  The difference with FPGAs is you
 > don't need to carry around extra bits to make the accumulator
> a multiple of some word size.  Still, that does not
> practically affect the IIR filter design appreciably.  
 > You have the same quantization effects to worry about
 > whether you use a microprocessor with fixed
> point or an FPGA with fixed point.

Well, on a 16 bit processor the discussion goes something like:

"Is 16 bits enough, no, is 32 bits enough, yes."


In the FPGA case you have to ask about the cost and benefit
of each extra bit.  (I was considering 2 bit/CLB architectures,
but even there you don't need to use both.)  One possibility is
to choose an FPGA and then increase the bit width of intermediate
values until it doesn't fit.

-- glen


Article: 68021
Subject: Time measurement with Xilinx Spartan-3 - Help
From: mindy <mindy@hotmail.com>
Date: Wed, 24 Mar 2004 21:13:23 GMT
Links: << >>  << T >>  << A >>

 
ADVERTISEMENT
 
 
Hi All

I need some help from someone that has worked with the Xilinx
Spartan-3 products.

I need to measure a "Time Of Flight" (TOF) of a laser pulse. The
measurement time will be between 6ns and 250ns. ( Ranges from 3-125
feet)

The system has two PIN sensors - One indicates the start of pulse
leaving the laser and the second receives the return pulse from the
reflection of the laser off the target.

I'm trying to avoid using ECL and TAC analog systems for this. I only
need 1ns resolution.

I have two ideas how to do this but don't know enough about the
Spartan-3 products to know if it will work.

1) Create Four 8-bit shift registers each running off a different
phase clock source (IE: 0-90-180-270) and run them at 250mhz.
All four would be feed by the same input signal. Then store
the data from the registers in the ram. I will need to de-interlace
the data.
Once the samples have been taken, go back any search the ram for the
edge of the return pulse.
This should give me a 1ns resolution in time for the samples.

How fast can a Spartan-3 shift data ?
Will this basic concept work ?
Is the clock/sampling jitter to large to expect separate input to
sample at this rate ?
etc ?

What is the Max shift rate of the Spartan-3 FPGA's ?

2) Create Four counters with each one running off a different phase
clock source (IE: 0-90-180-270) and run them at 250mhz.
Start the counter at the same time and stop them using the input
signal from the laser receiver signal.
Once they stop I will evaluate the 4 counter for the one with the
lowest value and determine the actual TOF from it.

Same basic question from above ?

Any other suggestions for making these type of measurements ?

Thanks
Mark


Article: 68022
Subject: Re: Time measurement with Xilinx Spartan-3 - Help
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 24 Mar 2004 21:35:57 +0000 (UTC)
Links: << >>  << T >>  << A >>
mindy <mindy@hotmail.com> wrote:

:  
: ADVERTISEMENT
:  
:  
: Hi All

: I need some help from someone that has worked with the Xilinx
: Spartan-3 products.

: I need to measure a "Time Of Flight" (TOF) of a laser pulse. The
: measurement time will be between 6ns and 250ns. ( Ranges from 3-125
: feet)

...
: Any other suggestions for making these type of measurements ?
 
Look for a TDC, e.g. www.acam.de
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 68023
Subject: Re: study verilog or vhdl?
From: johnjakson@yahoo.com (john jakson)
Date: 24 Mar 2004 13:48:55 -0800
Links: << >>  << T >>  << A >>
dreamguy007@hotmail.com (Jack) wrote in message news:<b7c82826.0403232250.4e3fbf5e@posting.google.com>...
> hi. i'm just starting out with fpga. maybe this question has popped up
> many times. which one is more useful in the industry: verilog or vhdl?
> which one do you recommend for starter?
> 
> i'm also learning with a goal to implement dsp in hardware.

Take a look at the Douglas Smith book on HDL design for synthesis, the
big blue hardcover, it used to be $100 IIRC, probably one of the best
books around but not a lang ref manual for either.

It gives examples of 100s of small projects in schematic, state
diagram, explanation, Verilog & VHDL side by side.

From that you can figure which one is more natural and which fits your
style.

FWITW I'd choose Verilog as its more C syntax but thats overstated too
often. The ASIC world has been mostly Verilog if thats where you are
headed. The FPGA world and .edu, dod, and EEC has been more VHDL if
thats where you are from.

One of the things I do all the time is to code RTL style in Verilog
but with care so that the same code can be cut n pasted into C for
cycle simulation. Its not as trivial as that sounds since Verilog
syntax is far more wire/logic capable, where C uses lots of shifts &
masks. Why do I do this, so I can run cycle simulations 100...x faster
than most simulators. VHDL would be a more onerous translation I am
sure.

VHDL is a far bigger language and the war may be moot, long term
Verilog or SystemVerilog is stealing most of the remaining features it
never had from VHDL & C.

For entry level work in FPGAs the free SW from X & A seems to support
both about evenly.

regards

johnjakson_usa_com

Article: 68024
Subject: Re: Bus width between registers in IIR
From: Jerry Avins <jya@ieee.org>
Date: Wed, 24 Mar 2004 16:56:09 -0500
Links: << >>  << T >>  << A >>
Sam (rép. sans -no-sp-am) wrote:

> Thank you for all these answers !
> 
> The only thing I would know is how many bits wide should I take for the
> intermediate results when I use an IIR filter. The input data is 24 bit.
> Should I use more than 24 bits to calculate the partial products, or not ?
> 
> Thank you !
> 
> Sam

Yes
-- 
Engineering is the art of making what you want from things you can get.
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯




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