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I am very new to PAL programming. I have created a few to decode addresses. I have been using the ATMEL 16V8 PAL and WINCUPL. I now need to latch data appearing on 3 inputs when a certain condition is met on 3 other inputs. I need to latch the data on a cpu data buss D0, D1, & D2 when the signal write (WR\) is low, and the signal chip enable (CE\) is low and the signal output enable (OE\)is high, then latch the data on D0-D3. I currently have the circuit working with a 74LS02 (NOR)with the inputs tied to WR\ and OE\, the output of the NOR goes to a 74LS08 (AND)the other input is tied to OE\. The output of the AND gate feeds a 73LS273 latch. I will be latching on the falling edge of WR\ I don't have room for the 3 TTL chips so I am trying to move it to the 16V8. I am not sure how to approach the latch, any help or push in the right direction would be greatly appreciated. I have had a hard time finding examples using the latching feature. Thanks, PaulArticle: 70376
Does better math skills really equal a better engineer in the future?Article: 70377
Paul K wrote:
> I am very new to PAL programming. I have created a few to decode
> addresses. I have been using the ATMEL 16V8 PAL and WINCUPL.
>
> I now need to latch data appearing on 3 inputs when a certain
> condition is met on 3 other inputs.
>
> I need to latch the data on a cpu data buss D0, D1, & D2 when the
> signal write (WR\) is low, and the signal chip enable (CE\) is low and
> the signal output enable (OE\)is high, then latch the data on D0-D3.
>
> I currently have the circuit working with a 74LS02 (NOR)with the
> inputs tied to WR\ and OE\, the output of the NOR goes to a 74LS08
> (AND)the other input is tied to OE\. The output of the AND gate feeds
> a 73LS273 latch. I will be latching on the falling edge of WR\
>
> I don't have room for the 3 TTL chips so I am trying to move it to the
> 16V8.
>
> I am not sure how to approach the latch, any help or push in the right
> direction would be greatly appreciated. I have had a hard time
> finding examples using the latching feature.
Here is an example, of a HC259 adr latch, minus the field statements
QL = DV & WrQ /* Follow */
# !WrQ & Qfb /* Hold */
# Qfb & DV /* Overlap */
# Reset /* Reset Forces all HI -> All OFF */
;
This is a change-over MUX, but the key line is the overlap one, you need
a MAKE-before-break MUX.
An alterative if you are not pushed for pins, is to flip the WRN using
PLD resource, hard wire that to the CLK pin,
and then use WR rising edge to clock std D 16V8 registers
QL.d = Update & Di
# !Update & QL;
-jg
Article: 70378defiantly.. all that math you try to forget at school will suddenly become useful when you start calculating track impedance and capacitor reactance Simon <user@domain.invalid> wrote in message news:w8tzc.540$XFF1.47@news04.bloor.is.net.cable.rogers.com... > Does better math skills really equal a better engineer in the future? >Article: 70379
I believe that the only thing that messes up the JTAG is the PROG pin. Simon "Thierry Gschwind" <thierryg@ee.ethz.ch> wrote in message news:40ce11d3$1@pfaff2.ethz.ch... > > > Markus Meng wrote: > > Hi Thierry, > > > > difficult to say, what the problem could be, however it might be > > worthwhile to always check "support.xilin.com" and simple type in > > - as an example - "impact incorrect idcode" and read through the > > database hits. It should give you a hint or an idea howto look closer > > to your problem ... > > > > Concerning JTAG programming I think you need to disable one or the > > other option - can't remember anymore - and the problem might disappear ... > > The guys who designed the hardware hardwired M2 and M1 to ground, it's > nearly not possible to change them. > > I have read all on Xilinx Support, but nothing helped me. Also what I > read if I understan it correct, JTAG has always priority over other > programming. >Article: 70380
user@domain.invalid a écrit: > Does better math skills really equal a better engineer in the future? No, although it helps -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 70381
not exactly equal...but you will impress the client when you give the frequency of a timing path of 14.4ns without using a calculator...:) Kelvin <user@domain.invalid> wrote in message news:w8tzc.540$XFF1.47@news04.bloor.is.net.cable.rogers.com... > Does better math skills really equal a better engineer in the future? >Article: 70382
Simon Peacock wrote: > I believe that the only thing that messes up the JTAG is the PROG pin. > > Simon > > "Thierry Gschwind" <thierryg@ee.ethz.ch> wrote in message > news:40ce11d3$1@pfaff2.ethz.ch... > >> >>Markus Meng wrote: >> >>>Hi Thierry, >>> >>>difficult to say, what the problem could be, however it might be >>>worthwhile to always check "support.xilin.com" and simple type in >>>- as an example - "impact incorrect idcode" and read through the >>>database hits. It should give you a hint or an idea howto look closer >>>to your problem ... >>> >>>Concerning JTAG programming I think you need to disable one or the >>>other option - can't remember anymore - and the problem might disappear > > .... > >>The guys who designed the hardware hardwired M2 and M1 to ground, it's >>nearly not possible to change them. >> >>I have read all on Xilinx Support, but nothing helped me. Also what I >>read if I understan it correct, JTAG has always priority over other >>programming. >> > > > We had similar problems in the past with Spartan2/Virtex. Although the datasheets state that JTAG has alway priority, configuration through JTAG with the mode pins set to any but JTAG-mode failed. I once read here in the news group that that's because of the dynamic reconfiguration feature of these chips. IIRC,you would have to issue some kind of start command through JTAG to make the configuration become valid. The problem with the boot from PROM not working reminds me of own experiences when the FPGA would not start up because the PROM file was build with the startup option "JTAG-CLK" instead of "CCLK". In that case the FPGA waited after loading the bitstream for some clock pulses to appear on the JTAG TCK-line which, of course, never came. If nothing helps, you could take a look to the configuration lines with a logic analyzer to see where the problem is. (Is /PROG low for some time followed by /Init going low, too? - FPGA starts booting. Does Init return to high some times later? - Configuration RAM cleared, data stream should be shifted in now. Is there a cclk signal? - FPGA is in master serial mode, indeed. Does /Init not go low again? - Configuration bitstream has no errors? Does DONE go high, finally? - Boot was succesful.) Regards, JensArticle: 70383
"Kelvin" <student@nowhere.com> wrote in message news:40ce99dc@news.starhub.net.sg... > not exactly equal...but you will impress the client when you give the > frequency of a > timing path of 14.4ns without using a calculator...:) > > Kelvin > That's not maths skill, that's arithmetic skill. For any technical profession you need to be fast and reliable at basic arithmetic - if you have difficulty working out how a 4.7uF capacitor compares to a 4700nF capacitor, you will have problems. But no one is going to blame you for using a calculator to multiply it by a 33k resistance. Maths skill is something else - it is about logical thinking, reasoning, and analysis. The skill is in the ability to work with symbolic representations, to understand, manipulate and interprete such systems, with a care for the details and an attention to all special cases, while still being able to sort the relevant from the irrelevant. In short, maths is most important as training for your mind (although obviously particular branches of maths are directly relevant to particular branches of engineering). It's not enough on its own, but if you are not good at maths, or don't study enough maths, then you will have great difficulty being a good engineer (except perhaps a social engineer...).Article: 70384
Hi, if I want to see the content of external SRAM in simulation (Modelsim) it is no problem because the memory of the VHDL SRAM model is represented by an variable field "memdata" which I can visualize in Modelsim. But how can I see the complete content of a RAM block (created with the MegaWizard in QuartusII) in Modelsim ? The only access to the memory are the ports wraddress, rdaddress ... Is there a way to look at the content? Thank you for your help. Kind regardsArticle: 70385
On 14 Jun 2004 18:38:54 -0700, accrg@accrepairs.com (Paul K) wrote:
>I am very new to PAL programming. I have created a few to decode
>addresses. I have been using the ATMEL 16V8 PAL and WINCUPL.
>
>I now need to latch data appearing on 3 inputs when a certain
>condition is met on 3 other inputs.
>
>I need to latch the data on a cpu data buss D0, D1, & D2 when the
>signal write (WR\) is low, and the signal chip enable (CE\) is low and
>the signal output enable (OE\)is high, then latch the data on D0-D3.
>
>I currently have the circuit working with a 74LS02 (NOR)with the
>inputs tied to WR\ and OE\, the output of the NOR goes to a 74LS08
>(AND)the other input is tied to OE\. The output of the AND gate feeds
>a 73LS273 latch. I will be latching on the falling edge of WR\
>
>I don't have room for the 3 TTL chips so I am trying to move it to the
>16V8.
>
>I am not sure how to approach the latch, any help or push in the right
>direction would be greatly appreciated. I have had a hard time
>finding examples using the latching feature.
>
>Thanks, Paul
My CUPL is a little rusty so excuse any punctuation errors...
pin[2..5] = [d0..3];
pin[12..15] = [q0..3];
pin[6,7,8] = [!ce,!oe,!wr];
field din=[d0..3];
field dout=[q0..3];
enable = !CE & OE & !WR;
dout = !enable & dout /* hold latch contents by feeding output back to input */
# enable & din;
Article: 70386Hi, I am currently using an APEX20KE device. When using the altclklock megafunction, I use OPERATION_MODE = NORMAL. I would like to know what is the function of the CLKLK_FB pin when in this mode? Does it act as a normal I/O? Thanks a lot! - Paulo ValentimArticle: 70387
it's true... but it's no big deal to calculate 47X33 anyway... arithmetic is part of mathematics...every engineer needs to be proficient in math... Kelvin "David Brown" <david@no.westcontrol.spam.com> wrote in message news:cam9d4$npo$1@news.netpower.no... > > "Kelvin" <student@nowhere.com> wrote in message > news:40ce99dc@news.starhub.net.sg... > > not exactly equal...but you will impress the client when you give the > > frequency of a > > timing path of 14.4ns without using a calculator...:) > > > > Kelvin > > > > That's not maths skill, that's arithmetic skill. > > For any technical profession you need to be fast and reliable at basic > arithmetic - if you have difficulty working out how a 4.7uF capacitor > compares to a 4700nF capacitor, you will have problems. But no one is going > to blame you for using a calculator to multiply it by a 33k resistance. > > Maths skill is something else - it is about logical thinking, reasoning, and > analysis. The skill is in the ability to work with symbolic > representations, to understand, manipulate and interprete such systems, with > a care for the details and an attention to all special cases, while still > being able to sort the relevant from the irrelevant. In short, maths is > most important as training for your mind (although obviously particular > branches of maths are directly relevant to particular branches of > engineering). > > It's not enough on its own, but if you are not good at maths, or don't study > enough maths, then you will have great difficulty being a good engineer > (except perhaps a social engineer...). > > >Article: 70388
Hi, I want to perform a timing simulation in Modelsim. For that purpose it is necessary to do a library mapping for the Altera Cyclone library. In Modelsim (Altera 5.7e) there is a library called "Cyclone", I think it is a precompiled library. When reading the Altera Modelsim manual there is explained the following: "If using Model Technology's Modelsim, first create the device family library and map it to the work library. Next compile the device family ATOM library files into the device family library. Refer to the section titled "Location of Simulation Libraries" for the location of these files". Location of Timing Simulation Libraries for ModelSim-Altera for VHDL LIBRARY VHDL cyclone d:\programs\modelsim57e\altera\vhdl\cyclone\ That sound somehow confusing to me. My questions: 1. How can I create a device family library if it already exists? 2. How can I compile the ATOM library files into the device family library? Without the mapping of course I get the following error message: #**Fatal: SDF files require Altera primitive library I would appreciate your help. Kind regardsArticle: 70389
Hi I want to build an application with linux running in virtex2pro with ethernet and usb. Now I want to calculate. How much, do I have to invest? For this calculation I have to know which components I need. Can anybody give me a hint? Which evaluation board is best, to evaluate linux in Virtex II Pro PowerPC core? Which components are really necessary? I start from zero, so I think I need: SW-development: Xilinx EDK IBM RiscWatch? HW-Debugger Xilinx Chipscope Verilog Devel.: ISE BaseX + Simulator Parallel Cable IV Evaluationboard: Virtex2 Pro SDRAM Interface JTAG, TRACE SystemACE ? USB Interface Ehternet Interface Xilinx: ML300 (it is not availible from Xilinx online store?) avnet: Virtex-II Pro Evaluation Kit Memec Design: Virtex-II Pro FG456 Do I miss something? FrankArticle: 70390
Hallo, i want to add my IP-CORE to Microblaze in FPGA with the IPIF template. i have changed the template according to the documentation and have successfully generated the netlist. Now i import it to ISE. But when i open ISE Project file(system.npl), i could not find my ip-core, just "system_stub.vhd" and system.vhd". so i added the wrappe for my ip-core(it named "my_counter_wrappe.vhd") and the VHDL files of my IP-core. During generating Programming File of system_stub.vhd (top-level) there was error that "Library proc_common_v1_00_b cannot be found". Should i add my ip-core to the system just like above, or there was still problem in EDK, when i have not my IP-Core in ISE automatically at the beginning? what should be the right steps to generate a bit-file in ISE with my IP-Core and then i can import the bit-file back to EDK? thanks for your advice and it will help me so much. krebsArticle: 70391
"Kelvin" <student@nowhere.com> wrote in message news:40cece16$1@news.starhub.net.sg... > it's true... > > but it's no big deal to calculate 47X33 anyway... > > arithmetic is part of mathematics...every engineer needs to be proficient in > math... > > Kelvin > Arithmetic is to maths what letters are to English, or perhaps what handwriting is to essay-writing - you can get a computer to help with the larger stuff as long as you understand what you are doing, but it's going to be a pain if you need a computer for every little note, and being able to write well does not make you a good essay writer. There are three sorts of mathematicians - those who can count, and those who can't. There are 10 sorts of software engineers - those that understand binary, and those who don't. Anyway, we agree that an engineer needs to be good at maths. David > > > > > "David Brown" <david@no.westcontrol.spam.com> wrote in message > news:cam9d4$npo$1@news.netpower.no... > > > > "Kelvin" <student@nowhere.com> wrote in message > > news:40ce99dc@news.starhub.net.sg... > > > not exactly equal...but you will impress the client when you give the > > > frequency of a > > > timing path of 14.4ns without using a calculator...:) > > > > > > Kelvin > > > > > > > That's not maths skill, that's arithmetic skill. > > > > For any technical profession you need to be fast and reliable at basic > > arithmetic - if you have difficulty working out how a 4.7uF capacitor > > compares to a 4700nF capacitor, you will have problems. But no one is > going > > to blame you for using a calculator to multiply it by a 33k resistance. > > > > Maths skill is something else - it is about logical thinking, reasoning, > and > > analysis. The skill is in the ability to work with symbolic > > representations, to understand, manipulate and interprete such systems, > with > > a care for the details and an attention to all special cases, while still > > being able to sort the relevant from the irrelevant. In short, maths is > > most important as training for your mind (although obviously particular > > branches of maths are directly relevant to particular branches of > > engineering). > > > > It's not enough on its own, but if you are not good at maths, or don't > study > > enough maths, then you will have great difficulty being a good engineer > > (except perhaps a social engineer...). > > > > > > > >Article: 70392
Hi all,
I'm using the code below to generate a pulse which is 16x57600 from a
51.2 MHz clock signal to controll the sampling in a rs232 module. The
pulse generator does not work however. It generats a constant high
signal instead of a 921.6 kHz pulse.
Can anyone see what might be faulty with my design? I'm clueless...
/Johan
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity baud16 is
port(
Clk : in std_logic;
baud_pulse : out std_logic);
end entity baud16;
architecture imp of baud16 is
attribute BOX_TYPE : string;
component SRL16E is
-- synthesis translate_off
generic (
INIT : bit_vector := X"0000"
);
-- synthesis translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic
);
end component SRL16E;
attribute BOX_TYPE of SRL16E : component is "BLACK_BOX";
component FD is
port (
C : in std_logic;
D : in std_logic;
Q : out std_logic);
end component FD;
attribute BOX_TYPE of FD : component is "BLACK_BOX";
signal clkdv56 : std_logic;
signal clkdv56_i1 : std_logic;
signal clkdv56_i2 : std_logic;
signal clkdv56_i3 : std_logic;
-- signal clkdv14_4 : std_logic;
signal baud_pulse_i : std_logic;
begin
--Denna SRL dividerar inklockan med 14
Del_8 : SRL16E
--synthesis translate_off
generic map (
INIT => X"0000")
--synthesis translate_on
port map (
CE => '1', -- [in std_logic]
D => clkdv56, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '0', -- [in std_logic]
Q => clkdv56_i1); -- [out std_logic]
Del_16_1 : SRL16E
--synthesis translate_off
generic map (
INIT => X"0000")
--synthesis translate_on
port map (
CE => '1', -- [in std_logic]
D => clkdv56_i1, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q => clkdv56_i2); -- [out std_logic]
Del_16_2 : SRL16E
--synthesis translate_off
generic map (
INIT => X"0000")
--synthesis translate_on
port map (
CE => '1', -- [in std_logic]
D => clkdv56_i2, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q => clkdv56_i3); -- [out std_logic]
Del_16_3 : SRL16E
--synthesis translate_off
generic map (
INIT => X"0001")
--synthesis translate_on
port map (
CE => '1', -- [in std_logic]
D => clkdv56_i3, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q => clkdv56); -- [out std_logic]
DFF : FD
port map (
C => Clk, -- [in std_logic]
D => clkdv56, -- [in std_logic]
Q => baud_pulse); -- [out std_logic]
end architecture imp;
Article: 70393"Johan Bernspång" <johbe@foi.se> wrote >Hi all, >I'm using the code below to generate a pulse which is 16x57600 from a >51.2 MHz clock signal to controll the sampling in a rs232 module. The >pulse generator does not work however. It generats a constant high >signal instead of a 921.6 kHz pulse. > >Can anyone see what might be faulty with my design? I'm clueless... > >/Johan Hi Johan, the SRL16E components in your design are not initialized for synthesis. Dependent on your synthesis tool, either delete the "synthesis translate_on/off" lines or add attributes with INIT values for the SRL16E components. Hope this helps, MichaelArticle: 70394
Tjena Johan, You can't directly connect the output from on SRL16 to the next one. It only works for the first SRL16. The other SRL16 will have it's output high for many clock cycles which creates the constant high signal. For the other SRL16, you need to clean the signal to only be high for one clock cycle. Göran Bilski Johan Bernspång wrote: > Hi all, > > I'm using the code below to generate a pulse which is 16x57600 from a > 51.2 MHz clock signal to controll the sampling in a rs232 module. The > pulse generator does not work however. It generats a constant high > signal instead of a 921.6 kHz pulse. > > Can anyone see what might be faulty with my design? I'm clueless... > > /Johan > > > library IEEE; > use IEEE.std_logic_1164.all; > > library unisim; > use unisim.vcomponents.all; > > entity baud16 is > port( > Clk : in std_logic; > baud_pulse : out std_logic); > end entity baud16; > > architecture imp of baud16 is > > attribute BOX_TYPE : string; > component SRL16E is > -- synthesis translate_off > generic ( > INIT : bit_vector := X"0000" > ); > -- synthesis translate_on > port ( > CE : in std_logic; > D : in std_logic; > Clk : in std_logic; > A0 : in std_logic; > A1 : in std_logic; > A2 : in std_logic; > A3 : in std_logic; > Q : out std_logic > ); > end component SRL16E; > attribute BOX_TYPE of SRL16E : component is "BLACK_BOX"; > > component FD is > port ( > C : in std_logic; > D : in std_logic; > Q : out std_logic); > end component FD; > attribute BOX_TYPE of FD : component is "BLACK_BOX"; > > > signal clkdv56 : std_logic; > signal clkdv56_i1 : std_logic; > signal clkdv56_i2 : std_logic; > signal clkdv56_i3 : std_logic; > -- signal clkdv14_4 : std_logic; > signal baud_pulse_i : std_logic; > begin > > > --Denna SRL dividerar inklockan med 14 > Del_8 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0000") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '0', -- [in std_logic] > Q => clkdv56_i1); -- [out std_logic] > > Del_16_1 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0000") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56_i1, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '1', -- [in std_logic] > Q => clkdv56_i2); -- [out std_logic] > > Del_16_2 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0000") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56_i2, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '1', -- [in std_logic] > Q => clkdv56_i3); -- [out std_logic] > > Del_16_3 : SRL16E > --synthesis translate_off > generic map ( > INIT => X"0001") > --synthesis translate_on > port map ( > CE => '1', -- [in std_logic] > D => clkdv56_i3, -- [in std_logic] > Clk => Clk, -- [in std_logic] > A0 => '1', -- [in std_logic] > A1 => '1', -- [in std_logic] > A2 => '1', -- [in std_logic] > A3 => '1', -- [in std_logic] > Q => clkdv56); -- [out std_logic] > > > > DFF : FD > port map ( > C => Clk, -- [in std_logic] > D => clkdv56, -- [in std_logic] > Q => baud_pulse); -- [out std_logic] > > end architecture imp;Article: 70395
Hi,
Instead of you spending time creating the code, I have attached some
modules.
The baud_rate module will produce the signal that you want.
The module is however a little more flexible and allows you to specify
the ratio that you want to divide the incoming clock.
The module will find all the factors between 2-16 which makes up the ratio.
The problem is when the ratio is a prim number and thus can't be split
up into factors.
The module will then return to a standard counter for implementing the
function.
For some application, the ratio doesn't need to be exact and there are
some inaccuracy allowed. UARTs has this flexibility.
So you can specify an inaccuracy which allows the modules to search for
values around the ratio which can be split into factors.
The cleaning of the signal for the SRL16 can be done in a LUT (you need
an AND gate) but I have used two DFFs for doing the same function in
order to save some LUTs.
The code is a good example of what VHDL can do.
Göran
Johan Bernspång wrote:
> Hi all,
>
> I'm using the code below to generate a pulse which is 16x57600 from a
> 51.2 MHz clock signal to controll the sampling in a rs232 module. The
> pulse generator does not work however. It generats a constant high
> signal instead of a 921.6 kHz pulse.
>
> Can anyone see what might be faulty with my design? I'm clueless...
>
> /Johan
>
>
> library IEEE;
> use IEEE.std_logic_1164.all;
>
> library unisim;
> use unisim.vcomponents.all;
>
> entity baud16 is
> port(
> Clk : in std_logic;
> baud_pulse : out std_logic);
> end entity baud16;
>
> architecture imp of baud16 is
>
> attribute BOX_TYPE : string;
> component SRL16E is
> -- synthesis translate_off
> generic (
> INIT : bit_vector := X"0000"
> );
> -- synthesis translate_on
> port (
> CE : in std_logic;
> D : in std_logic;
> Clk : in std_logic;
> A0 : in std_logic;
> A1 : in std_logic;
> A2 : in std_logic;
> A3 : in std_logic;
> Q : out std_logic
> );
> end component SRL16E;
> attribute BOX_TYPE of SRL16E : component is "BLACK_BOX";
>
> component FD is
> port (
> C : in std_logic;
> D : in std_logic;
> Q : out std_logic);
> end component FD;
> attribute BOX_TYPE of FD : component is "BLACK_BOX";
>
>
> signal clkdv56 : std_logic;
> signal clkdv56_i1 : std_logic;
> signal clkdv56_i2 : std_logic;
> signal clkdv56_i3 : std_logic;
> -- signal clkdv14_4 : std_logic;
> signal baud_pulse_i : std_logic;
> begin
>
>
> --Denna SRL dividerar inklockan med 14
> Del_8 : SRL16E
> --synthesis translate_off
> generic map (
> INIT => X"0000")
> --synthesis translate_on
> port map (
> CE => '1', -- [in std_logic]
> D => clkdv56, -- [in std_logic]
> Clk => Clk, -- [in std_logic]
> A0 => '1', -- [in std_logic]
> A1 => '1', -- [in std_logic]
> A2 => '1', -- [in std_logic]
> A3 => '0', -- [in std_logic]
> Q => clkdv56_i1); -- [out std_logic]
>
> Del_16_1 : SRL16E
> --synthesis translate_off
> generic map (
> INIT => X"0000")
> --synthesis translate_on
> port map (
> CE => '1', -- [in std_logic]
> D => clkdv56_i1, -- [in std_logic]
> Clk => Clk, -- [in std_logic]
> A0 => '1', -- [in std_logic]
> A1 => '1', -- [in std_logic]
> A2 => '1', -- [in std_logic]
> A3 => '1', -- [in std_logic]
> Q => clkdv56_i2); -- [out std_logic]
>
> Del_16_2 : SRL16E
> --synthesis translate_off
> generic map (
> INIT => X"0000")
> --synthesis translate_on
> port map (
> CE => '1', -- [in std_logic]
> D => clkdv56_i2, -- [in std_logic]
> Clk => Clk, -- [in std_logic]
> A0 => '1', -- [in std_logic]
> A1 => '1', -- [in std_logic]
> A2 => '1', -- [in std_logic]
> A3 => '1', -- [in std_logic]
> Q => clkdv56_i3); -- [out std_logic]
>
> Del_16_3 : SRL16E
> --synthesis translate_off
> generic map (
> INIT => X"0001")
> --synthesis translate_on
> port map (
> CE => '1', -- [in std_logic]
> D => clkdv56_i3, -- [in std_logic]
> Clk => Clk, -- [in std_logic]
> A0 => '1', -- [in std_logic]
> A1 => '1', -- [in std_logic]
> A2 => '1', -- [in std_logic]
> A3 => '1', -- [in std_logic]
> Q => clkdv56); -- [out std_logic]
>
>
>
> DFF : FD
> port map (
> C => Clk, -- [in std_logic]
> D => clkdv56, -- [in std_logic]
> Q => baud_pulse); -- [out std_logic]
>
> end architecture imp;
-------------------------------------------------------------------------------
-- $Id: baudrate.vhd,v 1.2 2003/01/16 22:32:37 tise Exp $
-------------------------------------------------------------------------------
-- baudrate.vhd
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: baudrate.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- baudrate.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2003/01/16 22:32:37 $
--
-- History:
-- goran 2001-06-12 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Baud_Rate is
generic (
C_USE_FIXED : integer := 1; -- Fixed baudrate
C_RATIO : integer := 814; -- The ratio between clk and the asked
-- baudrate multiplied with 16
C_INACCURACY : integer := 15 -- The maximum inaccuracy of the clk
); -- division in per thousands
port (
Clk : in std_logic;
Div_Factor : in std_logic_vector(0 to 15);
EN_16x_Baud : out std_logic);
end entity Baud_Rate;
library unisim;
use unisim.all;
library opb_uartlite_v2_00_a;
use opb_uartlite_v2_00_a.Divide_Part;
architecture VHDL_RTL of Baud_Rate is
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component Divide_Part is
generic (
Ratio : natural;
First : boolean);
port (
Clk : in std_logic;
Clk_En : in std_logic;
Clk_En_Out : out std_logic);
end component Divide_Part;
-- log2 function returns the number of bits required to encode x choices
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
-----------------------------------------------------------------------------
-- Calculate the number of SRL16s needed for the Ratio R
-----------------------------------------------------------------------------
constant MAX_DIV_FACTOR : natural := 16;
subtype SRL16_DIV_TYPE is natural range 2 to MAX_DIV_FACTOR;
type FACTORS_LIST_TYPE is array (natural range 1 to 15) of SRL16_DIV_TYPE;
type FACTORS_TYPE is
record
Good_Divide : boolean;
Nr_Of_Factors : natural;
Factor_List : FACTORS_LIST_TYPE;
end record FACTORS_TYPE;
-----------------------------------------------------------------------------
-- Trying to divide R into integer values of values 2-16 until the end result
-- is between 2-16.
-----------------------------------------------------------------------------
function Get_Factors (R : natural) return FACTORS_TYPE is
variable N : natural := R;
variable Result : FACTORS_TYPE;
variable no : natural := 1;
variable Found : boolean;
begin -- function Get_Factors
if (N < 16) then
Result.FACTOR_LIST(1) := N;
Result.Nr_Of_Factors := 1;
Result.Good_Divide := true;
return Result;
end if;
while N /= 1 loop
Found := false;
for I in 16 downto 2 loop
if ((N mod I = 0)) then -- Found factor
Result.FACTOR_LIST(no) := I;
N := N / I;
no := no + 1;
Found := true;
exit;
end if;
end loop; -- I
if (not(Found)) then
Result.Good_Divide := false;
exit;
end if;
end loop;
if (found) then
Result.Good_Divide := true;
Result.Nr_Of_Factors := no-1;
end if;
return Result;
end function Get_Factors;
-----------------------------------------------------------------------------
-- Trying to find a ratio that is within 1.5% of the asked ratio and that the
-- ratio can be implemented with SRL16.
-----------------------------------------------------------------------------
function Find_Best_Factors (R : natural) return FACTORS_TYPE is
constant Proc_Diff : natural := R*C_INACCURACY/1000; -- Calculate the max difference
-- for the maximum inaccuracy
variable Result : FACTORS_TYPE;
begin -- function Find_Best_Factors
Result := Get_Factors(R);
if (Result.Good_Divide) then
return Result;
end if;
for I in 1 to Proc_Diff loop
Result := Get_Factors(R+I);
if (Result.Good_Divide) then
return Result;
end if;
Result := Get_Factors(R-I);
if (Result.Good_Divide) then
return Result;
end if;
end loop; -- I
Result.Good_Divide := false;
return Result;
end function Find_Best_Factors;
constant Divide_Factors : FACTORS_TYPE := Find_Best_Factors(C_RATIO);
signal Clk_En_I : std_logic_vector(0 to Divide_Factors.Nr_Of_Factors);
signal Count : std_logic_vector(0 to 15);
begin -- architecture VHDL_RTL
Using_Fixed_Baudrate : if (C_USE_FIXED /= 0) generate
-----------------------------------------------------------------------------
-- A clean and good ratio was found that was within the 1.5% limit, so
-- implement the uartlite division using SRL16s
-----------------------------------------------------------------------------
Using_SRL16s : if (Divide_Factors.Good_Divide) generate
Clk_En_I(0) <= '1';
SRL16s : for I in 1 to Divide_Factors.Nr_Of_Factors generate
Divide_I : Divide_Part
generic map (
Ratio => Divide_Factors.FACTOR_LIST(I), -- [natural range 2 to 16]
First => (I = 1)) -- [boolean]
port map (
Clk => Clk, -- [in std_logic]
Clk_En => Clk_En_I(I-1), -- [in std_logic]
Clk_En_Out => Clk_En_I(I)); -- [out std_logic]
end generate SRL16s;
En_16x_Baud <= Clk_En_I(Divide_Factors.Nr_Of_Factors);
end generate Using_SRL16s;
-----------------------------------------------------------------------------
-- Couldn't find a good ratio within the 1.5% limit so implement the uartlite
-- generation using a standard counter
-----------------------------------------------------------------------------
Using_Counter : if (not Divide_Factors.Good_Divide) generate
constant Nr_Of_Bits : natural := log2(C_RATIO-1);
constant New_Value : std_logic_vector(0 to Nr_Of_Bits-1) :=
std_logic_vector(to_unsigned(C_RATIO-1, Nr_Of_Bits));
signal Cnt : std_logic_vector(0 to Nr_Of_Bits-1);
signal New_Cnt : std_logic_vector(0 to Nr_Of_Bits-1);
signal Carry : std_logic_vector(0 to Nr_Of_Bits);
signal Count : std_logic_vector(0 to Nr_Of_Bits-1);
begin
Carry(0) <= '0'; -- Always subracting
All_Bits : for I in 0 to Nr_Of_Bits-1 generate
New_Cnt(I) <= not(Count(I)) when Carry(Nr_Of_Bits) = '0' else New_Value(I);
MUXCY_L_I1 : MUXCY_L
port map (
DI => '0', -- [in std_logic]
CI => Carry(I), -- [in std_logic]
S => New_Cnt(I), -- [in std_logic]
LO => Carry(I+1)); -- [out std_logic]
XORCY_I1 : XORCY
port map (
LI => New_Cnt(I), -- [in std_logic]
CI => Carry(I), -- [in std_logic]
O => Cnt(I)); -- [out std_logic]
end generate All_Bits;
Counter : process (Clk) is
begin -- process Counter
if Clk'event and Clk = '1' then -- rising clock edge
Count <= Cnt;
end if;
end process Counter;
En_16x_Baud <= Carry(Nr_Of_Bits);
end generate Using_Counter;
end generate Using_Fixed_Baudrate;
Dynamic_Baudrate: if (C_USE_FIXED = 0) generate
Counter : process (Clk) is
begin -- process Counter
if Clk'event and Clk = '1' then -- rising clock edge
if (Count = "0000000000000000") then
Count <= Div_Factor;
EN_16x_Baud <= '1';
else
Count <= std_logic_vector(unsigned(Count) - 1);
EN_16x_Baud <= '0';
end if;
end if;
end process Counter;
end generate Dynamic_Baudrate;
end architecture VHDL_RTL;
===========================================================================
-------------------------------------------------------------------------------
-- $Id: divide_part.vhd,v 1.2 2003/02/13 16:13:28 goran Exp $
-------------------------------------------------------------------------------
-- divide_part.vhd - Entity and architecture
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: divide_part.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- divide_part.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.2 $
-- Date: $Date: 2003/02/13 16:13:28 $
--
-- History:
-- goran 2003-02-13 First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity Divide_part is
generic (
Ratio : natural;
First : boolean := true
);
port (
Clk : in std_logic;
Clk_En : in std_logic;
Clk_En_Out : out std_logic
);
end entity Divide_part;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture VHDL_RTL of Divide_part is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000");
-- pragma translate_on
port (
Q : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
Clk : in std_logic;
D : in std_logic
);
end component SRL16E;
component SRLC16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000");
-- pragma translate_on
port (
Q : out std_logic;
Q15 : out std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
CE : in std_logic;
Clk : in std_logic;
D : in std_logic
);
end component SRLC16E;
signal loop_Bit : std_logic;
attribute INIT : string;
constant Nr_Of_SRL16 : natural := 1 + ((Ratio-1)/16);
constant Last_SRL16_Ratio : natural := ((Ratio-1) mod 16);
constant A : std_logic_vector(3 downto 0) :=
std_logic_vector(to_unsigned(Last_SRL16_Ratio, 4));
signal shifts : std_logic_vector(0 to Nr_Of_SRL16);
signal Emptys : std_logic_vector(0 to Nr_Of_SRL16);
begin -- architecture VHDL_RTL
One_SRL16 : if (Nr_Of_SRL16 = 1) generate
attribute INIT of SRL16E_I : label is "0001";
begin
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => X"0001") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => loop_Bit, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => A(0), -- [in std_logic]
A1 => A(1), -- [in std_logic]
A2 => A(2), -- [in std_logic]
A3 => A(3), -- [in std_logic]
Q => loop_Bit); -- [out std_logic]
end generate One_SRL16;
Two_SRL16 : if (Nr_Of_SRL16 = 2) generate
attribute INIT of SRLC16E_1 : label is "0001";
attribute INIT of SRL16E_2 : label is "0000";
begin
-- The first SRLC16E
SRLC16E_1 : SRLC16E
-- pragma translate_off
generic map (
INIT => X"0001") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => loop_Bit, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q15 => shifts(1), -- [out std_logic]
Q => Emptys(1)); -- [out std_logic]
SRL16E_2 : SRL16E
-- pragma translate_off
generic map (
INIT => X"0000") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => shifts(1), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => A(0), -- [in std_logic]
A1 => A(1), -- [in std_logic]
A2 => A(2), -- [in std_logic]
A3 => A(3), -- [in std_logic]
Q => loop_Bit); -- [out std_logic]
end generate Two_SRL16;
More_Than_Two : if (Nr_Of_SRL16 > 2) generate
attribute INIT of SRLC16E_1 : label is "0001";
attribute INIT of SRL16E_n : label is "0000";
begin
-- The first SRLC16E
SRLC16E_1 : SRLC16E
-- pragma translate_off
generic map (
INIT => X"0001") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => loop_Bit, -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q15 => shifts(1), -- [out std_logic]
Q => Emptys(1)); -- [out std_logic]
The_Rest : for I in 2 to Nr_Of_SRL16-2 generate
attribute INIT of SRLC16E_I : label is "0000";
begin
SRLC16E_I : SRLC16E
-- pragma translate_off
generic map (
INIT => X"0000") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => shifts(I-1), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => '1', -- [in std_logic]
A1 => '1', -- [in std_logic]
A2 => '1', -- [in std_logic]
A3 => '1', -- [in std_logic]
Q15 => shifts(I), -- [out std_logic]
Q => Emptys(I)); -- [out std_logic]
end generate The_Rest;
-- The last SRL16
SRL16E_n : SRL16E
-- pragma translate_off
generic map (
INIT => X"0000") -- [bit_vector]
-- pragma translate_on
port map (
CE => Clk_En, -- [in std_logic]
D => shifts(Nr_Of_SRL16-2), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => A(0), -- [in std_logic]
A1 => A(1), -- [in std_logic]
A2 => A(2), -- [in std_logic]
A3 => A(3), -- [in std_logic]
Q => loop_Bit); -- [out std_logic]
end generate More_Than_Two;
-----------------------------------------------------------------------------
-- If the SRL16 is the first in a serie then the output is a clean single
-- clock pulse
-----------------------------------------------------------------------------
Is_First : if (First) generate
Clk_En_Out <= loop_Bit;
end generate Is_First;
-----------------------------------------------------------------------------
-- If not the first the output has to be masked so that it produce a single
-- clock pulse
-----------------------------------------------------------------------------
not_First : if (not First) generate
signal Out1 : std_logic;
begin
Out1_DFF : process (Clk) is
begin -- process Out1_DFF
if Clk'event and Clk = '1' then -- rising clock edge
Out1 <= loop_Bit;
end if;
end process Out1_DFF;
Out2_DFF : process (Clk) is
begin -- process Out2_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if (Out1 = '1') then
Clk_En_Out <= Clk_En;
end if;
end if;
end process Out2_DFF;
end generate not_First;
end architecture VHDL_RTL;
Article: 70396Engineer math skill is what remains after you forget everything in school, and what's gain from works.Article: 70397
Hello Peter, Did you mean the slave FPGA? Thats the one that is giving trouble and starts programming 1ms earlier than master. What factors can cause this on a FPGA? Both master and slave share the ground and power planes. Is the poweron voltage ramp causing the issue? Since they both share power planes it should affect both the same way. So poweron voltage ramp is probably not the issue. Thanks for taking time out to respond. Brijesh Peter Alfke wrote: > It seems to me that the Master tries to start programming too early after > power-up. > > Peter Alfke > ============= > >>From: Brijesh <brijesh_xyz@cfrsi_xyz.com> >>Organization: Virginia Tech, Blacksburg, Virginia, USA >>Newsgroups: comp.arch.fpga >>Date: Mon, 14 Jun 2004 16:50:38 -0400 >>Subject: FPGA serial programming troubles. (Virtex II) >> >>We have a board with 2 Virtex II 6000 devices. They are programmed from >>independent bank of serial eeproms in Master serial mode. >> >>One of the FPGA's (slave fpga) is not being programmed consistently. On >>power up it sometimes programs and at times fails. If after powerup we >>manually start a programming cycle by pulling program pin low, it >>programs properly. Observed INIT pin going low before DONE goes high on >>slave FPGA, indicating CRC error. >> >>Also observed that slave FPGA initiates the program cycle earlier and >>has higher serial clock frequency than master.(using the lowest >>frequency 4 MHz) >> >>Hooked up logic analyzer and counted the clock cycles in the programming >>cycle. The slave FPGA clock count varies, both when it fails and when >>it programs(manual program intiation). When it fails it is lower than >>the required count but varies from one try to another. When it succeeds >>it is higher than required and also vaires from one try to another. >> >>Master FPGA clock count is always the same. >> >>Any suggestions on what could be causing this problem? >> >>Thanks >>Brijesh > >Article: 70398
Kelvin <student@nowhere.com> wrote: : it's true... : but it's no big deal to calculate 47X33 anyway... Well, start with 50X30 , we're engineers :-) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 70399
Hi, I'm currently working on a project at my university for testing and developing rate based protocols and I've been having some problems with my dev board. I've been using the Altera Nios proffesional dev board (with stratix FPGA). So far I've ran tests with UDP (over 2 dev boards) to test the utilization of my network, which is 100 Mbps and I keep getting numbers just under 10 Mbps. I've done tests on the lines over PC's and they achieve over 40 so I know the line is not the problem. The only thing I can see is that maybe the Ethernet/PHY chip they use defaults to 10 Mbps, even though it says it auto detects to 100 or 10. I was wondering if anyone has experience with the low level libraries, like lan91c111.c, and could point me in the right direction. I would be satisfied to just get a printout of the register status to see if it is acutally setting itself to 10 Mbps. I've tried to use nr_lan91c111_dump_registers() but it won't give me a printout of the register banks. The lack of documentation also doesn't really help. Any help would be great. Thanks, Justin.
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