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I'm using ise webpack 6.2.03i through wine on redhat 9. After xst, when I tried to run ngdbuild i got the follwing message: --------------------------------------------------------------------------- FATAL_ERROR:NgdBuild:basnbmain.c:2531:1.90.4.3 - An error has occured in initializing the ngdbuild scripting system. Please set the 'XIL_NGDBUILD_OLDFLOW' environment variable to '1' to resolve this problem, or update the Xilinx tool installation. The following scripting error was reported: 'couldn't read file "/auto/wine-windows/ise6/bin/xilinx-init.tcl": no such file or directory'. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com --------------------------------------------------------------------------- I have to use "setenv XIL_NGDBUILD_OLDFLOW 1" to let it run through "old command flow". I'm pretty sure I can read file "xilinx-init.tcl". I found nothing on support.xilinx.com about that. Am I missing some steps? I ran ngdbuild right after xst. I can ran that using ise GUI w/o problem. Or does I miss any file in linux? I just copied the whole folder of ise6 to my linux machine. Anybody has any suggestion for that? Thanks, PZArticle: 71526
Never heard of... "John Carter" <cyent@xtra.co.nz> wrote in message news:55adf176.0407170137.24a5c25b@posting.google.com... > Does anyone know of a supplier of FPGA's in compact flash format? > > (Yes, I know of FPGA development boards that have slots for compact > flash storage devices.) > > Compact Flash is a flexible standard that extends way beyond just > flash storage devices. You can get GPS's, wireless LAN's, ADC/DAC's > etc. etc. in Compact Flash format. > > What I want is to be able to plug an FPGA into my Sharp Zaurus PDA > (which has a Compact Flash slot and embedded Linux) and use the PDA as > the user interface to the FPGA.Article: 71527
Hi, I have a directory called "TOP_PROJECT" in which I have several submodules. These submodules include VHDL files among each other. That can be done in QuartusII -->Projekt --> Add/Remove Files in Project There you have to specify the path of the VHDL file you want to include. But what if I want to change the name of "TOP_PROJECT" directory to "TOP_PROJECT_X" ? Is that a problem? Are the VHDL files still included correctly? And what if I change the directory name of a submodule ? Does Quartus update the "links" by itself or do I have to change the links manually? Thank you for your help. Kind regardsArticle: 71528
"ernie" <ernielin@gmail.com> wrote in message news:d7fe9825.0407191638.58b29e0c@posting.google.com... > Hi, > > Can anyone recommend any good (and cheap) 32-channel analyzers? By > cheap I mean less than or approximately $1000. It would be nice if > the software supported complex triggering and the analyzer had > decently fast sampling rates. Sample depth is not really a critical > issue but more is obviously better. Ernie, what do you mean by 'decently' fast? 100Msps, 500Msps? Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board www.nialstewartdevelopments.co.ukArticle: 71529
"ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0407202330.41ee13a0@posting.google.com... > Hi, > > I have a directory called "TOP_PROJECT" in which I have several submodules. > > These submodules include VHDL files among each other. That can be done > in QuartusII -->Projekt --> Add/Remove Files in Project > There you have to specify the path of the VHDL file you want to include. > > But what if I want to change the name of "TOP_PROJECT" directory to > "TOP_PROJECT_X" ? > Is that a problem? Are the VHDL files still included correctly? > > And what if I change the directory name of a submodule ? Does > Quartus update the "links" by itself or do I have to change the links > manually? > > Thank you for your help. > > Kind regards Hi, After you open the moved project in the new directory, first thing is to change the 'User libraries' found in the settings menu. Most of the times this is the only thing I need to do. In the case though, you decide to change also the name or place of a subfolder then in the Add/remove files setting you have to remove and add again from the new folders the files affected. Hope I explained it clear enough for you to understand, if not let me know. Christos Zamantzas at cern dot ch.Article: 71530
Andrew Rogers <andrew@_no_spam_rogerstech.co.uk> wrote: : Uwe Bonnes wrote: : > Phil Tomson <ptkwt@aracnet.com> wrote: : > ,,, : > : That still won't help when it comes to programming devices. The Jungo : > : parallel port driver doesn't work under Wine. : > : > I had some success with http://www.nahitech.com/jtag-en/ running with wine. : > Nahitafu will hopefully enable programming of more devices.. : > : > Bye : How about GtkJTAG from the same author? That runs on Linux, I have : downloaded and compiled it. The downside is that in needs to run as root As I understand Nahitafu, the Gtk Version is abandoned. Chip manufactures only prelease the needed programming information, if Nahitafu doesn't open up the code. The windows version running on wine doesn't need root access, if the ppdev/parport device is accessible to the user and ppdev configured right in wine. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 71531
Ed wrote: > Hi, > > Does anyone have any experience in programming Altera FPGA's? In particular > a FLEX8000. What development environment do you use and how much does it > cost? Do any free development environments exist for it (VHDL or Verilog)? > Also, is the programming hardware expensive? The flex series is outdated, choose another one. There is an application note on how to build a Byteblaster parallelport adapter. Basically a '244 plus a set of resistors and capacitors. There are also alternative sources in case you don't have the time to build one. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 71532
Hello! Sorry for the previous question. My card is done... and I have no external pull-up!! (I was confused by the information in a older version of the xc9500 datasheet):( . My question now is: => Can the device get hot because of a floating input (the output that drives the CPLD sometimes is in tri-state)? Can I solve this problem only in software using something like a bidirectional pin driving the pin internally with Logic "0" or Logic "1" (only when the output from the other IC is in tri-state)? Thanks Again Best Regards BrunoArticle: 71533
[good list of battery powered toys snipped] I think we are on the corner of reasonable life for many of todays toys. My digital camera with a second battery just lasts a week and is just light enough that I'm willing to carry it backpacking. Film is free. I take a lot of pictures. With a newer camera, I'd take the same number of pictures but they would have more pixels. >All of the above devices use uPs, ASICs or ASSPs because a FPGA is not >cost effective at all in these tasks (volume too large). >Reprogrammability doesn't add any value to any of the products. All of >these products use much older technology CMOS processes tweaked for low >power (high Vt's). >So, what market even exists that needs reprogramability (as in FPGAs), >AND also needs extremely low power? I should go read your marketing blurbs for a refresher. :) How many reasons aside from field reprogramability are there for using FPGAs? How about time to market? Avoiding NRE for low and medium volumes? Riding the bleeding edge of the technology curve probably doesn't apply if all low power chips are done with old process lines. How old are they? What's the ballpark NRE for a design as compared to a modern process? Is there much effort (investment) in tweaking lines for low power? >It isn't that I do not believe that there are no low power applications >out there, it is that I need to be told which ones they are if I am to >help provide products for them. Is there a chicken-egg problem here? Of course nobody will use FPGAs in power critical applications if they all use a lot of power. Are you still selling any 3000 or 4000 parts because they have very low idle current? How is CoolRunner doing? If somebody put out a press release announcing a family of FPGAs emphasizing low power, I don't think I would be too surprised. I'm probably not smart enough to write it (or even an outline), but I'll bet I would recognize and go "yup" on most of the technical points. (Half would be the same old reasons for using FPGAs.) I hang out with the ARM crowd. Lots of them in cameras and cell phones. Seems to fit well with low power applications. Ballpark is 1 mA per MIPS. How is PowerPC for low power? Microblaze? I could easily picture FPGAs being used next to existing uPs, either to fill out the IO options that aren't available in the normal menu or to add special IO devices. -------- I had an interesting change of focus about a year ago. I shifted from working on a board with 3 CPUs each needing 15 amps to a battery powered board where idle current is critical. 45 amps to 45 uA. That's a factor of a million, not that it's the same problem domain as the "million" that started this discussion. It was strange the first time I came out of the lab smiling because I had tracked down where 6 uA was going. I used to look at data sheets and start with the nSec and MHz, then work out whatever it took to power the chips and keep them cool. Now I start looking at the leakage currents. Fingers are used to find floating inputs rather than check temperature.Article: 71534
Hi, An other technique can be use in ASIC design too. Because ASIC have commonly multi-clock domains, some of them can be powered down when not required. Clock gating logic are used to do it, and you have an enable input for this logic; you can design this input to be active only after reset and clocks input stability. That give you a similar behavior than the FPGA proposal. JaI Jim Lewis wrote: > Hal, > >> What do ASIC/CPU designers do? My guess is that they don't >> have a global-reset so their version of this problem is a bit >> different. > > In ASIC design, we would connect the asynchronous reset to the > circuit Ken showed (or one like it). Reset for each clock > domain is separately synchronized. Reset would need to settle > in a clock period. Routing generally allows this. If not, > you work it out (build a fanout tree with buffers or > registers). Going back some time, on my first ASIC we had > to manually balance the clock tree. > > See my post. GSR would be generally alot more useful if > we could quantify in general that it settles in X to Y > amount of time and then apply its output to a circuit like > the one Ken shows to stabilize all logic or all control > logic. From the difference between Y and X we could calculate > how many states we needed to delay "critical" reset so that > it occurs last. Four registers is kind of ad-hoc and means > something much different for different clocks (20 MHZ vs > 200MHZ). > > Of course, going a step further, since synthesis tools can > and do recognize statemachines, and they know the clock > frequency of a particular clock, they could automatically > do the right thing for Xilinx (insert Ken's circuit). > However I like being in control of these type of things > and I am not sure I would like this solution. > > > Cheers, > JimArticle: 71535
Austin Lesea <austin@xilinx.com> wrote in message news:<cd66h7$47j1@cliff.xsj.xilinx.com>... > Peter's comment is perfectly accurate: series terminations dissipate > virtually no power That is exactly what he said, but it is not accurate. >in the series termination resistors. That he did not say. Its an addition of yourself that changes the meaning of the statement quite significantly. Please reread the post. Peter omitted 60mA per Bank. A mistake that can happen. What I do not understand why you catagorize this as "acurate". In an idle small Spartan-3 this more than doubles the power consumption. Kolja SulimmaArticle: 71536
Uwe Bonnes wrote: > Andrew Rogers <andrew@_no_spam_rogerstech.co.uk> wrote: > : Uwe Bonnes wrote: > : > Phil Tomson <ptkwt@aracnet.com> wrote: > : > ,,, > : > : That still won't help when it comes to programming devices. The Jungo > : > : parallel port driver doesn't work under Wine. > : > > : > I had some success with http://www.nahitech.com/jtag-en/ running with wine. > : > Nahitafu will hopefully enable programming of more devices.. > : > > : > Bye > > : How about GtkJTAG from the same author? That runs on Linux, I have > : downloaded and compiled it. The downside is that in needs to run as root > > As I understand Nahitafu, the Gtk Version is abandoned. Chip manufactures > only prelease the needed programming information, if Nahitafu doesn't open > up the code. > > The windows version running on wine doesn't need root access, if the > ppdev/parport device is accessible to the user and ppdev configured right in > wine. > > Bye I now have GtkJTAG working without being root. I am using the parport driver. I think you're right about GtkJTAG being abandoned by Nahitafu, good job I have the source code under GPL license:). I will release my version as soon as I can verify it works when my Spartan3 kit arrives. GtkJTAG understands Xilinx BSDL files so there shouldn't be a problem. The secrets seem to be in the bitstream encoding, how bitgen works? I had started to work on my own bitgen a while ago. I made some progress by taking a very simple design. If I remember correctly I did an auto-correlation on the bitstream. One of the interesting things I found was that the bitstream flipped half way through. If there is anyone interested in writing their own bitgen contact me and I will find my previous work. Regards AndrewArticle: 71537
Andrew Rogers <andrew@_no_spam_rogerstech.co.uk> wrote: : I now have GtkJTAG working without being root. I am using the parport : driver. I think you're right about GtkJTAG being abandoned by Nahitafu, : good job I have the source code under GPL license:). : I will release my version as soon as I can verify it works when my : Spartan3 kit arrives. Sound's interesting. : GtkJTAG understands Xilinx BSDL files so there shouldn't be a problem. : The secrets seem to be in the bitstream encoding, how bitgen works? I : had started to work on my own bitgen a while ago. I made some progress : by taking a very simple design. If I remember correctly I did an : auto-correlation on the bitstream. One of the interesting things I found : was that the bitstream flipped half way through. If there is anyone : interested in writing their own bitgen contact me and I will find my : previous work. Sounds even more interesing... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 71538
> It looks to me like the command line tools are still either developed on > Unix, or on Windows/Unix pretty much simultaneously. Only the gui has > become a Windows thingy. I mainly think this because it is clear that > the command line tool interface really has not changed much since "the > old days", and they remain separate from the gui even now. The gui > remains just a button clicking front end to those tools. I have not used > Solaris in awhile, so I have no idea how that GUI performs these days. I believe that your right. The real tools like map and par, and now xst, were always developed on Unix and ported to Windows. Those tools are straight POSIX C or C++ so they will run on anything with just a recompile. They always ran under WINE without a hitch and the Linux native versions run on any flavor of Linux. The GUI tools are another story. They are written for Windows and ported to Linux using a terrible tool that has all sorts of library dependencies and awful performance. Both the Cadence and Mentor tools will run on any flavor of Linux, I'm using them with both Mandrake 9.2 and 10.0, so it clearly possible to write a GUI that doesn't have any dependentcies on a particular distribution. Also I run Cadance and Mentor tools over a network without any performance issues, both Simvision and ModelSim are true X applications that work flawlessly when split between a client on one machine and an X server on another. The Xilinx GUI tools have very real distribution dependentcies which shows that the people responsible for porting them don't have a good understanding of the Linux world. Also they are unusable over a network which is their Windows heritage rearing it's ugly head. The GUIs will not run on Mandrake 10.0 although they do run fine on Mandrake 9.2. Impact, which requires a kernel patch for some reason, only works on Redhat 8.0. They provide the kernel patch but it's specific to the kernel used in RH8, I think it's 2.4.17, which is hopelessly obsolete. They haven't bothered to provide the patch for modern kernels. I've upgraded my servers to Mandrake 10.0 (2.6 kernel) because I do everything from scripts so I don't care if the GUI tools work. I'm keeping my workstation at Mandrake 9.2 so that I can use FPGA Editor if I need to.Article: 71539
Have you tried the LPM_DECODE function? From the Quartus menu ,o to Tools->Megawizard PlugIn Manager->Gates->LPM_DECODE and then follow the regular steps to stamp out an instance of thedecoder. Hope this helps. - Subroto Datta Altera Corp. "vadim" <vbishtei@hotmail.com> wrote in message news:2a613f5d.0407200852.5a45566c@posting.google.com... > There is a nice parametarizable MUX but how about a DEMUX ??? > > I have already implemented my own 1-bit 4-input DEMUX, but for the > 8-bit 4-input version thought Altera would provide something... > > Thanks in advance, > VadimArticle: 71540
Ernie, We use a couple of Rocky Mountain Logic Ant16 USB logic analyzers. Works very well and fits in your pocket! http://www.rockylogic.com/products/ant16.html I've only used one at a time and have never had more than 12-13 channels going at once, but suits our purposes on our under 100MHz fpga boards. Love working on my board on my laptop with Byteblaster, serial port, and Ant16 a blazin'. Cheers, Ken "ernie" <ernielin@gmail.com> wrote in message news:d7fe9825.0407191638.58b29e0c@posting.google.com... > Hi, > > Can anyone recommend any good (and cheap) 32-channel analyzers? By > cheap I mean less than or approximately $1000. It would be nice if > the software supported complex triggering and the analyzer had > decently fast sampling rates. Sample depth is not really a critical > issue but more is obviously better. > > Thank you!Article: 71541
Drew wrote: > > Hi all, > > I need Open Collector Active-Low analog circuit's logical > representation. I am having pretty hard time putting it togather. I > used bidirectional tristated bus, but it doesnt solve my problem. > There are some contentions as I have to read what I write to the Bidir > Pin (always) and at some point the Bidir Pin works as an output too. You didn't say what you are modeling in. Assuming you are using VHDL or Verilog, a tri-state bus is modeled using STD_LOGIC. A tri-state open collector driver will drive either a '0' or an 'X'. Any of these drivers can overdrive the 'X' of another when they drive a '0' which is a "strong" drive. If you want to model a pullup resistor, drive the net with a constant 'H' from another source. This is a "weak" high and will overdrive the 'X', but be overdriven by the '0'. In most logic functions, the 'H' will be treated the same as a '1'. Or you may have to convert to '0', '1' before using this bus as an input. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 71542
ibis@tiscalinet.de (E. Backhus) wrote in message news:<e5e7ca2e.0407200343.4837f037@posting.google.com>... > johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0407190711.45a7a53a@posting.google.com>... > > ibis@tiscalinet.de (E. Backhus) wrote in message news:<e5e7ca2e.0407182337.570d1070@posting.google.com>... > > > johnjakson@yahoo.com (john jakson) wrote in message > > > > > > > My family is all too aware of AthlonXP heat output, looking to kill it > > one day with a Transputer or 2, but 1 should suffice. After all it > > only surfs & plays net TV. > > I just didn't dare to mention Transputers :-) > > > > > > > > > I wonder, besides any asynchronous stuff, if the same space could hold > > > a bunch of (slow) low power SoC microcomputers, working together as > > > known from grid computers. > > > > Yes, thats what I am working on, Inmos did this 20yrs ago, probably > > 20yrs too early. I keep doing the same engineering calculation, Intel > > ups the freq of x86 by 30x and gets 30x perf over the p100. BUT > > transister count also went up (big no) and heat,noise,space too. That > > used to be called bad engineering. Notice that bridge builders today > > build lighter bridges today than IKB did many yrs ago. > > > > The intel supporters will pooh pooh that analysis but if you have > > distributed cpus & local memory and know how to use them (Transputer > > people do), you also get far more total memory b/w than pushing it all > > up 1 pipe. Also no reason to be limited to std DRAM, theres RLDRAM > > available with 20n RAS times. And with MTA architecture, branching & > > memory delays are better hidden than single threaded cpus with ever > > bigger caches. > > There are lots of pro's and con's about transputer technology, but > what really broke their neck was the high price of the CPU alone > compared to a whole PC with (then) cheap Network cards. The parallel > processing people started grid computing and the controller people > were just happy with their (then) fast controllers(ARM etc.) > > Today there is a possibility for the return of integrated parallel > processing architectures. The IEEE1355 and Spacewire Interfaces > (successors of the Transputer links) are available as FPGA-cores, and > combined with a CPU-core and other fancy stuff (e.g. hardware > scheduler) we get powerful Transputer-Substitutes on cool and cheap(?) > FPGA-Silicon. > > > > regards > Eilert Backhus Exactly, but today it is even more prudent to consider the plusses of FPGA design and work around the minusses to build a new Transputer or any cpu for that matter. Once you have x MHz in FPGA you get maybe 2-5X more in ASIC. I've been keeping an eye on .13 cell libs, and the critical path in both is ultimately how fast a dual port BlockRam can cycle for about 512x32. In Samsung its near 1GHz. One very nice advantage of MTA is that it allows for even that bottleneck to be pipelined although all the cells I've seen are single cycle 1.0ns designs. A fully pipelined DP SRAM could probably go 2x faster still. The cost isn't as low as I'd originally hoped, maybe in the 1k to 1.5K flops ballpark but FPGA does allow interesting architecture to be tried out for <<10th of the original Tp and probably 10-50x perf so thats not a bad combination. Anyway the IP will be fully portable. The SpaceWire,1355 certainly helps but I haven't decided yet on link layer HW issues. regards johnjakson_usa_comArticle: 71543
General Schvantzkoph wrote: > ... Impact, > which requires a kernel patch for some reason, only works on Redhat 8.0. > They provide the kernel patch but it's specific to the kernel used in RH8, > I think it's 2.4.17, which is hopelessly obsolete. They haven't bothered > to provide the patch for modern kernels. > I recompiled the kernel patch on RH9 (kernal 2.4.20). Impact is working fine for me. -- My real email is akamail.com@dclark (or something like that).Article: 71544
Pine wrote: > I'm using ise webpack 6.2.03i through wine on redhat 9. > > ... > Or does I miss any file in linux? I just copied the whole folder of > ise6 to my linux machine. > You really need to run the Webpack installer under Wine. -- My real email is akamail.com@dclark (or something like that).Article: 71545
Yes, I made a mistake, and I admit it. I left out the 60 mA of current in the controller, because I did not know that. It shook me up. Honest mistake, I apologize. Peter Alfke > From: news@sulimma.de (Kolja Sulimma) > Organization: http://groups.google.com > Newsgroups: comp.arch.fpga > Date: 21 Jul 2004 05:09:59 -0700 > Subject: Re: Spartan 3 termination question (DCI) > > Austin Lesea <austin@xilinx.com> wrote in message > news:<cd66h7$47j1@cliff.xsj.xilinx.com>... > >> Peter's comment is perfectly accurate: series terminations dissipate >> virtually no power > That is exactly what he said, but it is not accurate. > >> in the series termination resistors. > That he did not say. Its an addition of yourself that changes the > meaning of the statement quite significantly. > > Please reread the post. > > Peter omitted 60mA per Bank. A mistake that can happen. What I do not > understand why you catagorize this as "acurate". > In an idle small Spartan-3 this more than doubles the power > consumption. > > Kolja SulimmaArticle: 71546
"Ed" <Ed@nospam.com> wrote in message news:cdm3g3$809$1@news5.svr.pol.co.uk... > Hi, > > Does anyone know of any cheap FPGA's? By cheap I mean £5 or less. Also, do > you know any suppliers in the UK? I don't think you will find any current FPGAs that cheap unless you buy lots of them. I bought some Altera Cyclone EP1C3T100C8 chips for prototyping recently from Arrow UK for 8.13 GBP each (plus carriage and VAT). I've often seen older devices for sale cheaply on eBay. LeonArticle: 71547
Ed wrote: > Hi, > > Does anyone know of any cheap FPGA's? By cheap I mean £5 or less. Also, do > you know any suppliers in the UK? > > Thanks, > > Look on www.rswww.com. This link http://rswww.com/cgi-bin/bv/browse/Module.jsp?BV_SessionID=@@@@0353366949.1090426930@@@@&BV_EngineID=ccchadcmdgfghjkcfngcfkmdgkldfhl.0&cacheID=uknetscape&3267879749=3267879749&catoid=-95599411 might not work because of their session thing, but there are some (older) FPGA's on there for < £5. SimonArticle: 71548
Something like a Xilinx Spartan IIE XC2S50 is £22-35 from RS, £6-83 from Digikey !! The Digikey price includes duty, but not shipping (£12) or a 'handling charge' (£10 if order total < £75). Neither price includes VAT. If you wanted something a bit bigger, an XC2S200 is £42-31 (RS) or £14-11 (Digikey) ! I have had excellent service from DigiKey (and, to be fair, from RS most of the time ...) Dave "Ed" <Ed@nospam.com> wrote in message news:cdm3g3$809$1@news5.svr.pol.co.uk... > Hi, > > Does anyone know of any cheap FPGA's? By cheap I mean £5 or less. Also, do > you know any suppliers in the UK? > > Thanks, > >Article: 71549
In comp.arch.fpga Hal Murray <hmurray@suespammers.org> wrote: > > What do ASIC/CPU designers do? My guess is that they don't > have a global-reset so their version of this problem is a bit > different. a cpu "just" needs: * known good value in the pc * address translation and caches disabled thats a very small amount of state that needs to be right. the rest can be initiated to a known good state by software. -- Sander +++ Out of cheese error +++
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