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Hello
I am trying to implement a PCI design in a Spartan3 device. Everything
went quite well until I decided to use a DCM to remove the last timing
problems I got.
Since I put the DCM in my design, ISE refuses to P&R.
Here is what I got in the P&R report file:
WARNING:Ncd:218 - The component "pci_clk_in" specified in the .PCF file
was not
found in the design. Please verify that:
1. the specified component actually exists in the original design,
2. the trimming report in the .MRP file does not report it as having
been
trimmed, and also
3. the specified component record in the .PCF file is spelled correctly.
WARNING:Ncd:216 - Ignoring constraint <COMP "pci_clk_in" LOCATE = SITE "D9"
LEVEL 1; > because comp, pci_clk_in, not found
and so on...
It looks like my clock was removed somewhere.
I entered the constraints using the constraints editor so I'm sure I
din't misspell the signal names...
I'm lost.
Any help welcome.
--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/
Article: 72376Sean Durkin <smd@despammed.com> wrote: > > The footnote probably only says that the ICAP is 'specified' to 33 MHz, > > or something like this, right? > Yes... but at frequencies higher than about 38MHz (that's what I tested > in my particular case) it gives you invalid data, so 33MHz seems to be a > reasonable, if somewhat conservative limit. Hmm, you don't tell at which clock edge you are sampling your data, and also even with the SelectMAP you have to watch busy when doing any kind of readback (I assume that's what you mean with 'invalid data'), so I guess it would be normal to have problems when not doing so. > It's not about speed, it's about keeping it simple. If I have a bus > clock of 50MHz, and ICAP supposedly works up to 66MHz like SelectMAP, > why should I even bother with watching the BUSY-signal? The thought > never even crossed my mind until I ended up with strange data when > reading back and with not-working designs after reconfiguration... ICAP See the SelectMAP documentation about all of the meanings of BUSY during readback. I guess that would be the prime reason to bother with it, regardless of the clock. Btw. I've been using 100 MHz almost all of the time, as long as no external cables were involved, and it does work fine, at least on the 2vp7. > BRAMs are a problem, too, especially when they contain the program you > run on your PPC. When you read back BRAM contents, the instruction > fetches can get corrupted, causing your program to hang or behave > abnormally, like exiting loops after a more or less random number of > cycles and such. That gave me some headaches as well... Are you sure it's instruction fetches that get corrupted? Because about the SRLs/LUTs the standing explanation is that readback and write access collide, not readback and read access - so I wonder if it really was the readback + read-instr.fetch combination that caused the problems, or whether it may have been write accesses (reentry points for function calls, loop counters or whatever) getting corrupted. regards, -gArticle: 72377
7 <website_has_email@www.ecu.pwp.blueyonder.co.uk> wrote in message news:<SylUc.150065$28.99977@fe1.news.blueyonder.co.uk>... > I have a new cache. > Researched it as best as possible and it appears to be new. > Anyone interested? Sure. Tell us all about it. Cheers, JonBArticle: 72378
"Tyrone Kwok" <tokwok@eee.hku.hk> writes: > Hi Michael, > > I've just sent the manual of the SDRAM chip on the AFX V2P board to your > email mwd24@thompson.cl.cam.ac.uk > Hope that you can receive it (it's about 1.7M : ) > > Cheers, > Tyrone Many thanks Tyrone. I've checked all the parameters I was giving the SDRAM core to the document, and still I'm not having any luck. Below is the parameters I use, taken from the system.mhs file in EDK: # Confirmed that we have a -8 grade part (engineering sample) (ZVCGC) BEGIN opb_sdram PARAMETER INSTANCE = SDRAM_8Mx32 PARAMETER HW_VER = 1.00.d PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0 PARAMETER C_SDRAM_TCCD = 1 # confirmed (cas - 1 for read, any clock for write) PARAMETER C_SDRAM_TRAS = 48000 # confirmed (48 for -8, 50 for -10) PARAMETER C_SDRAM_TRC = 80000 # confrimed (80 for -8, 100 for -10) PARAMETER C_SDRAM_TRFC = 80000 # confirmed (80 for -8, 100 for -10) PARAMETER C_SDRAM_TRCD = 20000 # confirmed PARAMETER C_SDRAM_TRRD = 20000 # confirmed PARAMETER C_SDRAM_TRP = 20000 # confirmed PARAMETER C_SDRAM_TREF = 64 # confirmed (4096 refreshes every 64 ms) PARAMETER C_SDRAM_REFRESH_NUMROWS = 4096 # confirmed PARAMETER C_SDRAM_CAS_LAT = 2 # confirmed (2 for -8, 3 for -10) PARAMETER C_SDRAM_COL_AWIDTH = 8 # confirmed PARAMETER C_SDRAM_BANK_AWIDTH = 2 # confirmed PARAMETER C_SDRAM_AWIDTH = 11 # confirmed PARAMETER C_SDRAM_DWIDTH = 32 # confirmed PARAMETER C_SDRAM_TWR = 15000 # confirmed PARAMETER C_SDRAM_TMRD = 2 # confirmed PARAMETER C_OPB_CLK_PERIOD_PS = 10000 # confirmed PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x007fffff BUS_INTERFACE SOPB = opb PORT OPB_Clk = sys_clk_s PORT SDRAM_CLK_in = sys_clk_s PORT SDRAM_WEn = SDRAM_8Mx32_SDRAM_WEn PORT SDRAM_CKE = SDRAM_8Mx32_SDRAM_CKE PORT SDRAM_CASn = SDRAM_8Mx32_SDRAM_CASn PORT SDRAM_RASn = SDRAM_8Mx32_SDRAM_RASn PORT SDRAM_Addr = SDRAM_8Mx32_SDRAM_Addr PORT SDRAM_DQ = SDRAM_8Mx32_SDRAM_DQ PORT SDRAM_DQM = SDRAM_8Mx32_SDRAM_DQM PORT SDRAM_BankAddr = SDRAM_8Mx32_SDRAM_BankAddr END Does this match what you've got set for the SDRAM? Cheers, -- Michael Dales University of Cambridge Computer Laboratory http://www.cl.cam.ac.uk/~mwd24/Article: 72379
I would like to embed a device that has a PCI inteface with an FPGA (preferably a SPARTAN 3). Two questions have arisen before I start 1) Many PCI based chips (including the one I want to use) can be purchased as a PCI card to speed up development. I have had a good google without success but does anyone know of an FPGA development platform that includes a PCI card site, I could then develop the firmware without designing a PCB. 2) I have no PCI experience but there seems to be a lot of talk about meeting the irdy/trdy timings. Is it a lot easier in my scenario because if I am not the master then I know that I am being addressed (ie. I don't need a big address decoder) and if I am the master I just need to write single words to the device so I can live with a big performance hit. Thanks in advance ColinArticle: 72380
All, Conscious of the original intent of DCI: We're looking to drive a number (read 76) LEDs using a XC3S50. VCCO is 3.3V. IO Standard will be LVDCI_33. We're also aware that DCI is not available on Bank 5. We've got plenty of spare IO so we've decided to drive things statically (as opposed to scanning). Is it possible to use DCI to simulate current limiting resistors (~430ohm) for each of the 76 LEDs? If so, it can save us a significant amount of board space on an already tight board. Any comments / personal experiences appreciated. Gordon LauArticle: 72381
colin wrote: > I would like to embed a device that has a PCI inteface with an FPGA > (preferably a SPARTAN 3). > > Two questions have arisen before I start > > 1) Many PCI based chips (including the one I want to use) can be > purchased as a PCI card to speed up development. I have had a good > google without success but does anyone know of an FPGA development > platform that includes a PCI card site, I could then develop the > firmware without designing a PCB. By PCI site, you mean a slot where you can put PCI cards or a PCI edge so that you can use it your FPGA board as a PCI device. Look at the avnet spartan 3 kit. I have it and it's real nice ;) > 2) I have no PCI experience but there seems to be a lot of talk about > meeting the irdy/trdy timings. Is it a lot easier in my scenario > because if I am not the master then I know that I am being addressed > (ie. I don't need a big address decoder) and if I am the master I just > need to write single words to the device so I can live with a big > performance hit. If you want to implement a PCI device that is not a PCI master then that should not be too hard. Implementing a PCI host bridge however is really more complex ... Look at opencore there is one IIRC. SylvainArticle: 72382
Thanks for the article, Narasimha. Still need information about (or if possible) to set the default IO standard, getting rid of an old group, and it just occured to me that I am assuming that the 33 after LVCMOS refers to the Vcco but I never confirmed that. Might it be something else like the Voh? Brad > > "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10i1rel5f76hm67@corp.supernews.com>... > > Can anyone point me to a tutorial or explanation of the IO standards? And > > how to set the default? Seems as if the synthesis tool has assigned LVCMOS25 > > as the default setting although I don't recall setting this standard. As my > > IOs for my design are entirely 3.3V, shouldn't my default be LVCMOS33? > > > > Additionally in the PACE windows under Design Object List there is a section > > with Groups listed. Not sure what this is for, however, I have a group > > listed with no ( # 0) items in the group for a symbol I recall that I > > deleted from the VHDL code a long time ago. How do I get rid of this old > > group? > > > > Thanks, > > > > BradArticle: 72383
Hi, The SDRAM chip on my board is DVCGC, which is also a -8 grade part. BTW, I find one discrepancy with your parameters: > PARAMETER C_SDRAM_TWR = 15000 # confirmed My value for this is 17000, 1tCK + 7 ns. Please refer to P.33 of the manual. BTW, I've just written a simple program which writes to and then reads from a single address, and it reads correctly. Cheers, Tyrone "Michael Dales" <mwd24@thompson.cl.cam.ac.uk> ???????:yqmfz6lyc8u.fsf@thompson.cl.cam.ac.uk... > "Tyrone Kwok" <tokwok@eee.hku.hk> writes: > > > Hi Michael, > > > > I've just sent the manual of the SDRAM chip on the AFX V2P board to your > > email mwd24@thompson.cl.cam.ac.uk > > Hope that you can receive it (it's about 1.7M : ) > > > > Cheers, > > Tyrone > > Many thanks Tyrone. > > I've checked all the parameters I was giving the SDRAM core to the > document, and still I'm not having any luck. Below is the parameters I > use, taken from the system.mhs file in EDK: > > # Confirmed that we have a -8 grade part (engineering sample) (ZVCGC) > BEGIN opb_sdram > PARAMETER INSTANCE = SDRAM_8Mx32 > PARAMETER HW_VER = 1.00.d > PARAMETER C_INCLUDE_HIGHSPEED_PIPE = 0 > PARAMETER C_SDRAM_TCCD = 1 # confirmed (cas - 1 for read, any clock for write) > PARAMETER C_SDRAM_TRAS = 48000 # confirmed (48 for -8, 50 for -10) > PARAMETER C_SDRAM_TRC = 80000 # confrimed (80 for -8, 100 for -10) > PARAMETER C_SDRAM_TRFC = 80000 # confirmed (80 for -8, 100 for -10) > PARAMETER C_SDRAM_TRCD = 20000 # confirmed > PARAMETER C_SDRAM_TRRD = 20000 # confirmed > PARAMETER C_SDRAM_TRP = 20000 # confirmed > PARAMETER C_SDRAM_TREF = 64 # confirmed (4096 refreshes every 64 ms) > PARAMETER C_SDRAM_REFRESH_NUMROWS = 4096 # confirmed > PARAMETER C_SDRAM_CAS_LAT = 2 # confirmed (2 for -8, 3 for -10) > PARAMETER C_SDRAM_COL_AWIDTH = 8 # confirmed > PARAMETER C_SDRAM_BANK_AWIDTH = 2 # confirmed > PARAMETER C_SDRAM_AWIDTH = 11 # confirmed > PARAMETER C_SDRAM_DWIDTH = 32 # confirmed > PARAMETER C_SDRAM_TWR = 15000 # confirmed > PARAMETER C_SDRAM_TMRD = 2 # confirmed > PARAMETER C_OPB_CLK_PERIOD_PS = 10000 # confirmed > PARAMETER C_BASEADDR = 0x00000000 > PARAMETER C_HIGHADDR = 0x007fffff > BUS_INTERFACE SOPB = opb > PORT OPB_Clk = sys_clk_s > PORT SDRAM_CLK_in = sys_clk_s > PORT SDRAM_WEn = SDRAM_8Mx32_SDRAM_WEn > PORT SDRAM_CKE = SDRAM_8Mx32_SDRAM_CKE > PORT SDRAM_CASn = SDRAM_8Mx32_SDRAM_CASn > PORT SDRAM_RASn = SDRAM_8Mx32_SDRAM_RASn > PORT SDRAM_Addr = SDRAM_8Mx32_SDRAM_Addr > PORT SDRAM_DQ = SDRAM_8Mx32_SDRAM_DQ > PORT SDRAM_DQM = SDRAM_8Mx32_SDRAM_DQM > PORT SDRAM_BankAddr = SDRAM_8Mx32_SDRAM_BankAddr > END > > Does this match what you've got set for the SDRAM? > > Cheers, > > -- > Michael Dales > University of Cambridge Computer Laboratory > http://www.cl.cam.ac.uk/~mwd24/Article: 72384
Hi Jeremie,
For the benefit of anyone else who might be following this thread, the files
I sent you are now also available on the Xilinx support page. The to the record
with the patch is
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=18554
It was also good to hear that you were able to generate 4-lane modules from
Coregen after your webcase was resolved :)
Best Regards,
Nigel
Jeremie wrote:
> Hi Nigel,
>
> Thanks for the quick answer.
> I have a webcase opened to try to get the latest vhdl design out of Coregen
> and if I can get them no need for me to fix this old design. So far with
> Coregen I could only generate and test the code for single lane design.
> In the meantime I thought I should fix the old 4 lane design to prove the
> 4-lanes solution. So far it works with almost random data and I guess this
> patch is all I'm missing.
> I don't want to waste your time doing the conversion. A verilog patch will
> be fine. If it is an easy fix I'll convert it to the vhdl if not I'll wait
> for the webcase to help me to get the latest design.
> If you have the file I'll be glad if you can forward it to me.
> I'll send you an e-mail so that you get my address.
>
> Thanks and Best Regards,
>
> Jeremie.
>
> "Nigel Gulstone" <nigel.gulstone@xilinx.com> wrote in message
> news:411CF536.DD67C00D@xilinx.com...
> > Hi Jeremie,
> >
> > I'm sorry to say that the zip file you are looking for only contains
> a
> > Verilog version of the patch. It was originally produced by special
> request
> > for a customer who could not upgrade to one of our newer designs: they had
> > made custom changes to the old module.
> >
> > In general we recommend an upgrade to one of the modules from the
> > Xilinx Core Generator tool - these are the smallest Aurora designs we
> offer,
> > and have the same interface as the old designs. I would be happy to create
> a
> > VHDL version of the patch for you. If you contact me directly or pass the
> > message along via your FAE or hotline, I'll do my best to help you out.
> >
> > In hindsight, we should have provided both languages in the zip file.
> > We're working to fix the broken link on the server - when its up and
> running
> > again, we'll add the VHDL version of the patch to the zip file.
> >
> > Cheers,
> > Nigel
> >
> >
> > Jeremie Veyret wrote:
> >
> > > Hi,
> > >
> > > I'm using Xilinx 804 aurora vhdl design and I saw that on their web-site
> > > that there was a patch for it (Record Number: 18554) but the file is not
> > > available on their server anymore.
> > > I asked them and they seem to have problem finding it back.
> > > If any of you sees what I mean and has downloaded the patch called
> > > aurora_804_sp_patch.zip
> > > Could you let me know and I'll contact you directly (I'm not too fond of
> > > spam).
> > >
> > > Best regards,
> > >
> > > Jeremie.
> >
Article: 72385Hello, Someone has pointed out to me that the implementation in the Virtex2PRO will only go through the alignment once, i.e. ignoring any subsequent ALIGN characters in the data stream. The spec is a little ambiguous and I am unsure if this does actually happen. Quote: "if a comma is detected and the data is aligned, no further alteration takes place" which sounds like what i was told, but it then goes on to say: "The transceiver continuously monitors the data for the presence of the 10-bit chars. Upon each occurrence of the 10-bit char, the data is checked for word alignment" Does anyone have any practical experience of the alignment (comma detection enabled)? If so once the data is aligned are all subsequent align chars in the stream ignored? or does the det/Align re-align the data every time? Lee --Article: 72386
Ok, I finally got ST2 going and it's great! But everytime a add or change a signal to look at it does a full rebuild (~20min.) The docs seem to indicate that simply adding a node shouldn't take so long, but I can't figure out how to affect it. Smart compile and all the options listed in the docs are turned on, but I don't see any benefit. Even if I just press the build > twice in a row without editting *anything* it still does a full build. What's the secret? :) Thanks, KenArticle: 72387
On Tue, 17 Aug 2004 18:38:37 +0100, Lee <no.way@spam.com> wrote: >Hello, > >Someone has pointed out to me that the implementation in >the Virtex2PRO will only go through the alignment once, i.e. >ignoring any subsequent ALIGN characters in the data stream. > >The spec is a little ambiguous and I am unsure if this does actually >happen. >Quote: >"if a comma is detected and the data is aligned, no further >alteration takes place" >which sounds like what i was told, but it then goes on to say: > >"The transceiver continuously monitors the data for the presence >of the 10-bit chars. Upon each occurrence of the 10-bit char, the data is >checked for >word alignment" > >Does anyone have any practical experience of the alignment (comma detection >enabled)? If so once the data is aligned are all subsequent align chars >in the stream ignored? or does the det/Align re-align the data every time? > > >Lee in any communication system bit errors are always a certainty albeit with very low probability. the receiver should check the data it sees constantly and try to do bit lock and symbol lock when there are too many errors which are detected by align symbols not aligning properly or too many decode errors etc.Article: 72388
byseid@yahoo.com wrote in message news:<783d4d57.0408100407.68f1d8f6@posting.google.com>... > I am not new for logic design but I need help for designing a > sequential Logic circuit analysis and design. > I want to design a traffic light controller for crossroad(of four > direction) the controller at each direction say A,B,C,D detects the > number of cars on each then the line having more cars will get the > priority... for more details please mail me <byseid@yahoo.com>. Then this is an 100 years old problem. What's wrong with you?Article: 72389
vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0408092009.27cbc9eb@posting.google.com>...
> pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0408061906.79dd84ab@posting.google.com>...
> > pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0407312040.783610f9@posting.google.com>...
> > > mikeandmax@aol.com (Mikeandmax) wrote in message news:<20040730131548.23098.00002650@mb-m07.aol.com>...
> > > > >
> > > > > I've discovered that there is some significant propagation delay
> > > > >between the input and bidirectional pin & bidirectional pin to output
> > > > >pin in my simulation. I've compared the function LPM_BUSTRI within
> > > > >Quartus, a construction made up from Tri-state buffers within Quartus
> > > >
> > > > often prop delays in a tristate pin are due to OE performance - have you looked
> > > > at the OE timinng numbers, or are you indeed looking at the prop delay of the
> > > > in or out buffer. Most modern FPGAs now have syncronous OE and data registers
> > > > at the pin, which can give you much better timing through the I/O.
> > > >
> > > > Mike Thomas
> > > > Lattice fae
> > >
> > > Thanks for the update on where to start looking. After reading
> > > further the specificatios in the delays within the Stratix IOE
> > > structure, I've managed to compute the internal timing and external
> > > timing for a given drive strength at the output for a bidirectional
> > > pin:
> > >
> > > Internal Timing:
> > > =================
> > > total prop. delay = ip/op register clock-to-output delay + IOE data
> > > input to combinatorial output + setup time + hold time + routing delay
> > >
> > > In equation form I have this as:
> > >
> > > tpd1 = tco_c + tpcombin2pin_c + tsu + th + tlocal
> > > tpd1 = 0.171 + 3.357 + 0.080 + 0.068 + 0.345
> > > tpd1 = 4.021 ns
> > >
> > > External Timing (4mA drive strength LVTTL) :
> > > ==========================================
> > >
> > > total prop. delay = Setup time for bidi pin using column IOE registers
> > > + Hold Time for bidi pin using column IOE registers + Clock-to-Output
> > > Delay Bidi pin using column IOE registers
> > >
> > > In equation form I have this as:
> > >
> > > tpd2 = tinsu + tinh + toutco
> > > tpd2 = 2.33 + 0 + 4.922
> > > tpd2 = 7.252 ns
> > >
> > > ** Hopefully I interpreted the specifications correctly?
> > >
> > > If my interpretation is correct, the issue I have now is that I'm not
> > > sure if I should take total prop. delay = tpd1 + tpd2 = 11.273 ns?
> > > Does anyone know if this is the correct thing to do?
> > >
> > > My reasoning for combining both is that the internal one relates to
> > > the IOE internal timing & the external timing is associated directly
> > > to the output bidirectional pin.
> > >
> > > Regards,
> > > Pino
>
> Hi Pino,
>
> The equations above look wrong to me.
>
> It looks like what you're most worried about is the Tco of the output.
> That is given in the Stratix datasheet at
> http://www.altera.com/literature/hb/stx/ch_4_vol_1.pdf
>
> The parameter you want is Toutco. Its precise value depends on:
>
> 1. The device you are using (e.g. 1S10 vs. 1S80)
> 2. The speed grade
> 3. Whether you are using a PLL or not.
> 4. What kind of global network you are using (if you're not using a
> PLL).
> 5. The capacitive load on the IO (this is only an approximation of the
> true board delay; better accuracy requires that you actually simulate
> your board).
> 6. The IO standard, drive strength and slew rate you use.
>
> Assuming you want an LVTTL IO, driving a 10 pF load, using fast slew
> rate, and a 24 mA drive strength (this is the default IO setup), and
> are using a global clock with no PLL:
>
> Toutco = 4.71 ns in a 1S10 -5
> Toutco = 5.777 ns in a 1S80 -5
>
> If you use a 4 mA drive strength add 570 ps to the numbers above.
>
> If you use a PLL, things speed up by approximately 3 ns.
>
> While you can use the datasheet to answer these questions, I think
> you'll find it easier to just do simple sample designs in Quartus and
> look at the timing you achieve rather than doing manual timing
> analysis of various timing paths. The calculation I did above was
> just the Tco of the output (generally the most challenging timing
> parameter for this kind of design). To see the delays of paths into
> the IO input register and within the FPGA, it is easiest to just use
> Quartus rather than trying to add all the right numbers from the
> datasheet.
>
> You can grab a free version from
> https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp
>
> Vaughn
> Altera
Vaughn,
Thanks for the reply to this and I appreciate your advice in
using the timing analysis tool to extract a more appreciable number
than manual calculations. I still think the manual calculations also
give a good feel for how things are calculated internal to the
software. Quartus calculates ~ 8.4 ns, and my calculation above shows
close to that if I only use the External Timing. It seems from what
you mentioned, you only have to worry about Tco for the External
timing part within the documentation and not the Internal part.
I appreciate the clarification on the specific section.
Cheers,
Pino
Article: 72390
Hi All,
I am trying to boot linux on virtex 2 pro P7-ff672 board. My problem is
that I am able to boot the linux image(ppc) on bitstream generated by EDK
6.1 but not with bitstream generated by EDK 6.2 (SP2). Does anyone had
similar experience ? I wonder if the problem is EDK 6.2 or I need to change
my liuux image which should not be the case as I am using the same version
of cores. Following is the only message I get on bitstream generated by 6.2
EDK.
loaded at: 00400000 0045D1E4
board data at: 0045A13C 0045A154
relocated to: 00405600 00405618
zimage at: 00405AFB 00459C4F
avail ram: 0045E000 02000000
Linux/PPC load: root=/dev/nfs rw ip=on
Uncompressing Linux...done.
Now booting the kernel
While the same Image produce following message on 6.1 bitstream
loaded at: 00400000 005C71D0
board data at: 005C4128 005C4140
relocated to: 00405608 00405620
zimage at: 00405B24 0045A2AA
initrd at: 0045B000 005C3E44
avail ram: 005C8000 02000000
Linux/PPC load: root=/dev/ram
Uncompressing Linux...done.
Now booting the kernel
Linux version 2.4.18_mvl30-ml300 () (gcc version 3.2.1 20020930 (Mo
ntaVista)) #7 Mon Mar 1 19:31:21 MST 2004
Xilinx Virtex-II Pro port (C) 2002 MontaVista Software, Inc.
(source@mvista.com)
On node 0 totalpages: 8192
zone(0): 8192 pages.
zone(1): 0 pages.
zone(2): 0 pages.
Kernel command line: root=/dev/ram
Xilinx INTC #0 at 0xD0000FC0 mapped to 0xFDFFEFC0
Calibrating delay loop... 299.82 BogoMIPS
........
Any pointers or suggesitions are appreciated.
Thanks
raj
Article: 72391Hello group. PacoBlaze is my attempt to create a synthesizable and behavioral Verilog implementation of Ken Chapman's PicoBlaze embedded mcu: http://armoid.com/pacoblaze All PicoBlaze versions are targeted, however this is a work in progress and currently only the KCPSM3 instance is working. Please, if you have the chance to test it send me an email with your results. A rudimentary Java assembler (similar but not fully compatible with the original) is included. The source code for the micro and assembler are released under the modified BSD license for maximum flexibility. Many thanks to Ken Chapman from Xilinx for answering my questions and creating the PicoBlaze core in first place. Warmest regards. -- PabloBleyerKocik / pbleyer2004 /"Simplicity is prerequisite for reliability." @embedded.cl / -- Edsger Wybe DijkstraArticle: 72392
Gordon, Sure, this will work. Just remember that the power is then dissipated internally in the IO transistors. Austin Gordon wrote: > All, > > Conscious original intent of DCI: Our application involves driving 76 > discrete LEDs using a XC3S50. For cost reasons, we've decided to > drive each LED statically (as opposed to scanning). Each IO is > operating at LVDCI_33. > > Can we use DCI to current limit (~430 ohm) the LEDs? It looks like > LVDCI_33 is driver impedance controlled only, so the 3S50 will be a > current source. VCCO is 3.3V. > > Any comments / experience is appreciated. > > GordonArticle: 72393
I'm not sure if I would want to add a cache to a 6502 but you could design an upgrade that could replaced the 6502 with a 65816/65C816. The advantage of the 65816/65C816 is that it runs at 4 - 8 mhz and the original CPU was 1 - 2 mhz giving it a 2x - 8x the performance. The other big bonus is that you should be able to use SRAM cache that is the same size as the address space of the 6502. I'm sure it would make a Commodore VIC/C64/C128 or Apple II owner very happy. I'm sorry I just miss Commodore and the computers they use to make. Oh well back to work. Derek Simmons 7 <website_has_email@www.ecu.pwp.blueyonder.co.uk> wrote in message news:<SylUc.150065$28.99977@fe1.news.blueyonder.co.uk>... > I have a new cache. > Researched it as best as possible and it appears to be new. > Anyone interested? > Address matching in less > than 10% overhead of the cache RAM size in implementation for any size. > Not really interested in developing it myself. > Useful for gigahertz CPUs, missiles, supercomputers, mobile phones, > graphics cards, encryption, compression, and so on. > One or two months to modify vhdl of a 6502 or something > like that to see it working, > and then tape it out as fast as your legs can carry. > Its 2 or 3 pages to describe it in full in English. > One hour to do a presentation. > I'm interested in serious proposal.Article: 72394
Is XAPP462 up to date? I am running 6.1.03i and am getting completely different screen shots including IP(Architecture Wizard), Select Core Type, and other schematic-looking GUIs.Article: 72395
Sorry about all the messages ... Google Groups was acting up. Gordon elf_ster@hotmail.com (Gordon) wrote in message news:<4a2e9945.0408170713.57d62f2@posting.google.com>... > All, > > Conscious of the original intent of DCI: We're looking to drive a > number (read 76) LEDs using a XC3S50. VCCO is 3.3V. IO Standard will > be LVDCI_33. We're also aware that DCI is not available on Bank 5. > We've got plenty of spare IO so we've decided to drive things > statically (as opposed to scanning). > > Is it possible to use DCI to simulate current limiting resistors > (~430ohm) for each of the 76 LEDs? If so, it can save us a > significant amount of board space on an already tight board. > > Any comments / personal experiences appreciated. > > Gordon LauArticle: 72396
"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message > Module 4 also contains footprint drawings for all the available packages, > [...]The PDF diagrams are also color coded so you can > quickly see the various VCC inputs, grounds, clock pins, dedicated > configuration pins, etc. I would like to use this opportunity to say thank you to Xilinx for this feature. This is the most useful technical innovation since the time hard drive manufacturers started to print drive parameters on the drives. (Wich quickly became obsolete by bios autodetect features) Kolja SulimmaArticle: 72397
Hi I have a few questions (I belive the answers could be of general interest) 1) MGT POWERDOWN seems to be only possible way to tristate MGT TX, but there is seems to be some latency when exiting powerdown mode, unfortunatly this behaviour seems to be fully undocumented ? Any pointers numbers? 2) When AC coupled RX inputs are floating (or even short circuited rxn-rxp with SMB loopback cable) the MGT receiver keeps still receiving noise, this noise seems to have little different characteristics depending what MGT (in the same FPGA) is used. In all cases the noise seems to have some pattern with 4 data bits wide repeat cycle. This is probably normal, but it looked weird, any other observations or some explanation? 3) AC decoupling capacitors - any thumb formula what nominal to use depending on the the transmittion rate? Value of 0.01uF seems to be recommended, but it causes the RX DC balance to take quite long time to settle. When MGT TX is in TXINHIBIT mode the caps will fully charge, when then TX is restored (to 50:50 DC balance data stream) the charge on the AC decoupling caps makes the receiver lock to delay. During the time the AC decouplinc caps discharge the RX is receiving either constant 0 or 1. And that for a quite long time >= 100s of symbols. 4) There have been comments on this newsgroup that RocketIO can be used as high speed serial to parallel converted when all smart features are fully disabled - has anyone actually implemented this succesfully? Are there any special consideration/constraint that apply? As of my understanding there is some "life" inside the MGT (when all things are bypassed) that prevents this type of useage (see commet [2] about the noise). Thanks in advance, AnttiArticle: 72398
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:10i4scv38ooch25@corp.supernews.com... > Is XAPP462 up to date? I am running 6.1.03i and am getting completely > different screen shots including IP(Architecture Wizard), Select Core Type, > and other schematic-looking GUIs. The DCM Wizard--now called Clock Wizard in 6.1 and later--was updated. The screen shots in XAPP462 are from ISE 5.2. An update of XAPP462 is in progress, due out later this summer. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASICArticle: 72399
Have a look at FT2232C from FTDIchip.com. It is a simple USB slave controller that comes with the USB drivers. These drivers provide an UART com port on your PC. So interfacing this with your application is really easy. If your USB bus is not busy with other peripherals, you can get up to 8Mbit/s. So this should be sufficient for your application. /Daniel SneakerNet wrote: > Hi All > > We are currently involved in some DSP work where by we need to do further > analysis on the final results. > The final result is 16bits which is being captured at 48kHz. > Currently I am using SignalTap and using this I'm able to capture a max of > 8k samples, however this is not enough (as RAM is finite) and I was > wondering is there anyway of real-time spooling this data back to PC? > > I'm using Nios Development Board (Cyclone FPGA) and ByteBlaster II. > > Pls Advice > Regards
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