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<isa -->PCI> writes:
>I'm one of that "old" engineer with a bit of experience on ISA bus cards.
>Over the years I've designed and manufactured various cards for the ISA bus.
>But as the technology runs faster than I'm, my good-old cards become
>obsolete.
>
>I would like to ask what would be the simplest way of learning and
>experimenting on PCI bus ?
Have a look at PCI-to-"simplebus"-bridges, like PLX90xx (www.plxtech.com). They
are very easy to use and quite flexible...
The PCB-layout on the PCI side is not that critical for experimenting,
Vero-Wire-wrapping from a PCI breadboard to a QFP-adaptor-PCB works absolutely
flawless. I don't know what generic drivers PLX has for Windows, for Linux you
don't need one (if you can live without busmaster DMA or IRQs).
Doing an PCI-interface on your own in an FPGA is possible, but for a start
(getting the driver stuff right) a ready-made chip is IMHO better.
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 72751From another "old" engineer who had to update some ISA cards, you might want to consider a USB interface. If your quantities are small (as mine are) there are some nice USB products that will do wonders for your "time to market". Especially from a software/firmware standpoint. The software requirements for PCI compared to ISA is like comparing a bicycle to a Porsche. -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) "PCI>" <isa --> wrote in message news:4134a600$0$29950$afc38c87@news.optusnet.com.au... > I'm one of that "old" engineer with a bit of experience on ISA bus cards. > Over the years I've designed and manufactured various cards for the ISA bus. > But as the technology runs faster than I'm, my good-old cards become > obsolete. > > I would like to ask what would be the simplest way of learning and > experimenting on PCI bus ? > > >Article: 72752
Xilinx should try whatever Altera uses. Their Linux version of their tools seems to work fine. Wilbur Alex Gibson wrote: >"Rudolf Usselmann" <russelmann@hotmail.com> wrote in message >news:cgpi22$lkk$1@nobel.pacific.net.sg... > > >>Stephen Williams wrote: >> >> >> >>>Brad Smallridge wrote: >>> >>> >>>>Maybe it's one of those spaces in the path names problems disguised as >>>>path too long. >>>> >>>> >>>Might be. >>> >>>Have I mentioned yet that I hate this Wind/U atrocity?-) >>> >>> >>> >>I have to jump in here ! >> >>This Wind/U crap is made by some sort of a third party, to >>"easy" "porting" of windows applications to unix like systems. >> >>I can't see the usability of any GIUs made with this Wind/U >>stuff. Did anybody try to use EDK on Linux ? C'mon, I am >>trying to get a job done not finding out alternative ways >>to use a mouse and a keyboard. >> >>Great to see the results from the Wind/U "porting" tools. >>Don't have to bother evaluating or trying it out for any >>of our projects - what a piece of crap !!! >> >>If Xilinx could find an alternative to this Wind/U, I think >>they would have an excellent tool flow for Linux (plus fixing >>the paralle port support to something native of course). >> >> >> > >Well if they ever need a cross platform gui >they should look at wxwidget (was wxwindows ) >http://www.wxwindows.org/ >available for windows , linux and mac ox >as well as support for x, gtk+ , motif > >for some screenshots follow the links >http://www.wxwindows.org/screensh.htm > >for a list of users which includes AMD , AOL , Green Mountain(VHDL Studio), >ING (Bank), >Lockheed Martin, Ecos, Scitech , Xerox and others >http://www.wxwindows.org/users.htm > >for a list of applications writen using it >http://www.wxwindows.org/apps.htm > >wxperl http://wxperl.sourceforge.net/ >wxpython http://wxpython.org >are bindings for those languages > >Probably take a bit / while to rewrite but to have one >common main project would make it easier to >support multiple platforms. > > >Alex > > > >Article: 72753
Christian E. Boehme wrote: > The point I was trying to make was that the data sheet does > not explicitly tell whether there are clamping diodes in the > 5V PCI qualified buffers or not. Since Vcco is 3.3V maximum > at the input banks at the FPGA where would the clamping diodes > go without a 5V supply given that clamping to 3.3V is impossible ? The Spartan II datasheet, page 2 of module 2: Two forms of over-voltage protection are provided, one that permits 5V compliance, and one that does not. For 5V compliance, a zener-like structure connected to ground turns on when the output rises to approximately 6.5V. When 5V compliance is not required, a conventional clamp diode may be connected to the output supply voltage, VCCO. Page 31 of module 2: I/Os configured for the PCI, 33 MHz, 5V standard are also 5V-tolerant. -- Paul Fulghum paulkf@microgate.comArticle: 72754
"Ying Hu" <huying@lastechnologies.com> wrote in message news:<ee88431.1@webx.sUN8CHnE>... > Thanks Martin for the valuable > advice. > > Actually I already made some improvements to the design by > reducing Level_Of_Logic, adding FFs and giving some attributes. > > Since all the 5 FPGAs shares the same design and some of them can > run at a higher frequency, I think floorplanning is a better choice to > meet the timing requirement. > > For the current project, No manual floorplanning is done. > After adding those VHDL files and UCF files, I just let ISE to run automatically. > > Frankly speaking, I know nothing about floorplanning. Could anyone recommend any book/tutorial on this topic? Try to remove pin loc in your UCF, keep the clock/others constraints and let the SW assign the pins for you, see how fast you can go? From the result you may learn something...Article: 72755
hi I'm nev on this list and have question: Is there any possibility to buy Avnet's VirtexIIPro Eval Kit(ADS-XLX-V2PRO-EVLP7-5) in Europe, with discount from $500 to $250 - the code of this promotion is ADS-SPDWY-V2P. Regards -- ---------------------------------------------------------------------------- ------------------------------ Grzegorz Kasprowicz, AB Department, CERN, CH-1211 Geneva 23 office: 37 R-004, phone: +41 22 76 72584, fax: +41 22 76 78200 mailto: Grzegorz.Kasprowicz@cern.chArticle: 72756
Hi friends >>Paul N. wrote: >>>I am currently in a FPGA Desgin course that required us to design a 64 >>>bit floating point multiplier. I am very new to FPGA but have >>>experience in VHDL and computer architecture design. Can anyone >>>recommend a good book or a technical document on this subject matter? >>>Any personal knowledge on how to start this project is much >>>appreciated. You can try "Digital Signal Processing with FPGA" Second Edition by Uwe Meyer-Baese (Springer 2004), there is subchapter about floating-point arithmetic implementation. Very nice book for person with VHDL and com arch experience. > john jakson wrote: > And on the opposite side I was almost tempted to buy a text on FPU > design with all the schematics given, I forget the title, pretty much > all gate level, pity its not been brought up to date in HDL. IIRC it > was a German -> English book to supplement a DLX design tought in > schools. I figure the math books would be more usefull so the above > ref, I'll look into also. The HW books though could be usefull in > covering some of the thorny details. I think that the name of this book is "Computer Architecture-Complexity and Correctness" by S.Mueller and W.J.Paul, also from Springer, with chapters about fp arithmetics and data paths. Both of them discuss fp multipliers. These two books should be enought for your design. MichalArticle: 72757
Hello, I need to synthesize a verilog code for a Spartan device and was wondering whether I can use Icarus Verilog for this. I looked on the Icarus web page and it says that Icarus supports synthesis. I am pretty new to logic design and especially synthesis. Now I try to figure out how to synthesize my code for the Spartan. There are not really any device specific options given. The compiler can just be called with the -tfpga option. Is that all there is? Does this create me an edif file that I can import into ISE to do the place and route? I also tried searching the gEDA list archives for answers, but could not reach the server. Thanks for the help. GuenterArticle: 72758
"PCI>" <isa --> wrote in message news:4134a600$0$29950$afc38c87@news.optusnet.com.au... > I'm one of that "old" engineer with a bit of experience on ISA bus cards. > Over the years I've designed and manufactured various cards for the ISA bus. > But as the technology runs faster than I'm, my good-old cards become > obsolete. > > I would like to ask what would be the simplest way of learning and > experimenting on PCI bus ? As a 'not quite so old, but getting there' engineer I have done a couple of ISA based designs but realised that the ability to implement a PCI interface is becoming essential. I designed my 'EASY PCI' core to be as easy to integrate as possible. The PCI side of things is taken care of, the local bus side gives you an address bus, data bus in and out, 4 * CS lines and a Wr and Rd line. It's target only, a master version has been on the cards for a year but I haven't had the time to design/test it yet. The target will give 10MBytes/second write performance, about 8MBytes/second read. (The PCI bus allows burst transfers, but all the data I have found says that PC PCI bridge chips don't implement burst reads from target devices. If you want to get near to the theoretical PCI transfer bandwidth with a PC you have to use a device which can act as a bus master then transfer the data in bursts). The core's targeted at an Altera Cyclone, but is written with no architecture specific features implemented so could easily be re-targeted at Xilinx devices. It builds smaller than the Altera target only core so should be a good fit with the new MaxII development boards, I'll probably produce a cut-down version for that. I have also designed a proto-board to accompany the core, but again haven't had the time to get this produced in quantity. There's a core/board description on my web site if you want a look. I haven't finalised costs for the core, but it's _v_cheap_ compared to the Altera equivalent and the board space/design risk of a specific PCI interface IC. Good luck with the transition! Nial Stewart ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board www.nialstewartdevelopments.co.ukArticle: 72759
Austin Lesea wrote: > You might try reading the app notes? > > http://www.xilinx.com/bvdocs/appnotes/xapp653.pdf That one I did read and considered it for a while but dropped later due to lack of availability of the part. > http://www.xilinx.com/bvdocs/appnotes/xapp646.pdf This one I read also. Too bad that it's not applicable to my problem (namely _5V_ PCI tolerance ;). -ChrisArticle: 72760
Guenter Dannoritzer wrote: > Hello, > > I need to synthesize a verilog code for a Spartan device and was > wondering whether I can use Icarus Verilog for this. > > I looked on the Icarus web page and it says that Icarus supports > synthesis. I am pretty new to logic design and especially synthesis. > > Now I try to figure out how to synthesize my code for the Spartan. There > are not really any device specific options given. The compiler can just > be called with the -tfpga option. > > Is that all there is? Does this create me an edif file that I can import > into ISE to do the place and route? > > I also tried searching the gEDA list archives for answers, but could not > reach the server. "man iverilog-fpga" should give you some more answers. You specify relatively generic families and it will do synthesis for that, and generate and EDIF file. You will still need the Xilinx back-end tools to do the final map and par. I have to admit that you will probably find that the synthesis code generator can stand for some work. Not all cases are covered yet. I would have to say that this is more for experts who are willing to poke around the tools. If you are a software person trying to reform and go hardware, then I think you will find that the code fpga code generator source is well organized for easy update. It's also the most fun part of the Icarus Verilog source tree, as you can directly see the results of your labors in FPGAEditor:-) -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 72761
Austin Lesea wrote: > Spartan II is identical with Virtex, which means that the clamp diodes > can be programmed. Thus the device can operate just fine in the 5V > environment, and does meet the overshoot requirement of the PCI test > without any concerns. Clamping diodes only work in 3.3V PCI signaling environments. Since these programmable diodes clamp to Vcco and Vcco is 3.3V it's not too hard to imagine what a 5V steady level would do to the power department ;) -ChrisArticle: 72762
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> writes:
<....>
>(The PCI bus allows burst transfers, but all the data I have found says
>that PC PCI bridge chips don't implement burst reads from target
>devices. <...>
That's not entirely true. PCI bridges can of course do burst reads. They do
it only if requested by the CPU and that depends on the MMU-attributes of the
memory "behind" the PCI device. If the memory space is marked as prefetchable or
cacheable, a burst read is issued to fill a cache line even for a single read.
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 72763Paul Fulghum wrote: > The Spartan II datasheet, page 2 of module 2: > > Two forms of over-voltage protection are provided, > one that permits 5V compliance, and one that does not. > For 5V compliance, a zener-like structure connected > to ground turns on when the output rises to > approximately 6.5V. Probably slipped through because it says nothing about PCI, hmm ... > Page 31 of module 2: > > I/Os configured for the PCI, 33 MHz, 5V standard are also > 5V-tolerant. ^^^^^^^^^^^ Exactly that was the reason for the concern. I have been dealing with ``5V-tolerant'' standard logic (LVCMOS etcpp.) lately where the meaning of that term is technically something completely different from what I would expect from a ``5V-PCI-compliant'' device built in 3.3V technology. However, apart from the fuzzy 5V compliance and tolerance verbiage in the data sheet, that seems to answer my initial question. Thanks & regards, Christian BoehmeArticle: 72764
Hi, Just to re-state how Virtex and Spartan-II behave, so everyone's on the same page: When you use the SelectIO Modes "PCI33_3" or "PCI66_3" the clamp diodes are connected to VCCO (3.3v). The device is guaranteed to work in this environment. You would not want to use this in a 5.0v slot. When you use the SelectIO Mode "PCI33_5" the clamp diodes are not connected. You can use this in a 5.0v slot. The device is guaranteed by Xilinx to work in this environment. If you are building a universal card, the "right" way to do it is have two designs/bitstreams only differing in what SelectIO Mode is used. Then, at power-on, use an analog comparator to compare the slot's VIO with ~4.15v (make it with a voltage divider...) and load one of two bitstreams based on the result. Eric "Christian E. Boehme" wrote: > > Clamping diodes only work in 3.3V PCI signaling environments. > Since these programmable diodes clamp to Vcco and Vcco is 3.3V > it's not too hard to imagine what a 5V steady level would do > to the power department ;) > > -ChrisArticle: 72765
Christian, Yes. After I sent the first email, I realized that you were using Spartan II, not 3. Sigh. Next time I will be more careful on the send button. Engage brain. Virtex and Spartan II are what I call "Classic" FPGA parts: they do 5V PCI, they have hot insertion tri-state behavior, etc. In a way, the last of the great simple FPGAs. Everything since is based on the process technology getting more complicated (not to mention more internal features). In order to stay with high yields, we had to drop the floating outputs (not supported by foundries, so if anything goes wrong, like ESD -- you are on your on, and you own the wafers! which leads to higher costs to customers) as well as other nice features (like 0.35u IO transistors which are bulletproof). But a V1000 is old news, with a million "gates" becoming a small part today. The 2VP7 is now considered a very small part, with 3S1000 being the median member of the Soartan 3 family. S3 by the way has (finally) passed through the difficult times (first was process a year ago, next was demand was >>> supply). All parts (except one, again due to unprecedented demand) are in stock, and the last two largest family members should be out shortly (3S5000 is just shy of a Virtex 2V6000, or a Virtex II Pro 2VP50 in "gates"). Consult your disti, Austin Christian E. Boehme wrote: > Austin Lesea wrote: > >> You might try reading the app notes? >> >> http://www.xilinx.com/bvdocs/appnotes/xapp653.pdf > > > That one I did read and considered it for a while but > dropped later due to lack of availability of the part. > >> http://www.xilinx.com/bvdocs/appnotes/xapp646.pdf > > > This one I read also. Too bad that it's not applicable > to my problem (namely _5V_ PCI tolerance ;). > > > -Chris >Article: 72766
Christian, Yes, power would be the least of your worries: you would be sinking huge currents from the 5V rail to the 3.3V rail. Probably break something. Austin Christian E. Boehme wrote: > Austin Lesea wrote: > >> Spartan II is identical with Virtex, which means that the clamp diodes >> can be programmed. Thus the device can operate just fine in the 5V >> environment, and does meet the overshoot requirement of the PCI test >> without any concerns. > > > Clamping diodes only work in 3.3V PCI signaling environments. Since > these programmable diodes clamp to Vcco and Vcco is 3.3V it's not too > hard to imagine what a 5V steady level would do to the power department ;) > > > -Chris >Article: 72767
All, The zener structure is the ESD protection. It is not a simple zener. It is a complex SCR-zener ESD structure that was designed to pass the PCI requirement, yet also protect the device from ESD. Verrrry tricky. But it works, and gets tested, or it doesn't ship for Spartan II and Virtex. Eric is right: we stand behind the 5V and 3.3V PCI compliance on S2 and Virtex. Austin Christian E. Boehme wrote: > Paul Fulghum wrote: > >> The Spartan II datasheet, page 2 of module 2: >> >> Two forms of over-voltage protection are provided, >> one that permits 5V compliance, and one that does not. >> For 5V compliance, a zener-like structure connected >> to ground turns on when the output rises to >> approximately 6.5V. > > > Probably slipped through because it says nothing about > PCI, hmm ... > >> Page 31 of module 2: >> >> I/Os configured for the PCI, 33 MHz, 5V standard are also >> 5V-tolerant. > > ^^^^^^^^^^^ > > Exactly that was the reason for the concern. I have been dealing > with ``5V-tolerant'' standard logic (LVCMOS etcpp.) lately where > the meaning of that term is technically something completely > different from what I would expect from a ``5V-PCI-compliant'' > device built in 3.3V technology. > > However, apart from the fuzzy 5V compliance and tolerance > verbiage in the data sheet, that seems to answer my initial > question. > > > Thanks & regards, > Christian Boehme >Article: 72768
what is the procedure to be followed to run MGT of Virtex2 Pro on modelsim5.8b (for windows XP operating system). Is there any packages to be included or model sim SE 5.8b version and project navigator 6.2i supports it.Article: 72769
You need SWIFT support which is available with EE version I believe. http://support.xilinx.com/techdocs/14019.htm shalini wrote: > what is the procedure to be followed to run MGT of Virtex2 Pro on > modelsim5.8b (for windows XP operating system). Is there any packages > to be included or model sim SE 5.8b version and project navigator 6.2i > supports it.Article: 72770
I'm running Quartus (versions 4.0 and 4.1) on a Dell Inspiron 8600, with a dongle connected to the parallel port. The other day the dongle stopped being detected in Quartus. A printer still works off the port so it is fine, and port is set to ecp as required. The dongle works with other machines I am using. Has anyone got a program to determine the problem between the dongle and the parallel port? Maybe I will have to resort to using a debug tool to locate the problem.Article: 72771
Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> writes: > Alternatively, you could take the JDrive [open and free] Not even close. The Software contains copyrighted material, trade secrets, and other proprietary information. In order to protect them you may not decompile, reverse engineer, disassemble, or otherwise reduce the Software to a human-perceivable form. You agree not for any purpose to attempt to view or display the Software's object code on any computer screen or otherwise make copy of the Software code. You may not publish data information that compares performance with created distributed by others - aArticle: 72772
I also tought about the USB, but its packet structure (1ms) and not being able to use IRQ (and DMA) make the USB less appealing. "Gregory C. Read" <readgc.invalid@hotmail.com.invalid> wrote in message news:Uc3Zc.71$z05.37@trnddc08... > From another "old" engineer who had to update some ISA cards, you might > want > to consider a USB interface. If your quantities are small (as mine are) > there are some nice USB products that will do wonders for your "time to > market". Especially from a software/firmware standpoint. The software > requirements for PCI compared to ISA is like comparing a bicycle to a > Porsche. > > -- > GregArticle: 72773
Thank you for your posting. The board on www.fpga4fun.com looks VERY interesting BUT it is out of stock.. ... > I'm assuming you are interested in implementing your > PCI interfaces in an FPGA because you posted to this > newsgroup. > > As for learning about PCI, you can buy the PCI System > Architecture book by Mindshare. That's a good book, > especially if you don't have a copy of the spec itself. > If you can get a copy of the spec, that's an added > bonus. Check out http://www.pcisig.com > > Also, Xilinx offers PCI and PCI-X classes through the > Customer Education group. If you are willing and able > to enroll, they are not free but I think a great value. > > As for experimentation, you have a lot of options. It > comes down to finding hardware you like and can afford. > For example, several Xilinx distributors sell low cost > (less than $500) PCI prototyping boards. You can also > get one from http://www.fpga4fun.com for less than $300. > If you have easy access to manufacturing and assembly, > and want to build a batch of boards for a project, try > http://www.engr.sjsu.edu/crabill/projects/nxm/readme.htm > ...Article: 72774
Austin Lesea wrote: > The zener structure is the ESD protection. It is not a simple zener. It > is a complex SCR-zener ESD structure that was designed to pass the PCI > requirement, yet also protect the device from ESD. Verrrry tricky. But > it works, and gets tested, or it doesn't ship for Spartan II and Virtex. The datasheet calls the zener 'overvoltage protection'. Does it work as both overvoltage and ESD protection? The IBIS file for Spartan-II in the power clamp section of the PCI33_5 model shows that little current (~2 nA) is passed when the pin voltage goes over 6.5V The ground clamp section shows significant current when pin voltage drops below -0.5V as expected for the ground clamp diode. How does the zener structure protect from overvoltage if it does not pass significant current? Is the IBIS file not accounting for the zener structure? Am I misinterpreting the IBIS file? Thanks, Paul -- Paul Fulghum paulkf@microgate.com
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