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Hi, I have recently started work on a research project concerned with novel implementations of the CORDIC architecture to provide a high-speed, low power processor capable of affine transforms (translation, scaling, rotation, shearing) which will eventually be implemented as an FPGA chip. I am relatively new to the computer architecture field, and was hoping that someone out there might be able to point me to some useful resources on any of the following subjects: General introductions to ALUs Linear CORDIC implementations Current architectures with affine capabilities Principles of Low Power Architecture Design General Architecture design techniques Architecture Design using VHDL I am mainly looking for somewhere to start off, as I do not have much of an idea where to look at the moment... Any help you might be able to give me would be most helpful and greatly appreciated. Thanks in advance- -SelwynArticle: 75576
Hi Marcin, You need to set pld_RECONFIGREQ_n pin to '1'. I have no idea why Quartus defaults all unused pins to gnd instead of tri-stating them. You might also want to change your language to VHDL or Verilog, much better on your CV :-) Hans www.ht-lab.com "Marcin Olak" <kyokpae@aster.pl> wrote in message news:cmiju6$2a7d$1@mamut1.aster.pl... > Hello, > > I've quickly written AHDL code ( out = !in ), assigned out to the led > pin and in to the on-off switch pin. Then I downloaded that code into > Cyclone using ByteblasterII. Quartus reported that everything gone fine. > > BUT... > > ....all the leds started to blink (including the error led). It seemed > like > my design was being loaded then configuration controller realized that > something was not right and was reprogramming Cyclone again and again and > again and..... > > Does anybody know how to successfully program that Cyclone chip on the > Nios Development Board? > > I'll be very gratefull for any help. > > thanks in advance! > Marcin Olak > >Article: 75577
Hello Austin, thanks a lot for this scheme. This is far better than the schemes I tried. (Taking DCM "0 degree" & "180 degree" shifted clocks, normal inversion & passing through SSTL OBufs.) I have two more queries in this regard, 1. As a Spartan3 primitive - "FDDRRSE" is being used, this solution restricts the use of SP3 device (& V2, V2Pro) is there any way-out if one needs to use SP2, Virtex devices ? 2.In my design I need one more LVTTL 125 MHz clock out-of FPGA which should be phase-alligned with these SSTL clocks. The Post-PNR simulation that i have carried-out reveals that there is a phase differance between crossing-edges of SSTL pair & this LVTTL clock, of the order of 857 ps.is there any compensation technique fo this as well. (I have tried using I/Os whose physical locations are close to each other) Manish Austin Lesea <austin@xilinx.com> wrote in message news:<cmqnpp$s701@cliff.xsj.xilinx.com>... > Manish, > > It is better to use the DDR FF in the IOB to do clock forwarding with > the least duty cycle distortion. One IOB gets the DDR FF with the D > tied to Vcc for the top FF,and the D tied to GND on the bottom FF, and > the other (complement) IOB has the top D tied to GND, and the bottom D > tied to Vcc. > > Austin > > Manish wrote: > > Hi.. > > Is it recommended to use following scheme, to generate "Differential > > SSTL_2" clock signals which are sourcing DDR SDRAM & another > > controller. > > 1. Normal 125 MHz LVTTL clock source(Oscillator) feeding clock to > > FPGA. > > 2. FPGA functionality inverts this clock. > > 3. The same i/p clock & inverted clock are sent out of FPGA, with > > setting I/O standard of these to outputs as "OBUF_SSTL2_I". > > > > If this scheme is ok, will there be any constrain on using particular > > family of FPGA like Spartan 2, Spartan 3 or virtex etc. > > > > Cheers, > > ManishArticle: 75578
Hi George, The lmhostid is indeed the same as your MAC address. As far as I know flexlm still doesn't support hardware keys under Linux, thus you can only use the "easily changed" MAC address. Did you manage to install Designer on Slackware? I tried it on my Gentoo machine but it complained about the ksh interpreter, Hans www.ht-lab.com "geoerge" <georgevarughese@indiatimes.com> wrote in message news:1c3d8e19.0411052328.128adc4@posting.google.com... > Stefan Frank <stefrank@gmx.net> wrote in message > news:<418893d8$0$23487$4d4ebb8e@read.news.de.uu.net>... >> On 11/03/2004 08:52 AM, geoerge wrote: >> > I am trying to get a floating license for Actel Designer. When I enter > .... >> have you tried lmhostid from the flexlm utilities? If that does not >> work, try the MAC address of your ethernet card. >> >> The hostid command doesn't seem to be appropriate in all cases. >> >> HTH & HAND, >> Steff > > Thanks Steff, I got the registration done. It is strange, but I got a > 9 digit one from lmhostid. However, I prepended 000 to that and got it > registered. BTW, looks like mac address (from ifconfig) is same as the > lmhostid value. > > Thanks again, > GeorgeArticle: 75579
Hi, I'm planning to use ALVCH-Transceivers located 4-8 inches away from a 2V4000 FPGA. The board impedance is said to be 50R. I used IBIS models for both the transceiver and the FPGA (LVCM316S), and simulated one wire using PSPICE. The line is not terminated in any way. I get serious overshoot (>4V at 3.3V VCCO) and undershoot (-1V) at the (tri-stated) input of the FPGA. Current reaches 100mA during a short spike, otherwise some 50mA. My question: is this tolerable? Doc for VII-Pro states that the FPGA would suffer damage (gate oxide breakdown). Could it be that the simulation is too pessimistic in these cases? Thanks for any help GunterArticle: 75580
On 10 Nov 2004 02:22:34 -0800, selwyn.leeke@gmail.com (TheToad) wrote: >Hi, > >I have recently started work on a research project concerned with >novel implementations of the CORDIC architecture to provide a >high-speed, low power processor capable of affine transforms >(translation, scaling, rotation, shearing) which will eventually be >implemented as an FPGA chip. > >I am relatively new to the computer architecture field, and was hoping >that someone out there might be able to point me to some useful >resources on any of the following subjects: > > General introductions to ALUs > Linear CORDIC implementations > Current architectures with affine capabilities > Principles of Low Power Architecture Design > General Architecture design techniques > Architecture Design using VHDL > >I am mainly looking for somewhere to start off, as I do not have much >of an idea where to look at the moment... > >Any help you might be able to give me would be most helpful and >greatly appreciated. The last time I did something like this, I used normalised homogenous coordinates to represent the points. That way, all the affine transformation matrices can be multiplied together into a (3x3 or 4x4) matrix, and a single matrix multiplication is used to apply the aggregate transformation to a point in 2D or 3D space. I do not know if this is commonly used, however. http://www.google.com/search?q=homogeneous+coordinate Regards, AllanArticle: 75581
Gunter Knittel wrote:
> Hi,
>
> I'm planning to use ALVCH-Transceivers located 4-8 inches away from a 2V4000
> FPGA.
> The board impedance is said to be 50R. I used IBIS models for both
> the transceiver and the FPGA (LVCM316S), and simulated one wire using
> PSPICE. The line is not terminated in any way.
> I get serious overshoot (>4V at 3.3V VCCO) and undershoot (-1V)
> at the (tri-stated) input of the FPGA. Current reaches 100mA during a
> short spike, otherwise some 50mA.
> My question: is this tolerable?
> Doc for VII-Pro states that the FPGA would suffer damage (gate oxide
> breakdown).
> Could it be that the simulation is too pessimistic in these cases?
>
> Thanks for any help
> Gunter
Howdy Gunter,
I'm probably missing something here due to lack of sleep, but my
first reaction was that a 100 mA current spike into a tri-stated FPGA
pin doesn't seem quite right. I'm sure someone else will speak up on
that part of the issue.
Regardless, you could probably reduce the overshoot by using a ALVCHR
instead - they contain a ~25 Ohm series resistor. Another idea would be
to use a lower VCC (either in the ALVC, or on a related family that may
have higher input voltage tolerance like LVC or AVC).
Good luck,
Marc
Article: 75582> > What do you want? What sort of ballpark price are you interested in? > > LEDs and such aren't very expensive. You will probably do better > if you ignore them on some board that otherwise looks good. > > The Spartan3 starter kit is $100. That includes programming cable > and wall wart. It's got a couple of 40 pin connectors, but they > don't have enough ground pins for high end work. > > The FAQ has a page listing lots of board. Google can find it. Im trying to look for something a little higher end then a spartan-3, mabye a virtex-2 pro and above, something that can run at atleast 200MHz. This isnt for any classes, its for a bigger project. I have the spartan-3 starter board at the moment but its clock only rus to 50Mhz. Everyhting Ive seen for far has either a pci bus or some other bus on it which I wont be needing. The spartan 3 starter kit is basicly somehting I would like, but instead of a spartan-3, a virtex 2-pro or better. Ive looked around quite a bit and just ended up finding stuff over 1,000 atleast but has a lot of stuff that I dont want on it. I would like to make the connections myself since I will be making my own daughterboard to connect to it with some ADCs and an ethernet port. Ill keep looking around tho, but mainly Im curious if these 1000+ ranges are typical for basic FPGAs. Since the starter kit was pretty basic and only cost 100, I was thinking something that I would need would be under 1000. The general specs im looking for is something around 800k-1mil gates, with a pretty decent amount of ram. Ill continue to search for something, and Ill post back with what I find for references for other people if they need this info. Thanks! -MarkArticle: 75583
Hello, I am doing a project to build a system to receive GPS signals. I selected a Baseband Processor Zarlink GP4020 which has a ARM7TDMI core embened inside it. Now I want to add a FPGA(SpartanII XC2S200) to assist it in some arithmatic computation. And I want to use a Dual Port SRAM to store the temporary data and make the main processor and the FPGA communicate with each other. My question is : In what way can this two chip synchronize the process with each other? (maybe about timing and signal exchange) Thank you Regards PatrickArticle: 75584
Manish, See below, Austin Manish wrote: > Hello Austin, > thanks a lot for this scheme. This is far better than the schemes I > tried. > (Taking DCM "0 degree" & "180 degree" shifted clocks, normal inversion > & passing through SSTL OBufs.) > I have two more queries in this regard, > 1. As a Spartan3 primitive - "FDDRRSE" is being used, this solution > restricts the use of SP3 device (& V2, V2Pro) is there any way-out if > one needs to use SP2, Virtex devices ? Nope. Have to go back to using two separate BUFG clocks, CLK0 and CLK180. > 2.In my design I need one more LVTTL 125 MHz clock out-of FPGA which > should be phase-alligned with these SSTL clocks. > The Post-PNR simulation that i have carried-out reveals that there is > a phase differance between crossing-edges of SSTL pair & this LVTTL > clock, of the order of 857 ps.is there any compensation technique fo > this as well. > (I have tried using I/Os whose physical locations are close to each > other) There is always a slight (unavoidable) difference when you change IO standards. You clould use another DLL(DCM) to phase shift that output if that 857 ps is a problem. > > Manish > > > Austin Lesea <austin@xilinx.com> wrote in message news:<cmqnpp$s701@cliff.xsj.xilinx.com>... > >>Manish, >> >>It is better to use the DDR FF in the IOB to do clock forwarding with >>the least duty cycle distortion. One IOB gets the DDR FF with the D >>tied to Vcc for the top FF,and the D tied to GND on the bottom FF, and >>the other (complement) IOB has the top D tied to GND, and the bottom D >>tied to Vcc. >> >>Austin >> >>Manish wrote: >> >>>Hi.. >>>Is it recommended to use following scheme, to generate "Differential >>>SSTL_2" clock signals which are sourcing DDR SDRAM & another >>>controller. >>>1. Normal 125 MHz LVTTL clock source(Oscillator) feeding clock to >>>FPGA. >>>2. FPGA functionality inverts this clock. >>>3. The same i/p clock & inverted clock are sent out of FPGA, with >>>setting I/O standard of these to outputs as "OBUF_SSTL2_I". >>> >>>If this scheme is ok, will there be any constrain on using particular >>>family of FPGA like Spartan 2, Spartan 3 or virtex etc. >>> >>>Cheers, >>>ManishArticle: 75585
Gunter, The protection diodes are clamping the overshoot and undershoot. They will not be damaged, but your signal integrity is terrible, you will have excessive jitter, and that may lead to bit errors, and other behavior that you will not like at all. I doubt the simulation is pessimistic, as I get the same results, and often worse when too strong a driver is used unterminated. I suggest a small series resistor at the driver to better match the lines. Perhaps somewhere from 22 ohms to 43 ohms. Simulate until you have the best choice for the slow/weak and fast/strong IBIS model corners. Oh, and thank you for using IBIS before you built the board. We are happy (and you are happy) when you fix problems before the board layout. Austin Gunter Knittel wrote: > Hi, > > I'm planning to use ALVCH-Transceivers located 4-8 inches away from a 2V4000 > FPGA. > The board impedance is said to be 50R. I used IBIS models for both > the transceiver and the FPGA (LVCM316S), and simulated one wire using > PSPICE. The line is not terminated in any way. > I get serious overshoot (>4V at 3.3V VCCO) and undershoot (-1V) > at the (tri-stated) input of the FPGA. Current reaches 100mA during a > short spike, otherwise some 50mA. > My question: is this tolerable? > Doc for VII-Pro states that the FPGA would suffer damage (gate oxide > breakdown). > Could it be that the simulation is too pessimistic in these cases? > > Thanks for any help > Gunter > > >Article: 75586
"weizbox" <mwiesbock@gmail.com> escribió en el mensaje news:335c6753.0411100638.10064ee7@posting.google.com... > The general specs im looking for is > something around 800k-1mil gates, with a pretty decent amount of ram. You might want to take a look at www.xess.com . They are about to introduce the XSA-3S1000, 1M gates for under $200. Regards Josep DuranArticle: 75587
User Guide says that in Slave SelectMAP mode the CS pin can be de-asserted for clock cycles in which data is not available. Can I do the same thing in Master SelectMAP mode? The UG does not specifically say that I can. I wish to boot from config rom or from USB. Circuitry is a bit simpler if both cases can be same mode (Master), but in the USB case I cannot guarantee the USB receive fifo will never run dry. Thus I need to pause the Master. Thanks.Article: 75588
>Im trying to look for something a little higher end then a spartan-3, >mabye a virtex-2 pro and above, something that can run at atleast >200MHz. This isnt for any classes, its for a bigger project. I have >the spartan-3 starter board at the moment but its clock only rus to >50Mhz. ... Have you tried using the DCM to multiply by 4? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 75589
I am having trouble getting the VirtexII-Pro Rocket IO to work in 8/10 bit bypass mode. I understand that using the HW-AFX-FF1152-300 board may degrade performance but not to the degree that I am seeing. Can someone with experience shed some light into the problems that I am facing? Here is the situation. Using a 50Mhz oscillator I am trying to achieve a channel bit rate of 1Gbps in 8/10 bypass mode. For every 20 bits, I am transmitting 5 'ones' in random positions. This should ensure that I have at least 1 transition every 20 bits and enough for the PLL to lock on to the clock. What I am seeing is that the bit error rate is very high (>0.1). This is the case even when I set the MGT to serial bypass mode. What can be the cause of this since this configuration introduces no transmission losses? The BER decreases as the number of 'ones' increase. At 10 'ones', I am seeing BER of <10e-12. Where should I start in trying to solve this problem? I would appreciate any help that anyone can give me.Article: 75590
Hi All, I have a small project which requires a 30 something Combinational Logic Block CPLD with 20ns delay. In the good old days, I would have done this using several 22V10s. Given that I can start this one from scratch, I though that it might be time to see what is new - hence this posting. Prioritized requirements are as follows: 1) Availability of parts. Digikey is probably the easiest distributor to use where I am located (NZ). There is no point designing in a super new part if I can't buy them easily. Quad Flat Pack is preferred, PLCC will be OK and BGA is out of the question. 2) Development tools. Verilog is preferred, but I can probably get away with a Register Translation Language, or Schematic Capture. This is a small project, so I don't want to spend more than a few US$100s on tools. I have Orcad 9 and Protel 99 if that helps. 3) Programming tools. Same as 2, I don't want to buy a US$1200 programmer for the 30 or so devices I will be using in production. 4) EEPROM or FLASH part. This is a small project; I really don't want to burden the system with a serial boot EEPROM. Programming using a JTAG or and in circuit pod would be very nice. Usual problem really - high speed, low power, delivered yesterday on $0 budget. Any thoughts and pointers for our against current tools and manufacturers appreciated. Thanks, MarkArticle: 75591
Mark Aren wrote: > Hi All, > > I have a small project which requires a 30 something Combinational > Logic Block CPLD with 20ns delay. In the good old days, I would have > done this using several 22V10s. > > Given that I can start this one from scratch, I though that it might > be time to see what is new - hence this posting. > > Prioritized requirements are as follows: > > 1) Availability of parts. Digikey is probably the easiest distributor > to use where I am located (NZ). Well, you could try a NZ distributor, who have them on the shelf ? :) [ eg Apex ph 04 385 3404 ? ] > There is no point designing in a super > new part if I can't buy them easily. Quad Flat Pack is preferred, PLCC > will be OK and BGA is out of the question. > > 2) Development tools. Verilog is preferred, but I can probably get > away with a Register Translation Language, or Schematic Capture. This > is a small project, so I don't want to spend more than a few US$100s > on tools. I have Orcad 9 and Protel 99 if that helps. > > 3) Programming tools. Same as 2, I don't want to buy a US$1200 > programmer for the 30 or so devices I will be using in production. > > 4) EEPROM or FLASH part. This is a small project; I really don't want > to burden the system with a serial boot EEPROM. Programming using a > JTAG or and in circuit pod would be very nice. > > Usual problem really - high speed, low power, delivered yesterday on > $0 budget. > > Any thoughts and pointers for our against current tools and > manufacturers appreciated. You focused so much on price, you forgot to mention Vcc! If you want 5V, then Atmel ATF1502ASL [ATF1504 etc] is the ideal. For tools, use their WinCUPL [Free] - this can create test vectors, you can use in a programmer, if you want. http://www.atmel.com/dyn/products/tools_card.asp?tool_id=2759 Code entry is Boolean Equations, which is all you need for 30 MC designs. If you want 1.8V core, and lower Vcc (and faster) then look at Xilinx CoolrunnerII, and Lattice 4000z family. If you want a more FPGA fabric, and >= 128MC equiv, and medium power, then Altera are also an option. -jgArticle: 75592
I'm facing some timing problems and I'm not really sure how to proceed. In this design, there is a Nios processor, and a good bit of supporting components to interface with an external DSP (close to 9,000 LEs total). There are two UART/fifo components (written in-house) to support communication between the DSP and some other components. There were no problems until I added a third UART -- now there are lots of timing problems. The timing report indicates slack times up to 30ns (on a clock that is 60Mhz). The weird part is that after I deleted the additional component the timing problems still remain. I even reverted back to the previous version from CVS, but the timing problems still remain (and I know the version checked into the CVS server had no timing problems two days ago). What are the best steps to take to iron out timing problems? Is it worth doing some floorplanning? or is there maybe something more obvious that I'm overlooking? thnx, -PArticle: 75593
Hi, Try reading up on the TMC2301 / LF2301. This is an image processor that's been around for a while. EricArticle: 75594
"Herwin" <herwin@ee.ucla.edu> wrote in message news:6314bb40.0411101033.43e00fd4@posting.google.com... > I am having trouble getting the VirtexII-Pro Rocket IO to work in 8/10 > bit bypass mode. I understand that using the HW-AFX-FF1152-300 board > may degrade performance but not to the degree that I am seeing. Can > someone with experience shed some light into the problems that I am > facing? > > Here is the situation. Using a 50Mhz oscillator I am trying to > achieve a channel bit rate of 1Gbps in 8/10 bypass mode. For every 20 > bits, I am transmitting 5 'ones' in random positions. This should > ensure that I have at least 1 transition every 20 bits and enough for > the PLL to lock on to the clock. What I am seeing is that the bit > error rate is very high (>0.1). This is the case even when I set the > MGT to serial bypass mode. What can be the cause of this since this > configuration introduces no transmission losses? > > The BER decreases as the number of 'ones' increase. At 10 'ones', I > am seeing BER of <10e-12. Where should I start in trying to solve > this problem? > > I would appreciate any help that anyone can give me. Couple of questions to start off with... What's your receiver? If you're receiving into another MGT in the same chip, does it use the same or independant clocking resources? My guess is that you're exceeding jitter tolerance or frequency accuracy somewhere. The REFCLK tolerance is pretty tight, --JoshArticle: 75595
I just got one of these Xilinx V4 tshirts that must have been vacuumed sealed into a small package in the shape of a football. It was so small I thought it was a notepad. Well- I opened this thing up- and it was more wrinkled than prune. It seriously looks damaged it was crinkled up so tight. I haven't tried washing it yet. Has anyone managed to get all the wrinkles out?Article: 75596
Hi Patrick, I did take a quick look on the datasheet of the GP4020. It has a Module named "MPC". Through this interface you connect memory peripherals. Use this interface to connect your FPGA as a 'Coprocessor' to your system. Just Address & Data & Control to build a simple Slave interface in the FPGA. Just take a piece of paper and make a block diagram. It should not be to difficult to name the signals needed. For data exchange. Do you need interrupts as well? Another issue is FPGA configuration. Don't forget it ... "Patrick Gao" <foolboylei@vip.sina.com> wrote in message news:<cmt9n6$idh$1@news.yaako.com>... > Hello, > > I am doing a project to build a system to receive GPS signals. > > I selected a Baseband Processor Zarlink GP4020 which has a ARM7TDMI core > embened inside it. > > Now I want to add a FPGA(SpartanII XC2S200) to assist it in some arithmatic > computation. And I want to use a Dual Port SRAM to store the temporary data > and make the main processor and the FPGA communicate with each other. > > My question is : In what way can this two chip synchronize the process with > each other? (maybe about timing and signal exchange) You can use Flags or interrupts if available on the GP4020. I do not get the point of your question. In the Spartan-II you may make the option of the true dual ported nature of the memory blocks for data exchange from different clock domains ... Markus > > > Thank you > > Regards > PatrickArticle: 75597
On 10 Nov 2004 13:30:48 -0800, wpiman@aol.com (MS) wrote: >I just got one of these Xilinx V4 tshirts that must have been vacuumed >sealed into a small package in the shape of a football. It was so >small I thought it was a notepad. Well- I opened this thing up- and >it was more wrinkled than prune. It seriously looks damaged it was >crinkled up so tight. > >I haven't tried washing it yet. Has anyone managed to get all the >wrinkles out? Forgive me for asking, but if you object to wearing a free, wrinkled T-shirt, are you absolutely certain you're an engineer? Bob Perlman Cambrian Design WorksArticle: 75598
Bob, Bob Perlman wrote: > On 10 Nov 2004 13:30:48 -0800, wpiman@aol.com (MS) wrote: >> >>I haven't tried washing it yet. Has anyone managed to get all the >>wrinkles out? > > Forgive me for asking, but if you object to wearing a free, wrinkled > T-shirt, are you absolutely certain you're an engineer? That's priceless - deserves to be printed and framed! JohnArticle: 75599
John Williams wrote: > Bob, > Bob Perlman wrote: >> On 10 Nov 2004 13:30:48 -0800, wpiman@aol.com (MS) wrote: >>> I haven't tried washing it yet. Has anyone managed to get all the >>> wrinkles out? >> Forgive me for asking, but if you object to wearing a free, wrinkled >> T-shirt, are you absolutely certain you're an engineer? > That's priceless - deserves to be printed and framed! Printed on a T-shirt, I am not sure about framing of shirts. -- glen
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