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Brad, if your FIFO uses one common clock for write and read, and you really do not care about FULL or EMPTY (because your system design takes care of or avoids that situation), then just ignore the core generator and simply hook two counters to the two address ports, and declare one port the write input side, and the other one the read output side. That means you need one slice per two address bits, and totally exactly as many slices as your addressing is wide, i.e. 16 max. Most of the complexity (and trouble and frustration...) of a FIFO design is due to the asynchronous nature of the two clocks, while reliable EMPTY/FULL signals must be decoded. Peter AlfkeArticle: 76926
Kevin Neilson wrote:
> Kevin Neilson wrote:
>
>> Synplify now reads the defparam 'INIT' used for instantiated SRLs, so
>> you can initialize the value of the SRL16 for both simulation and
>> synthesis with a single defparam. However, I'm wondering if there is
>> a way to infer SRL16 Johnson rings or shift registers with an initial
>> value. This can be done with registers by setting the 'reset' value
>> of the register to the desired value, but you can't have a reset
>> clause with SRLs or they won't get inferred as SRLs. It would be
>> nice to be able to infer a Johnson ring because if you want to
>> instantiate SRLs you need to instantiate one for each 16 bits of the
>> register which makes it hard to parameterize it.
>
No, you pretty much have to instance the SRLs to take advantage of
putting the inits on them. You might be able to do it from the UCF (I
never tried that), but that makes the simulation not match the
hardware. That said, be careful using just the SRL as a johnson
counter, because there is no way to reset it other than
reconfiguration...ie, it won't recover from an upset. Ken Chapman kind
of glosses over that fact in his dissertation on SRL16's.
> I also have another question: I put a register on the output of the
> SRL to register the output. I assumed that the register would be
> placed in the same slice as the SRL, but the placer puts them in
> different CLBs. Why would it do that? -Kevin
Probably doing that because you're using the reset on the register. The
reset pin is not available if you are using the SRL in the same half-slice.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 76927You hit on an excellent point, that non binary values of Y indicated below CAN be easily implemented by adding a different value to the phase accumulator on one cycle after the phase accumulator overflows. I used this technique explicitly years ago to avoid some problems, adding a small delta so I repeated the same phase values over and over. The technique can apply to fractions with much smaller accumulators with the added benefit of no very-close-in spurs in your spectrum that can't be filtered out. I put together an Excel spreadsheet for figuring the best fractions (in order) for a given value with nice results. It's pretty easy to have a bound value for most fractions with a very acceptable accuracy without the extremely low frequency spurs. The one caution with the overflow-based correction is that 50% duty cycle is degraded in the simplest implementation. If all you need is an edge or a pulse, it's great. If you need (closer to) 50%, you need an overflow correction for each half of the clock cycle. For X/Y = 12/1021, the phase accumulator normally adds 12 to a 10 bit accumulator. On overflow, the phase value is "behind" by 3 bits so the phase accumulator gets 15 added for that round. In 1021 cycles, there are 12 overflows resuling in a phase accumulator value of (1021-12)*12 + 12*15 = 12*1024. Modulo 1024, that's back to 0. "Hal Murray" <hmurray@suespammers.org> wrote in message news:beudnbybkd66N13cRVn-qg@megapath.net... > This is leftover from a couple of discussions a week or two ago. > There is something interesting that I don't understand. > > In general, if I have an input clock and I want to generate > an output clock, and the output clock is (much) slower than > the input clock, I can do that with a FSM. > > The jitter on the output clock can be up to 1/2 of the input > clock off. (If it's off more, move it over by one.) If you > are lucky and the numbers work out exactly, you get no jitter. > (For example, dividing by 4.) > > But how close is the frequency? The output frequency is > out = in * X / Y > Y is the number of states in the FSM. > > Some combinations of X and Y give a better match to the > target frequency. I'm pretty sure a math wizard would use > continued fractions to explain it. > > I know how to implement this if Y is a power of 2. That's > just an adder and it generally fits well into FPGA. Given > a minute or 3, I can work out the value of the constant to > add. > > It's easy to get closer to the target frequency by using more > bits in the adder. If the bottom bit of the constant isn't a > 1, then the adder will skip 1/2 (or 3/4 or..) of the states. > So there are sweet spots where the bottom bit of the constant > is a 1. > > This approach is also convenient if you want to make > a sine wave rather than a square wave since you can > feed the top N bits of the adder to a ROM lookup table. > > But powers of 2 may not work as well as some simple pairs > of X and Y. Is there a simple implementation technique > for arbitrary Y that fits well into FPGAs? Is it something > as simple as use an adder and reset it back to 0 after Y > steps? > > Is there a good web page or book that covers this area? > > Next step is to understand the spectrum of the synthesised > clock. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 76928
Thank you for your reply. I made a test, two instance, one calculate A*B, the other calculate A*A, oprand is 20 bit. I found they are almost the same result. After map, both occupy 215 slices (VirtexE). And only small difference in the time delay. ISE translate the square operation to multiplier.Article: 76929
Bret Wade wrote: > The sizes on the web page are being corrected. Meanwhile, here are the > correct numbers: > > 6_3_03i_sol.tar.gz --> 287 MB > 6_3_03i_lin.tar.gz --> 291 MB > 6_3_03i_pc.exe --> 261 MB > > Bret Hi Bret, Can I install SP3 on Xilinx 6.3 Student Edition from Prentice Hall? BTW, what is the different between that and Webpack or BaseX? HendraArticle: 76930
Patrick wrote: > Hello, > > i'm trying to stop a running executable on the ppc405 placed on a > virtex2-pro. > ^C in gdb over xmd over jtag? -TonyArticle: 76931
Some colleagues and I were discussing the situation with the high tech industry, with jobs moving out of North America. This has hit circuit designers hard, especially those in digital. Can EDA tool development be expected to follow suit, is has it already happened? If not, what are the factors that differentiate it from design work to make it less exportable? Comments are also welcome for automatation of methodologies for programmable system-on-chip e.g. reconfigurable processor arrays.Article: 76932
On Wed, 15 Dec 2004 15:18:31 -0600, hmurray@suespammers.org (Hal
Murray) wrote:
>This is leftover from a couple of discussions a week or two ago.
>There is something interesting that I don't understand.
>
>In general, if I have an input clock and I want to generate
>an output clock, and the output clock is (much) slower than
>the input clock, I can do that with a FSM.
>
>The jitter on the output clock can be up to 1/2 of the input
>clock off. (If it's off more, move it over by one.) If you
>are lucky and the numbers work out exactly, you get no jitter.
>(For example, dividing by 4.)
The peak to peak output jitter at the output can be up to 1 period of
the input clock.
You can use both edges of the input clock to halve this (assuming a
50% duty cycle).
>But how close is the frequency? The output frequency is
> out = in * X / Y
>Y is the number of states in the FSM.
>
>Some combinations of X and Y give a better match to the
>target frequency. I'm pretty sure a math wizard would use
>continued fractions to explain it.
>
>I know how to implement this if Y is a power of 2. That's
>just an adder and it generally fits well into FPGA. Given
>a minute or 3, I can work out the value of the constant to
>add.
>
>It's easy to get closer to the target frequency by using more
>bits in the adder. If the bottom bit of the constant isn't a
>1, then the adder will skip 1/2 (or 3/4 or..) of the states.
>So there are sweet spots where the bottom bit of the constant
>is a 1.
>
> This approach is also convenient if you want to make
> a sine wave rather than a square wave since you can
> feed the top N bits of the adder to a ROM lookup table.
>
>But powers of 2 may not work as well as some simple pairs
>of X and Y. Is there a simple implementation technique
>for arbitrary Y that fits well into FPGAs?
Yes.
The phase accumulator will always produce a frequency of the form
c
--------------- * Fin
(2 ** num_bits)
As you point out, increasing num_bits improves the accuracy, but can
never give an exact result for some ratios.
There's a different archicture that produces a frequency of the form:
(a + b)
----------------------- * Fin
(a * n) + (b * (n + 1))
This uses a dual modulus prescaler that divides the input clock by
either n or n+1. An FSM twiddles the control of the prescaler to
produce the correct average division.
For a lot of practical ratios (such as those met in telecommunications
circuits) this can produce the exact ratio with the minimum jitter,
often using fewer flip flops than a comparable phase accumulator
solution.
>Is there a good web page or book that covers this area?
http://fractional-divider.tripod.com/
contains a perl script that works out the nasty details for you, then
generates synthesisable VHDL and Verilog code.
Disclaimer: I wrote the script.
>Next step is to understand the spectrum of the synthesised
>clock.
That's a little tricky, but can be done.
Regards,
Allan
Article: 76933EDA wannabe wrote: > Can EDA tool development > be expected to follow suit, is has it already happened? EdWin, the nightmarish Swedish PCB CAD system, has been "developed" in India for several years now. Paul BurkeArticle: 76934
Hi Austin, It would seem to me that the laser fuse method is a much better idea than EasyPath(tm). As you say in another post, we live in an errored world! With the laser fuse, yield is higher, price is lower. With EasyPath(tm), you scrabble around in the defect bin to find dodgy parts which fit the user's design. The design then must remain unchanged, because a recompile might hit a bad bit in your installed base. Maybe you should rename it DifficultPath(tm)? Or am I missing something? No worse than an ASIC, I guess. Syms. "Austin Lesea" <austin@xilinx.com> wrote in message news:cpq28u$9kt2@cliff.xsj.xilinx.com... > EasyPath(tm) is no different that selling an FPGA that has a laser fuse > blown to replace a defective column of logic. > > Gee, I wonder who does that with every part they sell?Article: 76935
I just read the V4 user guide, UG070. It seems the really tricky bit is making sure the FULL signal goes high when the FIFO is full. Not one write clock cycle later. ;-) Cheers, Syms. "Peter" <peter@xilinx.com> wrote in message news:1103155097.582753.217240@c13g2000cwb.googlegroups.com... > Most of the complexity (and trouble and frustration...) of a FIFO > design is due to the asynchronous nature of the two clocks, while > reliable EMPTY/FULL signals must be decoded. > Peter Alfke >Article: 76936
>With a 27-bit accumulator clocked at 100 MHz, you can generate any >integer Hz frequency, but with 5 ns jitter. Thanks, but that looks like a variation on what I was asking about. I can't see how to make a 1 Hz output with a 27 bit phase accumulator running at 100 MHz. Works great if I have a 134.217728 MHz clock. If I have a 27 bit accumulator and I add 1 each cycle with a 100 MHz clock, I get 0.745 Hz. Adding 2 makes 1.490 Hz. Is there some variation of the simple phase accumulator that I haven't stumbled into yet? If so, what's the magic word? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76937
Hal, Make the accumulator overflow at 100,000,000 rather than at 134217728. HTH, Syms. "Hal Murray" <hmurray@suespammers.org> wrote in message news:G8udnZiTqfj5wlzcRVn-2g@megapath.net... > >With a 27-bit accumulator clocked at 100 MHz, you can generate any >>integer Hz frequency, but with 5 ns jitter. > > Thanks, but that looks like a variation on what I was asking about. > > I can't see how to make a 1 Hz output with a 27 bit phase accumulator > running at 100 MHz. Works great if I have a 134.217728 MHz clock. > > If I have a 27 bit accumulator and I add 1 each cycle with a > 100 MHz clock, I get 0.745 Hz. Adding 2 makes 1.490 Hz. > > Is there some variation of the simple phase accumulator that I > haven't stumbled into yet? If so, what's the magic word?Article: 76938
In article <41C0FFE5.6BDE4AFF@Email.Address.com>, EDA wannabe <No@Email.Address.com> wrote: >Some colleagues and I were discussing the situation with the high tech >industry, with jobs moving out of North America. This has hit circuit >designers hard, especially those in digital. Can EDA tool development >be expected to follow suit, is has it already happened? It's already happening to a large degree. Most of the big EDA companies have India/China SW R&D offices. > If not, what >are the factors that differentiate it from design work to make it less >exportable? It's just as easy to export EDA development jobs as it is to export circuit design. Might be easier since software developers are readily available. Probably the best bet if you want an EDA job in the US is to get a PhD, but even some of the highlevel research is starting to move over. It's not a pretty picture. The standard of living will likely have to fall a good bit in the US before you see these kinds of jobs move back. PhilArticle: 76939
>What you describe is called DDS, Direct Digital Synthesis. Go to >www.analog.com, they have plenty of stuff for that. And also a very good >tutorial on the toppic. Thanks. In case anybody else gets curious: Ask The Application Engineer-33 All About Direct Digital Synthesis http://www.analog.com/library/analogDialogue/archives/38-08/dds.html A Technical Tutorial on Digital Signal Synthesis (120 pages) http://www.analog.com/UploadedFiles/Tutorials/450968421DDS_Tutorial_rev12-2-99.pdf (I haven't read it carefully yet. Lots of good stuff.) >> But powers of 2 may not work as well as some simple pairs >> of X and Y. Is there a simple implementation technique >> for arbitrary Y that fits well into FPGAs? Is it something > >Again, DDS. It look a little bit weired on the first sight, but then turn >out to a (almost) perfect oscillator. How do I implement a phase accumulator if Y is not a power of 2? Suppose I want an output that is exactly 4/17 of the input. That's almost a divide by 4. Just need to insert an extra stutter every 17 cycles. I can do that with a 17 state FSM. (34 states gets DC ballance.) For the simple phase accumulator, the magic number to add is 0.3C3C3C3... (hex, decimal point on the left edge) That's a repeating fraction. Making the accumulator bigger will get closer, but never an exact match. Yet a simple 17 state FSM is right on. Is there a term for something like that? Is there an easy way to implement them? (Simpler than a table driven FSM for large numbers of states.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76940
Hal, For 4/17 you should implement accum <= (accum + 4) mod 17; Generate your output enable with an overflow signal. Cheers, Syms. "Hal Murray" <hmurray@suespammers.org> wrote in message news:ufWdnSQ3WaVF_1zcRVn-rg@megapath.net... > > How do I implement a phase accumulator if Y is not a power of 2? > > Suppose I want an output that is exactly 4/17 of the input. > That's almost a divide by 4. Just need to insert an extra > stutter every 17 cycles. I can do that with a 17 state FSM. > (34 states gets DC ballance.) >Article: 76941
>Make the accumulator overflow at 100,000,000 rather than at 134217728. Ahh. That seems like a key idea. Is there a name/term for this variation? I've been stuck in the rut of thinking of the decimal point to the left of the accumulator. The top bit is the output if you want a square wave. Use the top N bits and a ROM if you want a sine wave. If I want a 50% duty cycle, I think I have to move the decimal point 1 step to the right and "overflow" the fraction at 50,000,000. Move it more for the sine/ROM trick. Or something like that. But that's just a scaling factor. I still don't see how to easily implement "overflow" at an arbitrary value. Time to sleep on it. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 76942
"Hal Murray" <hmurray@suespammers.org> wrote in message news:0qadncXIAdX6-lzcRVn-ig@megapath.net... > >Make the accumulator overflow at 100,000,000 rather than at 134217728. > > Ahh. That seems like a key idea. Is there a name/term for this > variation? > > I've been stuck in the rut of thinking of the decimal point > to the left of the accumulator. The top bit is the output > if you want a square wave. Use the top N bits and a ROM > if you want a sine wave. > > If I want a 50% duty cycle, I think I have to move the decimal > point 1 step to the right and "overflow" the fraction at 50,000,000. > Move it more for the sine/ROM trick. Or something like that. > But that's just a scaling factor. > How about:- if accum < 50000000 then accum <= accum + freq; else accum <= accum + freq - 50000000; out <= not out; end if; > I still don't see how to easily implement "overflow" at an > arbitrary value. Time to sleep on it. > I thought you were up late! I'm on a trip to the UK; time for lunch! best, Syms.Article: 76943
Hi all, I am using Altera Quartus 4.0 edition, which is working fine, as far as compilation of designs etc. is concerned. However whenever I click on Tools --> SOPC Builder (after opening a project), it gives me the following message in a message box: ------ Error: Path to Quartus SOPC Builder installation: c:/program files/quartus/sopc_builder contains spaces, which is not permitted. You will need to install Quartus at a location without spaces in its path. ---------- After clicking OK on message box, the SOPC template disappears and the tool is never instaniated. I don't want to reinstall my Quartus edition again. If anybody has an idea on how this error can be removed or how I can change the path of SOPC Builder instaniation (say by putting "program files" as "progra~1" somewhere, as we normally do in such cases), please help asap. Thanx in advance.Article: 76944
John_H wrote: > You hit on an excellent point, that non binary values of Y indicated below > CAN be easily implemented by adding a different value to the phase > accumulator on one cycle after the phase accumulator overflows. This is essentially Bresenhams algorithm for line drawing: http://www.cs.helsinki.fi/group/goa/mallinnus/lines/bresenh.html Bresenham is used to draw a line that moves up by dy pixels while going to the right for dx pixels. You can easily translate it to generating dy clock output transitions during dx clock cycles. The algorithm produces provably minimum error. Kolja SulimmaArticle: 76945
I read in sci.electronics.design that Phil Tomson <ptkwt@aracnet.com> wrote (in <cprnfc02h25@enews3.newsguy.com>) about 'Exportability of EDA industry from North America?', on Thu, 16 Dec 2004: >It's not a pretty picture. The standard of living will likely have to >fall a good bit in the US before you see these kinds of jobs move back. Or the standard of living elsewhere will have to rise. The removal of WTO quotas for clothing exports from developing countries is said to spell trouble for ... - no, Bangladesh! Apparently India and China can undercut the Bangla manufacturers. -- Regards, John Woodgate, OOO - Own Opinions Only. The good news is that nothing is compulsory. The bad news is that everything is prohibited. http://www.jmwa.demon.co.uk Also see http://www.isce.org.ukArticle: 76946
I think there was a post a year or two ago about doing an efficient square operation by splitting the number in half such that a N bit square could be done with some N bit lookups and some additions instead of a 2N table lookup. Such that a 10 bit square only required a 10 bit lookup table instead of 20 bit. I think it went something like this: Take a 10 bit number to be squared and represent it as a+32b where a and b are 5 bit numbers. (a+32b)(a+32b) = a^2 + 64ab+1024b^2. Now you have to do 3 of the smaller table lookup mpys and some shifting and adding to get the result.Article: 76947
On Wed, 15 Dec 2004 11:11:26 -0800, Austin Lesea wrote: > "everything except the squeal"? The expression "everything except the squeal" comes from Upton Sinclair's book The Jungle about the Chicago Stockyards. The Jungle caused Congress to pass the 1906 Clean Food and Drug act that created the FDA. > > Now that is pretty graphic. > > > EasyPath(tm) is no different that selling an FPGA that has a laser fuse > blown to replace a defective column of logic. > > Gee, I wonder who does that with every part they sell? > > Get over it: a few bad memory bits (out of 20 million) is not a > "slightly defective" part -- it is >99.99985% perfect. > > Austin I didn't say there was anything wrong with EasyPath it's a good idea. I was just making the point that no chip company is going to throw out a part if there is a way to sell it. EasyPath allow you to sell parts that work with specific bit streams but not with every bit stream. The customer benefits by getting a much lower price at the cost of giving up the flexibility of being able to drop in a different bit stream. The OP was asking about parts that are slower than the slowest speed grade, I was saying if there were any significant number of parts that were failing to meet the lowest speed grade you would simply add a lower grade. It would be bad business to do anything else. The farmstand on my corner does the same thing. At the end of August they sell cases of Tomatoe seconds for $6 a case. The tomatoes are fine for sauces, but they are ugly enough that you don't want to put them in a salad. I buy a case of EasyPath tomatoes every year and use them to make a years supply of spaghetti sauce.Article: 76948
EDA wannabe wrote: > Some colleagues and I were discussing the situation with the high tech > industry, with jobs moving out of North America. This has hit circuit > designers hard, especially those in digital. Can EDA tool development > be expected to follow suit, is has it already happened? If not, what > are the factors that differentiate it from design work to make it less > exportable? Comments are also welcome for automatation of methodologies > for programmable system-on-chip e.g. reconfigurable processor arrays. This has been happening for quite some time now. At first (during the "good times") companies have been moving jobs to India and China because there where not enough engineers available in the US. Than during the recession, companies have been moving/continuing to use India and China because they *appear* to be cheaper than local talent. And I think it is very important to analyze the cost "savings" in greater detail. The truth is that engineers in these developing countries, are less experienced and do not have the needed background of pulling through large projects. As smart as they may be, doing a large project and coordinating some 100 engineers is a tough task. My personal experience with products coming from the developing/low cost countries, is that the quality of workmanship is just not there YET. Many of the "savings" are getting killed because things have to be rewritten/redesigned/fixed/ start over from scratch. Typically the decisions of outsourcing is done by upper management without any feedback from any senior engineers in the US. Managers and engineers are hired in the developing countries with the expectation that they will deliver good of same quality as their US counterparts. So far in my opinion this has not happened (YET !). I believe that in the next 5-10 years we will see the experience level increase and the quality of products to start reaching the same levels as what we would expect form US based engineers. At the same time, I believe, these engineers expectations will be raising as well. As these engineers become more senior and experienced, many of them will have the opportunity to go to the US and get a "high-paying" job. As such the "cost advantage" together with the lower expectation in the US (which will be in my opinion a natural development) will become a wash. Overall I believe we will see a few swings back and forth of this outsourcing "problem" the US is facing. After a while this will become irrelevant as all of the developing countries will become also leaders on the same level as the US. I think if the US does not start attracting new internal engineers by providing more incentives for students, it, as a whole country, will eventually fall behind in the technology sector, which will be led by Japan, China and India (in this order - I believe). I believe this fall back, can already be observed in the automotive industry ... And that, will be by far a much larger problem everybody in the US will face than the outsourcing you see today. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 76949
In article <aqUz8KBGOYwBFw$7@jmwa.demon.co.uk>, John Woodgate <noone@yuk.yuk> wrote: >I read in sci.electronics.design that Phil Tomson <ptkwt@aracnet.com> >wrote (in <cprnfc02h25@enews3.newsguy.com>) about 'Exportability of EDA >industry from North America?', on Thu, 16 Dec 2004: > >>It's not a pretty picture. The standard of living will likely have to >>fall a good bit in the US before you see these kinds of jobs move back. > >Or the standard of living elsewhere will have to rise. True. We'll have to meet in the middle somewhere. This is partly why the dollar is falling (also because of the national debt, of course). The fact remains that the US standard of living will have to fall in this kind of a free-trade system. It's not going to be pretty for the US standard of living to fall that way - it hasn't really happened before. Phil
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