Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Ken wrote:
> The question is to do with the source of the rst signal. Assuming that the
> rst signal pulse comes into the device via a pad, I assume that the
> circuitry external to the FPGA generating the pulse *must* do so
> synchronously to clk?
That's the best way.
Sometimes there is an onboard cpu on the same clock,
and it can toggle reset after loading the fpga from flash.
> Otherwise, if rst is asynchronously
> generated, there must be a chance of the rst pulse transitioning too close
> to a clk edge at the flops and causing metastability?
The problem is a logic race, not metastability.
One way or another, the reset pulse needs to
be synchronized before it gets to the global
reset network on the fpga.
-- Mike Treseler
Article: 78551You could use the clocklock feature to de-skew the clock input to the register.Article: 78552
Ulf Samuelsson wrote: >>If I would make a top list for SPI flash it would look like: >> >>1. SST >>2. ST >>3. Nexflash >> >>best regards >>rick >> >> >>ps: And still no answer given regarding Atmel making EPCS chips >> for Altera (o; >> >> > > > > I certainly have not heard anything about this. > Checked out the different alternative. > > Nexflash is nice due to uniform sector size. All parts seems to have 256 > byte pages. > It makes it easy to do a FAT file system w 512 B sectors. > Fairly low current, both in read (4 mA) and in power down (1 uA) > 64 kB Sector erase time sucks greatly - 2 seconds !!! > Single RAM page in the device, so you have to wait until the device > is ready until you shift in more. > Max size 16 Mbit... > > SST is very quick to program/erase - 70 msa for chip erase. 18 ms for block > erase. > The 4 kB sectors makes the part harder to use, since it becomes hard to > allocate > a block for a single data entity. > Single SRAM page, byte write is nice. 100 years data retention. Is this to > be believed? > 33 Mhz operation is also nice. > Is only useable for 3.0V-3.6V - No mobiles phones ...(Run at 2.8 V) > Anything larger than 8 Mbit? .... > > ST - 8 Mbit > 64 kB Sector erase time is up to 5 seconds (he he he..) Say no MORE... > > Comparing them to the AT45DB642 (which is several years old) > 1056 byte sectors, note: Not 1024: this measn that the extra bytes you > need for handling the flash like CRC, erase count etc are inside the > sector... > > Dual SRAM page, which means that you can load in a page, > start programming the page and while the programming is in progress > you can start loading the next page. > > 4 mA read current, and 2 uA power down current. > 18 ms page programming, but the page size is 4 x Nexflash and > they will need to shift in between every programming cycle, so > in reality, they are quite close. > > 18 ms block erase. This is 8 pages or8 kB, so multiply by 8 > to get 144 ms per 64 kB block. Obviously it is faster, if you are happy > with erasing a block. > > Lacks byte programming unlike SST. > 20 Mhz clock rate is a little low, but it will soon increase to 50 Mhz > and the size will also increase to 128 Mbit. > > I leave it to the reader to draw conclusions. > Okay...finally received Atmel samples of AT25F1024A and AT25F4096. Both are not working as replacement for EPCS configuration for Cyclone FPGA. rickArticle: 78553
hi in the following compile option ---------------------------------------------------------- mb-gcc -O2 TestApp/src/TestApp.c -o TestApp/executable.elf \ -mno-xl-soft-mul -Wl,-T -Wl,TestApp/src/TestAppLinkScr -g -I./mic roblaze_0/include/ -L./microblaze_0/lib/ \ -xl-mode-executable \ ---------------------------------------------------------- Could someone kindly tell me the meaning of two options below -mno-xl-soft-mul and -xl-mode-executable ? any relavant meterials will be also fine thanksArticle: 78554
i had a simular problem with version 5.7 and i solved it removing the file vsim.wlf (located in my working directory) before running modelsim. hope this help. Andrea SabatiniArticle: 78555
We use the 8000 in an old version of our development environment. I need to redesign some part of it put I didn't want to put much more money in it. I guess I'll stick with MAX+PLUSII for this part of the job. Thanks, VinceArticle: 78556
I just tried and it doesn't work I checked up licence file with "diagnose" tool, licence is ok and environment variable is ok too :'( "Andrea Sabatini" <andrea@dapdesign_N_O_S_P_A_M_.com> a écrit dans le message de news: 4202315f$0$28981$e4fe514c@news.xs4all.nl... >i had a simular problem with version 5.7 and i solved it removing the file >vsim.wlf (located in my working directory) before running modelsim. > > hope this help. > > Andrea Sabatini > >Article: 78557
software multiplier spings to mind for the first one and i know nothing.Article: 78558
"Jim George" <jimgeorge_@_gmail.dot.com> wrote in message news:ZLudnZdk283VB5zfRVn-iQ@comcast.com... > Jim George wrote: > > Hi, > > Why is it that you cant put a FDRE and an SRL16E on the same slice? [snip] > John, I can tolerate the delay, I guess. I will be running the design > at 65 MHz. > The reason I cant use either this or John's suggestion of an external > flop is that I want to pack this with as much density as I can (2 bits > per slice). [snip] If you need a common reset for a large number of SRLs - your density desires - you might get by with registering the reset signal and using it for qualification of the SRL flop outputs downstream. If your SRLs feed LUTs rather than other dedicated primitives and you don't use all the inputs to those LUTs, it would be simple to force an "effective" reset on those signals by masking the signals with the registered reset. Retiming. What fun!Article: 78559
Hi, Question: Is there a way I can connect gdb to a remote microblaze target without the use of XDM? The kernel is the xilkernel and the development board is the Memec Insight Virtex2. Do I need to compile in some gdb-stub files, if so, where could they exist? regards, StefArticle: 78560
Hi , I hope somebody else has had the same problem.... I am currenlty migrating some software from an XC3400-4PQ208 to a SPARTAN-3 XC3400-4TQ144. The software and everything is running perfectly in the previous spartan. I have created a new project for the TQ144 and synthesised it without any error. However, when I run the PACE software to assign the pins, the Design Rule Check gives me lots of errors with the same legend "The bank number specified does not exist", It is worth to note that I am not assigning the bank, I am assigning a pin and PACE selects the Bank by itself. The bank for each case is correct though, I have double checked the data sheets and the pins are currently assigned to a correct bank. If I dont pay attention to this errors and try to generate the programming file , the bitgen generates an error without reason. I have tried to disselect the option of "Run Design Rules Checker" under the general options for generate programming files. Then, the bitgen doesn't give any error but I am afraid this is causing my FPGA to be incorrectly programmed since no input/outputs are working... do you have any idea what can i do in this case? My Project Navigator and PACE's versions are 6.01.3i... thank you SergioArticle: 78561
Symon wrote: > p.s. > Hey Kolja, did you look at those resistor packs? Yes I did. I used them in previous projects. The problem with this one are the vias. I can run differential pairs nicely pitch matched from the 0.5mm pitch pqfp to the 1mm bga. Now 0.5mm single in line resistor packs would be graet (Pinout A1-A2-B1-B2-....). But dual in line resistor packs are rather useless unless I can route a signal between the pins. I can't meet a 0.5mm via pitch, so the resistors can not sit at the back . And I can not have the vias on the inside of the PQFP (at least not all of them) because it is almost completely filled with a thermal pad. But I am going to find a way to squeeze in the resistors.... KoljaArticle: 78562
I’m wondering. I wrote the following VHDL-code (this is only an example, not
something usefull):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_test is
Port ( clk : in std_logic;
cnt : out std_logic_vector(7 downto 0));
end counter_test;
architecture Behavioral of counter_test is
signal counter_intern : std_logic_vector (23 downto 0) := (others =>
'0');
begin
process(clk)
begin
if rising_edge(clk) then
counter_intern <= counter_intern + 1;
end if;
end process;
cnt <= counter_intern(7 downto 0);
end Behavioral;
And when I synthesize it I get the following warnings:
WARNING:Xst:1291 - FF/Latch <counter_intern_22> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_23> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_8> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_9> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_10> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_11> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_12> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_13> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_14> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_15> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_16> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_17> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_18> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_19> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_20> is unconnected in block
<counter_test>.
WARNING:Xst:1291 - FF/Latch <counter_intern_21> is unconnected in block
<counter_test>.
Why do I get that when I only want a part of the counter_intern vector?
Article: 78563Hi, My FPGA design is supposed to send out a pattern to a device and then receive that pattern back. So the flow is FPGA -> device-> back to FPGA (Spartan3). Then the FPGA is supposed to compare the sent pattern with the received pattern, and count the number of bits matched. I have successfully coded the FPGA to generate pattern, and a comparison module that will compare the bits and give me a count. But the problem is I want to store this count in a register inside of the FPGA, and then read this register through JTAG back to the PC. Anyone knows how to do this? Can you do this via IMPACT? Thanks. ALArticle: 78564
The Xilinx EDK Embedded System Tools Reference Manual has this info. See page 175 of http://www.xilinx.com/ise/embedded/est_rm.pdf Paul Hur wrote: > > hi > > in the following compile option > > ---------------------------------------------------------- > mb-gcc -O2 TestApp/src/TestApp.c -o TestApp/executable.elf \ > -mno-xl-soft-mul -Wl,-T -Wl,TestApp/src/TestAppLinkScr -g -I./mic > roblaze_0/include/ -L./microblaze_0/lib/ \ > -xl-mode-executable \ > ---------------------------------------------------------- > > Could someone kindly tell me the meaning of two options below > > -mno-xl-soft-mul > > and > > -xl-mode-executable > > ? > > any relavant meterials will be also fine > > thanksArticle: 78565
On Thu, 3 Feb 2005 17:30:40 +0100, "Mr M" <student@telia.se> wrote: >I’m wondering. I wrote the following VHDL-code (this is >only an example, not something usefull): [...] >use IEEE.STD_LOGIC_ARITH.ALL; >use IEEE.STD_LOGIC_UNSIGNED.ALL; Please consider migrating to NUMERIC_STD instead of these old and poorly-standardised packages. >entity counter_test is > Port ( clk : in std_logic; > cnt : out std_logic_vector(7 downto 0)); >end counter_test; So you have an 8-bit output.... >architecture Behavioral of counter_test is > signal counter_intern : std_logic_vector (23 downto 0) > := (others => '0'); and a 24-bit internal counter... >begin [snip standard counter process] > > cnt <= counter_intern(7 downto 0); and you port out only the bottom 8 bits of the counter. >And when I synthesize it I get the following warnings: >WARNING:Xst:1291 - FF/Latch <counter_intern_22> is unconnected in block [etc, etc] >Why do I get that when I only want a part of the counter_intern vector? Because the synthesis tool has correctly detected that you make no use of its upper 16 bits, and has optimised them away. If you had instead picked the TOP eight bits of the counter... cnt <= counter_intern(23 downto 16); then the tool could not optimise away the lower 16 bits and you would not get the messages. Be grateful; the synthesis tool is trying to save you money by fitting your design in a smaller part :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 78566
Chipscope?Article: 78567
>The question is to do with the source of the rst signal. Assuming that the >rst signal pulse comes into the device via a pad, I assume that the >circuitry external to the FPGA generating the pulse *must* do so >synchronously to clk? (clearly if rst is generated on the device >synchronous to clk then no problem). Otherwise, if rst is asynchronously >generated, there must be a chance of the rst pulse transitioning too close >to a clk edge at the flops and causing metastability? Or does this >metastability issue only apply for the D/Q pins on the flop? An additional complication is that the global reset signal that is available on most FPGAs is slow relative to modern clock speeds. So even if it is synchronous at the pad, it may take more than one clock cycle to distribute over the chip. Even if your clocks are slow, there is still the problem of multiple clocks. The normal solution is to make a local copy of the reset signal that is synchronous to your local clock. Say one for each FSM. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 78568
Anyone had any luck with this constraint? I can apply it in VHDL, and XST reports that it has seen and set the constraint: Set property "CLOCK_SIGNAL = yes" for signal <x> in unit <y>. However, further down in the logfile, it reports that the clock signal is generated by combinatorial logic, and it can't identify the primary clock signal. It then suggests using a CLOCK_SIGNAL constraint. This clock is produced by combinatorial logic, and the output of the logic drives a BUFG. I've tried applying the VHDL attribute to both the input and the output of the BUFG, with the same results. Thanks - EvanArticle: 78569
Kolja Sulimma wrote: (snip regarding FPGA based MP3 player) > I would suggest that you rip the decoder algorithm source code from some > open source decode and first try to build a PC software that decodes mp3 > into audio files so that you are sure that everything works as expected > and that you are sure that you understand how to apply the algorithm. This sounds like a good start. In many cases, the appropriate FPGA algorithm is very different than the software algorithm, but that is usually because you want to use more logic to run it faster. With MP3 there isn't much reason to run it faster. > Then I would build a system on a chip in your FPGA with some processor > from www.opencores.org that can run the software decoder. (Some of these > cores should come close to real time decoding allready, but realtime is > not necessary at this step) > When this works you can replace some of the simple bu time consuming > parts of the algorithm by a coprocessor to your CPU to achieve real time > decoding. Or find a faster FPGA based processor. -- glenArticle: 78570
Hi, Part of my project is to read a register content without using Chipscope. If Xilinx software can use JTAG to read back configuration settings, then I think there must be a way to read back a register content through JTAG. Does anyone know? If this involves low level coding, I am willing to try. Thanks, AnnArticle: 78571
> > > > I leave it to the reader to draw conclusions. > > > > Okay...finally received Atmel samples of AT25F1024A and AT25F4096. > Both are not working as replacement for EPCS configuration for Cyclone FPGA. > > > rick If you want o configure FPGAs, then you need to look at the AT17xxxA family. -- Best Regards, Ulf Samuelsson ulf@a-t-m-e-l.com This message is intended to be my own personal view and it may or may not be shared by my employer Atmel Nordic ABArticle: 78572
Ann wrote: > Hi, Part of my project is to read a register content without using Chipscope. If Xilinx software can use JTAG to read back configuration settings, then I think there must be a way to read back a register content through JTAG. Does anyone know? If this involves low level coding, I am willing to try. Thanks, Ann I am taking an educated guess here, but the LUT contents are part of the configuration, so I assume that can be read out via JTAG readback. If so, you can use a LUT as a shift register and you can shift your counter setting into LUTs. If you have time, you can use all 16 bits in the LUTs, but if you need to update the value on each clock, you can just store one bit in each LUT and use N LUTs. Does that help? -- Rick Collins rick.collins@XYarius.com Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design http://www.arius.com 4 King Ave. 301-682-7772 Voice Frederick, MD 21701-3110 GNU tools for the ARM http://www.gnuarm.comArticle: 78573
Hi, the placement of Quartus depends on many factors, changing the fmax-requirement (the PLL-output is used as fmax-requirement automatically for that clock by Quartus) will change the timing-driven-placement and therefore also the timing. You can vary the "Seed"-number in Assignments -> Settings -> Fitter Settings (or -> Compiler Settings -> Fitting in your version) to get other placements, with either better or worse timing. (DSE searches for the best seed automatically). But why do you think that 33.1 MHz is not OK when you need 33MHz? The chip-editor is more stable in newer Quartus-versions, I think. Regards, Thomas www.entner-electronics.com "g. giachella" <giachella.g@laben.it> schrieb im Newsbeitrag news:caea16ca.0502030008.1e44427b@posting.google.com... > Dear all, > I've placed my design in an Altera Stratix and use a PLL for clock > generation. In a first stage PLL generated 22 MHz as output freq and > Quartus II (3.0 release) showed 36 MHz as fmax. Due to this result, I > have decided to increase PLL output to 33 MHz (without any change on > the design). > Now, after placement, Quartus Timing Analyzer shows 33.1 MHz as new > fmax. I've repeated both placements (with a 22MHz PLL and with a 33 > MHz PLL) multiple times and the results are similar. > > Has the PLL configuration any impacts on other parameters which affect > timings ? > > I've also tried a backannotation when going to 33 MHz, but the results > are the same. I can't use Chip Editor, since it crashes. > > Thanks for your help.Article: 78574
You must admit though that the warning message is not very clear.Most compilers at least say something about removing redundant logic.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z