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Messages from 80100

Article: 80100
Subject: pin assignment on an expansion module
From: adrian <adrian.mora@terra.es>
Date: Tue, 01 Mar 2005 18:27:11 GMT
Links: << >>  << T >>  << A >>
Hello there,

I have a Spartan-3 Starter Board with an ethernet module on one of the 
expansion ports and working with EDK 6.3.
My intention is to use the ethernet module on my project to be able to 
send/recieve TCP/IP frames using lwIP but I'm not quite sure how to map 
the pins of the ethernet module to the pins of the expansion port for 
the design to work.
How can this be done correctly?
It might be quite simple but I am quite a newbie on FPGA design so I 
would be very grateful for any help.

Thankyou very much,

Adrian.

Article: 80101
Subject: Re: SR latches in Xilinx devices?
From: Richard Thompson <nospam@nospam.com>
Date: Tue, 01 Mar 2005 18:55:39 +0000
Links: << >>  << T >>  << A >>
On Tue, 01 Mar 2005 10:09:52 -0800, Mike Treseler
<mike_treseler@comcast.net> wrote:

>Richard Thompson wrote:
>
>> Luckily, not an issue here - the standard cross-coupled NAND is
>> already hazard-free (unless the mapper decides to reimplement it,
>> which seems unlikely).
>
>Hazard-free as long as the set and reset pulses
>are well formed and far enough apart in time.
>It's not difficult to make an oscillation
>burst otherwise.

Gabor's comment referred to, presumably, single-variable static
hazards, and the cross-coupled NAND is already covered for this.

Oscillation isn't relevant here, because you can't noramlly solve for
multi-variable dynamic hazards by adding terms. It's not difficult to
make almost any async circuit oscillate by changing more than one
input 'simultaneously'. That's why they're normally designed to allow
only one input to change at a time, and why F/Fs have setup and hold
requirements, for example. An SR latch has similar timing requirements
on its 2 inputs.

Rick

Article: 80102
Subject: Re: FPGA tool benchmarks on Linux systems
From: "Dave Colson" <dscolson@rcn.com>
Date: Tue, 1 Mar 2005 14:13:36 -0500
Links: << >>  << T >>  << A >>
I was told that the benefit of two CPUs is that you can run another
application while simulating and not have your computer slow down
because the other application will run from the other CPU.


"Christian Schneider" <please_reply_to_the@newsgroup.net> wrote in message
news:d02amb$r5a$1@online.de...
>
> Thanks for all the benchmaks! Very interessting information!
>
> If I interpret the data correctly, two CPU result in the same simulation
> time, so they are of no benefit? That's a pity!
>
> BR,
> Chris
>
> Kim Enkovaara wrote:
> > Jason Zheng wrote:
> >
> >> 3. You are comparing state-of-the-art AMD workstations with mediocre
> >> Intel servers. It's like comparing oranges with apples.
> >
> >
> > I have some measurements with more current Xeon processors.
Unfortunately
> > I had only one not so state of the art Opteron to measure.
> >
> > These results were published by me in one local Mentor Graphics
conference
> > (these are only small part of the numbers). The simulations are done
with
> > Modelsim for a ~8Mgate chip (+all memories). The numbers are simulation
> > time
> > in seconds.
> >
> >
> >     RTL One CPU active
> > Sun V880 UIII/900        3531
> > P4 Xeon 2.2/512k        2224
> > P4 Xeon 2.4/512k        2087
> > P4 Xeon 2.8/512k        1928
> > P4 Xeon 3.06/512k        1634
> > P4 Xeon 3.4EMT (32b)        1239
> > AMD Opteron 848(32b)        1584
> >
> >     RTL Both CPUs active
> > Sun V880 UIII/900        3520
> > P4 Xeon 2.2            2540
> > P4 Xeon 2.4            2680
> > P4 Xeon 2.8            2650
> > P4 Xeon 3.06            2120
> > P4 Xeon 3.4EMT (32bit)        1450
> > AMD Opteron 848(32b)        1587
> >
> > One thing that amazes me is that in Xeons even with RTL simulation the
> > performance
> > degrades very guickly. I guess with 4 processors Xeons degrade very
> > badly. In
> > Opterons there was no degradation to be seen.
> >
> > For the gate level simulations the results are almost identical, altough

> > the dataset
> > is 15-20x larger and simulation times for the same case are longer. Also
> > if 64b mode
> > was used Opteron became faster and Xeon EMT was little slower (very
> > small differences
> > compared to 32b mode tough).
> >
> >
> > --Kim



Article: 80103
Subject: Re: pin assignment on an expansion module
From: hmurray@suespammers.org (Hal Murray)
Date: Tue, 01 Mar 2005 13:15:07 -0600
Links: << >>  << T >>  << A >>
>I have a Spartan-3 Starter Board with an ethernet module on one of the 
>expansion ports and working with EDK 6.3.
>My intention is to use the ethernet module on my project to be able to 
>send/recieve TCP/IP frames using lwIP but I'm not quite sure how to map 
>the pins of the ethernet module to the pins of the expansion port for 
>the design to work.
>How can this be done correctly?
>It might be quite simple but I am quite a newbie on FPGA design so I 
>would be very grateful for any help.

Get the schematics for both boards and the data sheet for the
big chip on the Ethernet card.  Pick some interesting pin
on the big chip and follow it over to the connector.  Find
the corresponding pin on the other connector and trace it back
to the FPGA.

If you are lucky, you can find some documentation that does
that for you.

Beware, it's far from uncommon to get pin numbers scrambled
on connectors.  For example, pins will be numberd 1-40 on one
connector, but the corresponding pins will be numbered 40-1,
or 2,1,4,3, ...  Or 1,3,5...  An ohmmeter may help you trace
wires, or verify that you have things correct.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 80104
Subject: Re: FPGA interface to an asynchronous microcontroller memory bus
From: "Pablo Bleyer Kocik" <pablobleyer@hotmail.com>
Date: 1 Mar 2005 11:40:52 -0800
Links: << >>  << T >>  << A >>
Christian Schneider wrote:
> Wow! You use REAL Latches. I never dared to used them. If it works
> stable, my are sure of my deep repect.
>
> I would have doubled (or quadroupled) the 24 MHz clock and
synchonized
> the write signal.
>
> Cheers,
> Chris

 You bet. And for really critical applications (ie potentially lethal
for living beings), *I even don't trust clocks*. Synch or asynch, I end
up implementing smart, redundant, buffer-isolated interfaces with
internal consistency checks in case something goes mad. There are
horror stories even at sub-MHz frequencies!

 The horror... The horror...

--                /"Horror and moral terror are your friends.
PabloBleyerKocik / If they are not then they are enemies to
 pbleyer        / be feared. They are truly enemies."
  @embedded.cl / - Colonel Walter E. Kurtz, Apocalypse Now (1979)


Article: 80105
Subject: Re: FPGA tool benchmarks on Linux systems
From: Christian Schneider <please_reply_to_the@newsgroup.net>
Date: Tue, 01 Mar 2005 20:49:14 +0100
Links: << >>  << T >>  << A >>
Dave Colson wrote:
> I was told that the benefit of two CPUs is that you can run another
> application while simulating and not have your computer slow down
> because the other application will run from the other CPU.

ACK. But it would have been nice to see multithreaded simulations, which 
benefit from more CPUs. Especially since simulations are parallelizable 
and some vendors support clusters. So I think that this is just a small 
step ... which is not done yet. And the dual core CPUs are ante portas ...

BR,
Chris

> 
> "Christian Schneider" <please_reply_to_the@newsgroup.net> wrote in message
> news:d02amb$r5a$1@online.de...
> 
>>Thanks for all the benchmaks! Very interessting information!
>>
>>If I interpret the data correctly, two CPU result in the same simulation
>>time, so they are of no benefit? That's a pity!
>>
>>BR,
>>Chris
>>
>>Kim Enkovaara wrote:
>>
>>>Jason Zheng wrote:
>>>
>>>
>>>>3. You are comparing state-of-the-art AMD workstations with mediocre
>>>>Intel servers. It's like comparing oranges with apples.
>>>
>>>
>>>I have some measurements with more current Xeon processors.
> 
> Unfortunately
> 
>>>I had only one not so state of the art Opteron to measure.
>>>
>>>These results were published by me in one local Mentor Graphics
> 
> conference
> 
>>>(these are only small part of the numbers). The simulations are done
> 
> with
> 
>>>Modelsim for a ~8Mgate chip (+all memories). The numbers are simulation
>>>time
>>>in seconds.
>>>
>>>
>>>    RTL One CPU active
>>>Sun V880 UIII/900        3531
>>>P4 Xeon 2.2/512k        2224
>>>P4 Xeon 2.4/512k        2087
>>>P4 Xeon 2.8/512k        1928
>>>P4 Xeon 3.06/512k        1634
>>>P4 Xeon 3.4EMT (32b)        1239
>>>AMD Opteron 848(32b)        1584
>>>
>>>    RTL Both CPUs active
>>>Sun V880 UIII/900        3520
>>>P4 Xeon 2.2            2540
>>>P4 Xeon 2.4            2680
>>>P4 Xeon 2.8            2650
>>>P4 Xeon 3.06            2120
>>>P4 Xeon 3.4EMT (32bit)        1450
>>>AMD Opteron 848(32b)        1587
>>>
>>>One thing that amazes me is that in Xeons even with RTL simulation the
>>>performance
>>>degrades very guickly. I guess with 4 processors Xeons degrade very
>>>badly. In
>>>Opterons there was no degradation to be seen.
>>>
>>>For the gate level simulations the results are almost identical, altough
> 
> 
>>>the dataset
>>>is 15-20x larger and simulation times for the same case are longer. Also
>>>if 64b mode
>>>was used Opteron became faster and Xeon EMT was little slower (very
>>>small differences
>>>compared to 32b mode tough).
>>>
>>>
>>>--Kim
> 
> 
> 

Article: 80106
Subject: Re: FPGA tool benchmarks on Linux systems
From: Jason Zheng <xin.zheng@jpl.nasa.gov>
Date: Tue, 01 Mar 2005 11:49:57 -0800
Links: << >>  << T >>  << A >>
Dave Colson wrote:
> I was told that the benefit of two CPUs is that you can run another
> application while simulating and not have your computer slow down
> because the other application will run from the other CPU.
> 
> 
That depends on the process scheduler in the kernel. The most 
significant benefit is that your multi-threaded application such as HDL 
simulator can run multiple threads at the same time. For example the 
following verilog structure lends itself to multi-threading:

fork
    begin
       ...
    end
    begin
       ...
    end
join

Now whether that piece of code is actually run as two threads is up to 
the HDL compiler's design. It might just run as a single thread. Even if 
it were as two threads, the kernel might decide that another process is 
important and only give one cpu to the hdl simulator.

The real advantage of the AMD cpu is that each cpu has its own memory 
interface, and a high-bandwidth link to each other. Intel cpus have a 
different architecture, where all cpus share the same memory interface. 
AMD's design is more scalable: adding cpus to the mainboard only 
slightly affects the memory bandwidth each cpu receives, whereas Intel 
cpus will get much less memory bandwidth as the number of cpu goes up. 
Although the memory bandwidth can be improved with higher FSB frquency 
(1066MHz now) and larger L2 (2MB now) and L3 cache (8MB-16MB?), the 
Intel approach does not scale. This is why AMD Opetron can easily have 
8-way configuration and you rarely even see quad Xeon.

-jz

Article: 80107
Subject: Re: Problem with LXT970A
From: Jeremy Stringer <jeremy@_NOSPAM_endace.com>
Date: Wed, 02 Mar 2005 09:09:58 +1300
Links: << >>  << T >>  << A >>
Eug wrote:
> At power on autonegotiation switches to 10 Mbps 
> while I have 100 Mbps hub and 100 Mbps Ethernet 
> at PC. At 10 Mbps all is OK. But when I force 
> chip to work in 100 Mbps mode I get RX_CLK low. 
> All LEDs are off except "100 Mbps" inspite of 
> intensive traffic. No data can be sent to the 
> network and no data can be received.

Just a silly question - is it in fact a 10Mb only hub?  This would be 
completely consistant.

Jeremy

Article: 80108
Subject: Examples with GEMAC and ML300 board?
From: nweaver@soda.csua.berkeley.edu (Nicholas Weaver)
Date: Tue, 1 Mar 2005 20:52:06 +0000 (UTC)
Links: << >>  << T >>  << A >>
I haven't gone digging through all the ML300 examples which ship with
the board recently, but I seem to recall this was from the time when
the Xilinx GMAC used an integrated PCS/PMA unit, rather than the
current standalone GEMAC and PCM/PMA separation.

Does anyone have a trivial example design using these cores to drive
the MGTs on the ML300 board?

Thanks.
-- 
Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu

Article: 80109
Subject: Re: FPGA tool benchmarks on Linux systems
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Tue, 01 Mar 2005 16:40:52 -0500
Links: << >>  << T >>  << A >>
On Tue, 01 Mar 2005 11:49:57 -0800, Jason Zheng wrote:

> Dave Colson wrote:
>> I was told that the benefit of two CPUs is that you can run another
>> application while simulating and not have your computer slow down
>> because the other application will run from the other CPU.
>> 
>> 
> That depends on the process scheduler in the kernel. The most 
> significant benefit is that your multi-threaded application such as HDL 
> simulator can run multiple threads at the same time. For example the 
> following verilog structure lends itself to multi-threading:
> 

Parallel simulators are apparently a much harder problem then you might
suspect. A number of years ago I was discussing this issue with the CTO of
IKOS (since bought by Mentor). To me it seemed that simulation should be
a highly parallel problem but he claimed that there had be a number of
attempts at parallel software simulators (as opposed to hardware
acceleration engines) and that no one had succeeded. With the advent of
multi-core processors this year I suspect that the issue will be
revisited. In the mean time a dual processor machine is useful for running
multiple simultaneous simulations, like regression suites, assuming that
you have more than one license.


Article: 80110
Subject: Re: RocketIO, where to start?
From: nigelg <nigel.gulstone@xilinx.com>
Date: Tue, 01 Mar 2005 13:41:38 -0800
Links: << >>  << T >>  << A >>
The first Aurora code for Virtex 4 will be available in the first 
IPUpdate for ISE 7.1. You might also try talking to a Xilinx FAE in your 
area, since they can sometimes set you up with early access material.

Regards,
Nigel

MM wrote:
> Hi Nigel,
> 
> Thanks for your help. When is the Aurora module going to be available for
> the V4 FX series? I know that even V4 MGBT user manual has not been released
> yet...
> 
> 
> /Mikhail
> 
> 

Article: 80111
Subject: Re: FPGA tool benchmarks on Linux systems
From: "Thomas Entner" <aon.912710880@aon.at>
Date: Tue, 1 Mar 2005 22:51:07 +0100
Links: << >>  << T >>  << A >>
I think we should all encourage the FPGA- and EDA-tool-vendors to adapt 
there software for parallel algorithms (especially place and route), as the 
dual-cores are really coming soon and most of us will buy the fastest 
machine they can get for reasonable money. In fact, a parallel algorithm 
would already help a little bit today for P4s with hyper-threading.

Regards,

Thomas

www.entner-electronics.com

"B. Joshua Rosen" <bjrosen@polybus.com> schrieb im Newsbeitrag 
news:pan.2005.03.01.21.40.50.480146@polybus.com...
> On Tue, 01 Mar 2005 11:49:57 -0800, Jason Zheng wrote:
>
>> Dave Colson wrote:
>>> I was told that the benefit of two CPUs is that you can run another
>>> application while simulating and not have your computer slow down
>>> because the other application will run from the other CPU.
>>>
>>>
>> That depends on the process scheduler in the kernel. The most
>> significant benefit is that your multi-threaded application such as HDL
>> simulator can run multiple threads at the same time. For example the
>> following verilog structure lends itself to multi-threading:
>>
>
> Parallel simulators are apparently a much harder problem then you might
> suspect. A number of years ago I was discussing this issue with the CTO of
> IKOS (since bought by Mentor). To me it seemed that simulation should be
> a highly parallel problem but he claimed that there had be a number of
> attempts at parallel software simulators (as opposed to hardware
> acceleration engines) and that no one had succeeded. With the advent of
> multi-core processors this year I suspect that the issue will be
> revisited. In the mean time a dual processor machine is useful for running
> multiple simultaneous simulations, like regression suites, assuming that
> you have more than one license.
> 



Article: 80112
Subject: Part of a ranged signal
From: "KCL" <kclo4_NO_SPAM_@free.fr>
Date: Tue, 1 Mar 2005 23:25:53 +0100
Links: << >>  << T >>  << A >>
Hi,

I want to declare signal using range 0 to A
and then only to take some MSB of this signal how can I do??

at the start my code was

generic(
        B: integer
)
.....
signal temp (B downto 0);
signal temp2(B-3 downto 0);
....
temp2<= temp(B downto 3);

and now I want that temp and temp2 to be ranged signal so I do

generic(
        A: integer
)
.....
signal temp (range 0 to A);
signal temp2(range 0 to A/8);
....
temp2<= temp(B downto 3); -- this is this part that I doesn't know how to 
replace

does anyone know how to do??

Thanks

Alexis.



Article: 80113
Subject: Re: FPGA tool benchmarks on Linux systems
From: Jason Zheng <xin.zheng@jpl.nasa.gov>
Date: Tue, 01 Mar 2005 14:40:00 -0800
Links: << >>  << T >>  << A >>
Place-n-route can already be done in pseudo-parallel fashion with 
xilinx's modular design. You can simply run two processes that each par 
a part of the design, and maybe even write a script to automate that 
process. Dual-core P4 and AMD64 should have no problems doing that sort 
of things.

Of course, you can't do that for all EDA tools as you will soon run into 
licensing problems.

-jz

Thomas Entner wrote:
> I think we should all encourage the FPGA- and EDA-tool-vendors to adapt 
> there software for parallel algorithms (especially place and route), as the 
> dual-cores are really coming soon and most of us will buy the fastest 
> machine they can get for reasonable money. In fact, a parallel algorithm 
> would already help a little bit today for P4s with hyper-threading.
> 
> Regards,
> 
> Thomas

Article: 80114
Subject: Re: RocketIO, where to start?
From: "MM" <mbmsv@yahoo.com>
Date: Tue, 1 Mar 2005 17:48:09 -0500
Links: << >>  << T >>  << A >>
On a different topic, what kind of error rate can I expect at 2.24 GB/s? Two
FPGAs I am connecting with this link are on 2 separate PCBs (so called front
and rear Compact PCI cards). The cards are connected with a 2mm Hard Metric
"pass-through" connector. In other words there is a backplane or rather
midplane between the cards, but there are no tracks, the signals pass
directly through the vertical male connector pins sticking out on both sides
of the plane, while each of the cards has a right angle female connector.

My problem is that I can't really have any errors at all... If that is not
achieavable with RocketIO at the data rate I am interested in, then I guess
I should look at other options. I noticed that there is a slower core in the
Coregen, called High-Speed Data Serialization and Deserialization. I guess I
could use 4 of them, one per each of the bytes in my packet and run them at
560 MHz. Would this be more reliable?



Thanks,
/Mikhail



Article: 80115
Subject: Re: SR latches in Xilinx devices?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 1 Mar 2005 23:57:21 +0100
Links: << >>  << T >>  << A >>

"Mike Treseler" <mike_treseler@comcast.net> schrieb im Newsbeitrag
news:38jpfiF5ou9etU1@individual.net...

> Hazard-free as long as the set and reset pulses
> are well formed and far enough apart in time.
> It's not difficult to make an oscillation
> burst otherwise.

After all, what is a RS-FF good for nowadays??

Regards
Falk




Article: 80116
Subject: Re: FPGA interface to an asynchronous microcontroller memory bus
From: Laurent Pinchart <laurent.pinchart@skynet.be>
Date: Wed, 02 Mar 2005 00:04:08 +0100
Links: << >>  << T >>  << A >>
> I don't know what peripheral  you want to implement, but for  an address
> latch / decoder an FPGA sounds like an overkill.
> Spartan-II is not expensive, but consider the power supply and sereal
> EEPROM etc.
> A CPLD may be a simplier solution. Say 9572?

There are a few reasons why I choosed the Spartan-II. First, I need several
counters, a peripheral interrupt controller, a PWM signal generator and
possibly other things. All that wouldn't have fitted in a CPLD.

The second reason is that I have several in stock :-)

Laurent Pinchart


Article: 80117
Subject: Re: Part of a ranged signal
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 01 Mar 2005 15:13:16 -0800
Links: << >>  << T >>  << A >>
KCL wrote:

> signal temp (range 0 to A);
> signal temp2(range 0 to A/8);
> ....
> temp2<= temp(B downto 3); -- this is this part that I doesn't know how to 
> replace

Converting from a TO vector to a DOWNTO vector
is trickier than you might expect. See:
http://groups-beta.google.com/groups?q=vhdl+reverse_bits

Also consider concatenating small vectors to
make big ones instead of slicing.

     big_vec_s <= vec_a & vec_b & vec_c;

       -- Mike Treseler

Article: 80118
Subject: Re: FPGA interface to an asynchronous microcontroller memory bus
From: Laurent Pinchart <laurent.pinchart@skynet.be>
Date: Wed, 02 Mar 2005 00:17:31 +0100
Links: << >>  << T >>  << A >>
> Wow! You use REAL Latches. I never dared to used them. If it works
> stable, my are sure of my deep repect.
> 
> I would have doubled (or quadroupled) the 24 MHz clock and synchonized
> the write signal.

I thought about doubling the clock as well for the same reason. How
safe/unsafe is a real latch in a Spartan-II ? What should I know about it ?

Laurent Pinchart


Article: 80119
Subject: Re: FPGA interface to an asynchronous microcontroller memory bus
From: Laurent Pinchart <laurent.pinchart@skynet.be>
Date: Wed, 02 Mar 2005 00:34:32 +0100
Links: << >>  << T >>  << A >>
> Can't you run the MCU form a clock drived from the FPGA one - that way
> they won't be asynchronous.

No I can't. The datasheet states that the MCU internal clock is delayed by
an unknown amount, so even if I could get it to work, there would be no
guarantee, and the risk is too high.

Laurent Pinchart


Article: 80120
Subject: Re: FPGA interface to an asynchronous microcontroller memory bus
From: Laurent Pinchart <laurent.pinchart@skynet.be>
Date: Wed, 02 Mar 2005 00:46:35 +0100
Links: << >>  << T >>  << A >>
> We handle this situation in this way.
> NO oversampling. Since there is no need to do so.
> A read acces to a register inside the FPGA is plain combinatorical, no
> problem here.
> A write access to a register is defacto a clocked process, so we use WR as
> a clock (on a global clock net) to load data into FPGA registers.

> For an address latch its similar, use ALE to clock the address into the
> latch/register. Here you dont need to wast a global clock net, local
> routing (low skew lines) do fine, since the latch is small (just a
> handfull of flipflops)

Ok, that's nice, will save a global clock net.

>> The FPGA will do many things in parallel. One of the things it will do
>> is a latch that's clocked by the appropriate edge from the AVR that is
>> independent of any logic that's changed by the FPGA's clock. After the
>> data is latched, it will set a "new data available" flag that's handled
>> by the FPGA's clocked logic.
> 
> The right way to go. Dont forget to synchronize the flag using the classic
> 1/2 flipflop synchronizer.

Forgive my ignorance, but where can I find documentation about that ? Is at
a half flipflop or a 1-or-2 fliflop ? :-)

I also would appreciate pointers to some good FPGA design tutorial. I can
find VHDL tutorials all over the net, but they only cover the basics, not
the design methodology. I haven't been able to find a good book about it.

Laurent Pinchart


Article: 80121
Subject: Resetting Virtex II BlockRAM
From: Sudhir.Singh@email.com
Date: 1 Mar 2005 15:46:59 -0800
Links: << >>  << T >>  << A >>
Hi Group,
I am implementing a multichannel IIR filter on Virtex II fpga and the
filter memory is implemented using the BlockRAM. Is there a way to
reset all memory contents to 0, without having to sequentially write
0's into the RAM.

Thanks in advance.
Sudhir


Article: 80122
Subject: Re: Memory or registers and JTAG
From: "Pablo Bleyer Kocik" <pablobleyer@hotmail.com>
Date: 1 Mar 2005 16:06:31 -0800
Links: << >>  << T >>  << A >>

AL wrote:
> Hi, I read a lot of stuffs on JTAG and SVF file, but I still can't
figure out how to read back multiple memory spaces or multiple
registers via JTAG. I used BSCAN_SPARTAN3 and USER1 Register, but that
only allows you to read back one register. I need to read back at least
10 registers or memory spaces via JTAG. Is it possible to do this at
all? Thanks, AL

 They don't call them 'chains' for no reason. Your 'register' is really
the chain of all the registers you want to shift in/out, or you can
connect a register mux to one user chain and control the mux select
signal using the other. You will have to serialize in and out your
registers from the SVF bitstream or add the selection commands to the
SVF process (depends on the capabilities of your SVF tool).

 Cheers.

--
PabloBleyerKocik /"Mama said to get things done
 pbleyer        / you better not mess with major Tom"
  @embedded.cl / -- Ashes to ashes, David Bowie


Article: 80123
Subject: Re: Resetting Virtex II BlockRAM
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Tue, 01 Mar 2005 17:08:25 -0700
Links: << >>  << T >>  << A >>
Sudhir.Singh@email.com wrote:
> Hi Group,
> I am implementing a multichannel IIR filter on Virtex II fpga and the
> filter memory is implemented using the BlockRAM. Is there a way to
> reset all memory contents to 0, without having to sequentially write
> 0's into the RAM.
> 
> Thanks in advance.
> Sudhir
> 
No.

Article: 80124
Subject: Help with XST warnings (2)
From: "morpheus" <saurster@gmail.com>
Date: 1 Mar 2005 16:21:13 -0800
Links: << >>  << T >>  << A >>
Can anybosy help me with these warnings? I tried looking at XILINX
answers database and found no record of them.
Moreover, I found out that by modifying the environment variable, these
warnings can be turned off....but i'm kinda skeptical as i dont know if
these are major show-stoppers or not

WARNING:Xst:1710 - FF/Latch  <seriesiii_chan1_reg_2> (without init
value) is constant in block <t1>.
WARNING:Xst:1290 - Hierarchical block <c1> is unconnected in block
<t1>.

Thanks
MORPHEUS




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