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hi, I'm having trouble initializing some memory in a verilog include file. If I do the following : BRAM16_S9 memory ( ... ); // synthesis attribute init_00 of memory is "...." Everything works fine. However, I really want to have the memory initialization done in an include file (because it is generated), like such: BRAM16_S9 memory ( ... ); `include "init.v" (with the init.v file containing the // synthesis attribute ...). But then I get an error from XST: Cannot find <memory> in module <Unknown Module> Is there a way to make this work ? ArletArticle: 80426
I am looking for some ideas on doing a final project for my course using spartan 3 board. I am currently doing a simple RISC processor project using this board.It has a few instructions that it needs to support. So i am looking for something a bit more difficult than the one i am doing right now. Any suggestions or pointers please?Article: 80427
Folks I am trying to write and read from an address location of the ISSI SRAM on the spartan 3 board. Basuically i tried to write a state machine that represented the timing diagram of the read and write cycle of the SRAM. Does anyone know of a simple way to try writing an 8-bit data to a location and reading it back using the spartan 3 board? thanks in advanceArticle: 80428
Brian, I think the best thing to do here is to agree to disagree on some of the points, and realize that we are in agreement on most of the rest. C isn't the whole story. We have more tests to do yet. The story about packaging (HJ) was limited to inductance of the loops formed by signals, power, and ground. dV/dt can be a problem. Cin can be a problem. Cin can be an insurmountable problem if the rate is high, the termination is external. Standards written for ASSP's and ASIC's are often not met by FPGAs (to every dotted 'i', and crossed 't'). That does not mean that we do not get used in all of the standards. It just means we have to show how these small differences either can be dealt with, or don't limit the performance of the standards in question. You have stated that you would use our parts if we had segregated the IO banks (and reduced the Cin), and you have stated that losing DCI would not be a factor in your use. Thank you for your marketing input. It turns out that DCI uses the existing output transistors, so its loss would reduce Cin by about 10% or less. It would speed up (lower the delay) through the IOB, however. Virtex E did not have a true LVDS driver (used an external R network with single ended drivers). As for the rest, I'll let it go for now, and come back later with data. Austin Brian Davis wrote: > Austin, > >>> Looking at the output waveforms shown in figure 20, my first >>>reaction was that it clearly showed that Xilinx hasn't done >>>much to improve their I/O cell capacitance [1] since V2. >> >>Why should we do that? >> > > > Because 10 pF and 1 Gbps are a poor match. > > >>What is it about the Cout that is such a big deal? >> > > > Note that I used "I/O cell capacitance" in my post as I > attempted to point out the impact on both inputs and outputs. > > However, as the only parameter given in the V4 datasheets is > called Cin, I wasn't consistent in that name usage. > > Hereafter I shall attempt to use C to refer to the I/O > structure capacitance, as applies to both inputs & outputs. > > >>Driving the pcb trace, and the load at the other end swamps >>the intrinsic C of the pin in almost all cases. >> > > > Not in my experience, particularly when dealing with > connections from 'real' 1 Gbps logic <-> FPGA > > >>To do what we do (which is more than the competitor), we >>need the silicon area. Silicon area = C. >> > > > My heretical $0.02: > > DCI = not worth the penalty of excess C > > So ditch DCI, keep the DT terminators, and invent a controlled > slew driver with low C for the LVCMOS-ish standards. > > >>> Meanwhile, the marketeering data rate has gone from >>>"840 Mbps" for V2 to "1 Gbps" for V4. >> >>Sure has. Works great. Eye diagrams look fantastic (on a real > > board). > > > Where in Xilinx's V4 documentation might one find these pictures > and eye diagrams, including real world vs. simulated waveforms at > the driver, receiver, and points in between ? > > >>> Perhaps Dr. Johnson could proffer his honest opinion of >>>a "1 Gbps" LVDS receiver with a Cin of 10 pF [2]. >> >>I am sure he wioll answer that if asked in a fair and impartial way. >> > > > Those 1 Gbps and 10 pF numbers are straight from Xilinx's own > V4 datasheet- I don't see how you can claim any partiality on > my part for merely pointing out your own numbers. > > >>Perhaps he will also point out that there is a lot more to the >>IO performance than just C? >> > > When have I ever claimed that it is the only factor? > > Particularly in a post where my lead-in paragraph ended with > the phrase "... which is not the whole story for high speed I/O." > > >>> While the reduced output slew rate due to capacitive loading >>>may be of marginal "benefit" for low speed I/O standards, >> >>Ho ho ho. That is funny. Take the problem of slew rate out of > > control, > >>and try to case our C as BAD because it slows us down SO WE WORK? Ha > > ha > >>ha. I am rolling on the floor. Be serious. The C is what it is. It > > >>does not limit performance in any way. >> > > ROTFL right back at ya > > >>If all the power is in the pin C, perhaps you will see a 30% >>improvement. Again, we may be talking less than 6 milliwatts per pin. > > >>Big advantage when the S2 won't work in a system. >> >>Oh my, my 72 pin bus switching at 200 MHz with 2.5V has ~430 mW more >>power than an S2......but it WORKS! >> > > I suggested this test as a quick way of verifying Altera's > claims of improved C - given 500 switching outputs, a few > points along the power vs switching rate curve should give us > something to ponder. > > I never said anything about what percentage of device power > this would represent. > > BTW, how many of those 500 outputs connect to PCB traces, how > many only to a BGA solder pad? > > >>Excuse me, the waveforms look fine. Excessive rise and fall >>times don't buy you anything but misery. HJ just proved that. >> > > Dr. J demonstrated that Xilinx's package is better. > > He did not address the issue of whether the I/O capacitance > of the V4 was amenable to 1 Gbps operation. > > "Too Fast For the Package" is bad. > "Just Fast Enough" is great. > "Can't get out of my own way due to high C" is also bad. > > As these are general purpose I/O, the case of multidrop > as well as point-point needs to be considered, along > with non-FPGA 1 Gbps drivers. > > > >>>C) Differential output switching would mitigate the SSO package >>> effects somewhat as compared to single ended switching at >>> the same rate >> >>Yes, the C is half differentially. >> > > > There's more to this one than just output C ( balanced > driver ICCO; some degree of agressor cancellation ). > > If you can repeat Figure 19 with 250 LVDS/LDT type pairs > ( or as many as you can fit into both devices ), that would > be an interesting comparison. > > >>>D) input reflections would be worse for the Xilinx part >>> >> >>Yes. But, since our termination is internal, and the driver is >>terminated, it doesn't matter. >> >>Do the simulation, the eye the receiver sees is just fine. >>Reflected signal (small) is absorbed by the transmitter, and >>does not cause distortion in the receiver. >> > > ROTFL yet again > > I'll note here that, unlike the current V2/V4 material, the > old Virtex-E LVDS application notes actually addressed the issues > of C, reflections, and multidrop configurations, with waveforms > plotted at points other than only the receiver of a point-point > connection. > > >>You are not correct in assuming bad SI always results from pin C. >> > > > When, and where, have I EVER said that pin C is the ONLY source > of SI problems? > > >>If you terminate externally, I would agree with you. >> > > BTW, thanks to Xilinx for putting those DT terminators back > into the S3E parts. > > >>We'll keep that in mind if we ever get to where we have to do >>this to meet all specs and standards. SO far, we do >> > > > Long ago and far away, when discussing this for V2, I wrote: > > Although the original LVDS specification did not directly > specify a max Cin value, newer specifications such as > HyperTransport do; for example, HyperTransport requires a > maximum 2pf (single-ended) Cin for receivers rated > 800 Mbps. > > and also: > > See for instance Table 13, footnote 1 of XAPP622, which > clearly states that, although tested interoperable, the > V2 devices do not meet the rise/fall requirements of the > SFI-4 specification > > > >>>[2] I'd be happy to quote a Cdiff instead, if someone could tell >>> me where it is documented. >>> >>> Ideally, the differential input model would include both >>> the single ended shunt Cin values as well as a differential >>> across-the-pair Cdiff, so I could model both the differential >>> and common mode reflections. >>> >>> If Cdiff is negligible, and the input waveform is purely >>> differential, then Cdiff = 1/2 Cin, as Austin has argued before. >> >>Uh, last I looked at circuit theory, it is still C/2 for the diff > > pair. > >>It also agrees with simulations (if you instantiate the V4 receiver, >>and compare it to a circuit model of the same thing). >> > > > I'm not sure exactly what you're disagreeing with here. > > I was attempting to point out that real differential > input buffers have a mix of both "shunt to plane" and > "shunt across the pair" C, the values of each I'd like > to see documented separately for modeling purposes. > > Perhaps I should have said "effective Cdiff = 1/2 Cin" > in my last sentence about the special case? > > Brian >Article: 80429
Michel Billaud wrote:
> It seems to be a trivial case of the difficult "state assignment
> problem" but i must admit i'm to lazy to read the 199 pages of
> http://alexandria.tue.nl/extra2/200413270.pdf now :-/)
The state assignment "problem" is an academic one.
The average fpga controller, say (idle, start, cook, stop)
has not many states to begin with and playing
with assignments makes very little difference for utilization.
> There are 2 very simple situations in FSM
> 1. n-step cycle S1 -> S2 -> Sn -> S1 -> S2 -> ....
> 2. n-step, last is a sink : S1 -> S2 -> Sn -> Sn -> Sn -> Sn ...
> that can be easily implemented with counters, binary, gray code,
> whatever.
Yes, those are counters and are better described
with an n:= n + 1; than a circle and arrow for each count value.
I expect that any counter you come up with
will fit your device.
-- Mike Treseler
Article: 80430fpgawizz wrote: > > I am looking for some ideas on doing a final project for my course using > spartan 3 board. I am currently doing a simple RISC processor project > using this board.It has a few instructions that it needs to support. > > So i am looking for something a bit more difficult than the one i am > doing > right now. > Any suggestions or pointers please? A full featured 32bit soft processor with SIMD,cache,mmu ... complete with a gnu toolchain and linux 2.6 support out of the box. With a nice Java application to fit peripherals around the core etc (like what the EDK does). Preferably that fits in a XC3S50. could be named YAFSP (Yet Another FPGA Soft Processor) SylvainArticle: 80431
I should read data from a 32bit register (where another process write datas into) and every time it changes, copy data into ram. In what way may I understand when register changes? If I create a process which is clock sensitive, it writes in ram lots of times? MarcoArticle: 80432
The only way to find out whether data has changed, is to compare the old data with the new data. Write data into a 2-deep, 32-bit parallel shift register, and perform identity comparison betweenthe two data vlues. When different, write the new content into your RAM. You might also write everything into the RAM all the time, but increment the RAM address only when you detected new data with the above mentioned comparator. In Virtex BlockRAM, the write port has a read output that-as a configuration option- shows the content before the writing. That eliminates the need for one 32-bit register, but you always need the comparator. You must also watch out for the usual problems when you cross clock domains. Peter Alfke, Xilinx ApplicationsArticle: 80433
<Huianx> wrote in message news:42286153$0$31619$afc38c87@news.optusnet.com.au... >I am new to the FPGA and I want to learn by small experiments. > > Can some FPGA experts tell me what is the easiest and least expensive way > of getting started ? http://www.howell1964.freeserve.co.uk/logic/burched/fpga_devkit_b5.htm Very competitive price. Looks the cheapest, and is the most versatile because it doesn't give you features you might not want. Individual projects tend to have their own requirements, so you build those bits yourself. Some things tend to crop up often, and you can buy those ready-made as required. (RAM, IDE, CF, KBD, MSE, DACs, VGA, buzzer etc).Article: 80434
I am using the spartan 3 and want to read in data from the hyperterminal. I wanted to know if someone had or could show me an example of how to do this. thanksArticle: 80435
reachranbir@gmail.com wrote: > Hi, > this is ranbir here. my client is plannin to build complex SoC for > their CDMA based mobile handsets. their design centre will be based in > Bangalore, India. > > they are looking for an entire team for that purpose. we want frontend > design engineer, backend, physical design, verification, memory design, > rtl architects and everyting else. > > anybody from any nationlity are welcome to apply. > > Anybody interested??Article: 80436
Many Thanks. I'll configure the block ram with data out before writing. What problems about clock are you mentioning? Delay propagation? Or others?Article: 80437
Hi Ranbir,
when is it going to start. I am prently starting my thesis in
Thales Electronic Engg Gmbh, Duesseldorf , Germany.
I would be finished sometime around november or december. if after that
is ok.
Then i can send you CV.
Regards,
Anil
reachranbir@gmail.com wrote:
> Hi,
> this is ranbir here. my client is plannin to build complex SoC for
> their CDMA based mobile handsets. their design centre will be based
in
> Bangalore, India.
>
> they are looking for an entire team for that purpose. we want
frontend
> design engineer, backend, physical design, verification, memory
design,
> rtl architects and everyting else.
>
> anybody from any nationlity are welcome to apply.
>
> Anybody interested??
Article: 80438Is there a way to measure the jitter?...the ouptu frequewncy of the VCO is 27Mhz....and the input frequency is 15.34 Mhz....so the PLL's dividers are given ratios accordingly... Falk Brunner wrote: > "genlock" <genlocks@gmail.com> schrieb im Newsbeitrag > news:1109954872.112005.262490@z14g2000cwz.googlegroups.com... > > Thanks...Well, right now...everything is working with the whole PLL > > function being done inside the FPGA itself.....but then there is a > > jitter in the output.....and am not able to figure out the reason.... > > How much jitter? > 1ns? > 1us? > > Whats the output frequency of the VCO? > Whats the compare frequency of the phase detetor? > > Regards > FalkArticle: 80439
Fernando Peral wrote: > i want to program atf750 from a .tt2 file (generated from another > vendor software). I'm trying fitters, i download fit5.0.zip and the > fitters for 1500, 1502, 1508... works well, but fit2500 which i must > use for atf750 says "NTTAPKP.DLL not found" and fails. I,ve tried > to download and use fit2500.zip but when i do > > fit2500 -i myfile.tt2 -dev p750 > > it says "error cannot open .dev file p750.dev" > > i,ve tried also with ablfit2500.zip but when i install it and try to > use says "i cant connect to the key". > i've also tried to use the p750.dev file from ablfit2500.zip with the > fit2500.exe froom fit2500.zip but it says it is a wrong file. żis > there any way of using the fitter from command line or similar? If you cannot get this to work, you could try a more convoluted but reliabe path : Use FIT1502 (etc), as they will import TT2 files, and the .FIT report file has the Boolean Equations, which you can then use as Atmel WinCUPL source files [some editing needed], and compile with WinCUPL set to ATF750, and you then get a ATF750 JED file. -jgArticle: 80440
oh I am looking for an example in c.Article: 80441
"genlock" <genlocks@gmail.com> wrote in message news:1110056003.781730.60110@l41g2000cwc.googlegroups.com... > Is there a way to measure the jitter?...the ouptu frequewncy of the VCO > is 27Mhz....and the input frequency is 15.34 Mhz....so the PLL's > dividers are given ratios accordingly... > Look back to my previous post. The phase comparator of the PLL should have two inputs at 15.734 kHz. One comes from the sync stripped off your video, the other from the VCO divider in the FPGA. Sync your scope on one, crank the timebase speed and the brightness way up, and see how far the other jitters.Article: 80442
Hi. I'm trying to do two basic things with a 22v10 but seem to be getting nowhere with them and would appreciate some help. I need the 22v10 to do the following: 1) Divide a 2mhz clock signal by 2 and output a 1mhz signal. 2) Output a high pulse for a duration of X clock cycles, triggered by an input going high. Can someone give me a clue as to how I get the chip to do these things? StephenArticle: 80443
"dollaz" <dollaz@gmail.com> writes: > oh I am looking for an example in c. Assuming you're using the EDK: ... char c; c = inbyte(); ... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 80444
Any of you has concrete numbers of the insurge current for the XC3S1000? how long does it take to go through the high current period? I'll appreciate any feedback. thanks, paulArticle: 80445
There is no high-current "insurge" upon power-on in Xilinx Virtex-II and later, nor in Spartan-3 devices. We fixed that old problem many years ago... Peter Alfke, Xilinx ApplicationsArticle: 80446
Jens Baumann wrote: >KCL wrote: > > > >>Personnaly I have bought digilent board spartan to a french distributor >> >> >would you tell the distributor's name? > >I don't want to order from th US, because I have no idea about customs fees. > > > > >>But You should wait to see the price of the next starter kit spartan3e >>that have more stuff on it , but for the price it's actually unknow :on >>board >>:S3e 500 -4, 32MByte SDRAM, usb2,ethernet phy , 2 lines LCD display.... >>sound great >> >> > >any reference? > >Jens > > No Problem with ordering from the US. I ordered things from Xilinx and there is usally 16% "Einfuhrumsatzsteuer". When the postman rings twice he wants to collect it. Regards ThomasArticle: 80447
In term of choosing which FPGA board to buy, the best way to do is to write the code for your project FIRST, simulate, synthesize and place and route it. Verify everything works then buy the FPGA board LATER. I said this because by the time you verify that everything works in the simulation environment, you already know what features of the FPGA board you will need for your project. If you buy the FPGA board now, you may overspend your money on the FPGA that has all the bells and whistles you don't need, or underspend your money on the FPGA that doesn't have all the features you want. HendraArticle: 80448
"Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:zfmWd.4053$4x2.2947@newsfe4-gui.ntli.net... > <Huianx> wrote in message > news:42286153$0$31619$afc38c87@news.optusnet.com.au... >>I am new to the FPGA and I want to learn by small experiments. >> >> Can some FPGA experts tell me what is the easiest and least expensive way >> of getting started ? > > http://www.howell1964.freeserve.co.uk/logic/burched/fpga_devkit_b5.htm http://www.burched.biz/ > > Very competitive price. > Looks the cheapest, and is the most versatile because it doesn't give you > features you might not want. > > Individual projects tend to have their own requirements, so you build > those bits yourself. > > Some things tend to crop up often, and you can buy those ready-made as > required. > (RAM, IDE, CF, KBD, MSE, DACs, VGA, buzzer etc). xilinx S3 starter kit is a lot cheaper US$99 verus US$236 but Tony Burch does free fpga replacement if you blow your chip up. www.digilentinc.com make the S3 starter kit for xilinx and offer add on modules Also offer the S3 board with up to a 1 mil gate S3 for an extra US$50 (add board to shopping cart and options come up) also a S3e board on the way from Digilentinc / Xilinx http://www.xilinx.com/products/spartan3e/s3eboards.htm quarter3 2005 AlexArticle: 80449
For those (like me) who has no experience in FPGA programming, can you suggest which SW tool(s) (free or low-cost) would be good to start with for vendor independent learning ? > In term of choosing which FPGA board to buy, the best way to do is to > write the code for your project FIRST, simulate, synthesize and place > and route it. Verify everything works then buy the FPGA board LATER. > I said this because by the time you verify that everything works in the > simulation environment, you already know what features of the FPGA > board you will need for your project. If you buy the FPGA board now, > you may overspend your money on the FPGA that has all the bells and > whistles you don't need, or underspend your money on the FPGA that > doesn't have all the features you want. > > Hendra >
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z