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Messages from 81225

Article: 81225
Subject: FPGA and Verilog question
From: dfdfdfdf@gmail.com
Date: 19 Mar 2005 11:15:23 -0800
Links: << >>  << T >>  << A >>
Hello! I am very new to news groups, sorry if I'm doing something
wrong.

Couldn't you give me some useful links or something other, where I can
read about FPGA and FPGA programmators. I need to build FPGA
programmator with Vetilog, but not familiar with Verilog nor FPGA
(I program on C and other languages). Please help me


Article: 81226
Subject: Re: Spartan 3E vs. Cyclone2
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Sat, 19 Mar 2005 19:31:06 GMT
Links: << >>  << T >>  << A >>
Hi Austin,

> Spartan 3S100E was just announced, so to ask if a 3S1500E is sampling is
> a bit like asking if we are ready to go visit Mars.

So this Mars Rover thing is all a lie? I knew the whole thing was fake, just
like the moon landings! ;-)

Ben


Article: 81227
Subject: Re: (Stupid/Newbie) Question on UART
From: hmurray@suespammers.org (Hal Murray)
Date: Sat, 19 Mar 2005 13:52:51 -0600
Links: << >>  << T >>  << A >>
>A CID (consecutive identical digits) of 50 bits will cover most
>real-world cases of scrambled SONET traffic, but I'd personally want a
>CDR with noticably more staying power than that.

2**50 is 10**15  With a gigabit/sec link, that would be a glitch
every 10**6 seconds or roughtly 10 days.  Note that we are talking
clock-slip which is much worse than a simple bit error.
Adjust for your link speed.

I typed in 50 without much thinking.  Looks like I got in the right
ballpark.  Much lower than that would be a serious problem.  Much
higher would be hard to measure.

I think I remember 70 from years ago on OC-3.  That would be
another factor of 10**6 which would push the problem well
beyond the lifetime of any gear I've ever worked with.

What are current specs/reality for SONET links?  Are there any
interesting alternatives to SONET for long links?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 81228
Subject: Re: Spartan 3E vs. Cyclone2
From: "Marc Randolph" <mrand@my-deja.com>
Date: 19 Mar 2005 12:35:02 -0800
Links: << >>  << T >>  << A >>

Ben Twijnstra wrote:
> Hi Austin,
>
> > Spartan 3S100E was just announced, so to ask if a 3S1500E is
sampling is
> > a bit like asking if we are ready to go visit Mars.
>
> So this Mars Rover thing is all a lie? I knew the whole thing was
fake, just
> like the moon landings! ;-)

I'm going majorly off-topic here...

That reminds me of an mpeg clip I collected a while back: it has aliens
on Mars holding up a print-out of a barren Martian landscape - so
that's all the Mars rover can see.  It's pretty funny... but I don't
currently have anywhere to post it, and I can't find it online any
more.

   Marc


Article: 81229
Subject: Re: rocketio
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sat, 19 Mar 2005 21:35:15 +0100
Links: << >>  << T >>  << A >>

"austin" <austin@xilinx.com> schrieb im Newsbeitrag
news:d1hqit$ka91@cliff.xsj.xilinx.com...
> Falk,
>
> You could decide to scramble the data and not use 8B10B, but then you
> would have to be sure your scrambling never violated run length, or DC
> imbalance issues, and you could live with scrambling multiplying a
> single error into to more than one.

Hmmm, since scrambling works reasonable well (all long distance traffic on
fiber optics is SONET/SDH) so it is a good option. But maybe a soft 64B/66B
encoder (V2P) let you sleep much more relaxed and so its worth the silicone.

Regards
Falk




Article: 81230
Subject: Re: Spartan 3E vs. Cyclone2
From: Kris Vorwerk <nothanks@noonehere.org>
Date: Sat, 19 Mar 2005 15:44:38 -0500
Links: << >>  << T >>  << A >>
> So this Mars Rover thing is all a lie? I knew the whole thing was fake, just
> like the moon landings! ;-)


Actually, that would be Actel -- not X or A -- devices supporting the
Mars Rover  ;)

http://www.actel.com/company/press/2005pr/MarsRover.html

;)


cheers,
Kris


Article: 81231
Subject: Re: rocketio
From: "Thomas" <res0rsef@verizon.net>
Date: Sat, 19 Mar 2005 21:08:36 GMT
Links: << >>  << T >>  << A >>

Thanks for all the response. There is a very good app note(xapp681) from 
xilinx by John Snow bypassing MGT 8B/10B used as HD Receiver. Source code 
included.
Thomas


"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message 
news:3a3h36F67qf7aU1@individual.net...
>
> "austin" <austin@xilinx.com> schrieb im Newsbeitrag
> news:d1hqit$ka91@cliff.xsj.xilinx.com...
>> Falk,
>>
>> You could decide to scramble the data and not use 8B10B, but then you
>> would have to be sure your scrambling never violated run length, or DC
>> imbalance issues, and you could live with scrambling multiplying a
>> single error into to more than one.
>
> Hmmm, since scrambling works reasonable well (all long distance traffic on
> fiber optics is SONET/SDH) so it is a good option. But maybe a soft 
> 64B/66B
> encoder (V2P) let you sleep much more relaxed and so its worth the 
> silicone.
>
> Regards
> Falk
>
>
> 



Article: 81232
Subject: Re: (Stupid/Newbie) Question on UART
From: "Marc Randolph" <mrand@my-deja.com>
Date: 19 Mar 2005 13:21:28 -0800
Links: << >>  << T >>  << A >>

Hal Murray wrote:
> >A CID (consecutive identical digits) of 50 bits will cover most
> >real-world cases of scrambled SONET traffic, but I'd personally want
a
> >CDR with noticably more staying power than that.
>
> 2**50 is 10**15  With a gigabit/sec link, that would be a glitch
> every 10**6 seconds or roughtly 10 days.  Note that we are talking
> clock-slip which is much worse than a simple bit error.
> Adjust for your link speed.
>
> I typed in 50 without much thinking.  Looks like I got in the right
> ballpark.

Yes, you did.

> Much lower than that would be a serious problem.  Much
> higher would be hard to measure.

Yep - until you start feeding PRBS test streams into the scrambler,
which can make your equipment look less reliable than it would be
against a real-world stream.

> I think I remember 70 from years ago on OC-3.  That would be
> another factor of 10**6 which would push the problem well
> beyond the lifetime of any gear I've ever worked with.
>
> What are current specs/reality for SONET links?  Are there any
> interesting alternatives to SONET for long links?

I don't think there is an absolute minimum requirement, but a commonly
accepted number is 72 digits - so your memory is quite good.  Modern
CDR's tend to be able to handle even more digits than that, but as you
said, the probability starts getting so low that it is well beyond the
lifespan of just about anything (humans, electricty, copper wire, etc).
 Somewhere I got it that the V2Pro MGT can handle over 75 CID (to try
to insert at least one FPGA related item to this post).

As for long haul links, if you want protection, SONET is still the main
choice.  I think that RPR is trying to make in-roads, but has been slow
out of the gate and from what I've heard third hand, is slow to be
adopted by the carriers.  I believe a third alternative is protected
DWDM (not as intelligent as SONET or RPR, but that means maintenance is
considerably less expensive).  There may be others I can't recall at
the moment.

Have fun,

   Marc


Article: 81233
Subject: Re: Spartan 3E vs. Cyclone2
From: austin <austin@xilinx.com>
Date: Sat, 19 Mar 2005 13:29:23 -0800
Links: << >>  << T >>  << A >>
Kris,

Well, we are in the wheel control, arm control, and we did the pyro 
control for the lander:

http://www.xilinx.com/prs_rls/design_win/0412_marsrover.htm

Austin

Article: 81234
Subject: Re: rocketio
From: austin <austin@xilinx.com>
Date: Sat, 19 Mar 2005 13:31:17 -0800
Links: << >>  << T >>  << A >>
Falk,

I agree.  Making your own link format, data protocol, etc. is a big 
project.  Best to use a standard.

Also, don't use silicone.

Austin


Article: 81235
Subject: Re: XC3S50 or EPM1270?
From: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca>
Date: Sat, 19 Mar 2005 16:37:45 -0500
Links: << >>  << T >>  << A >>
Hi Vax,

You will need three voltages for your S3 (1.2, 2.5, and 3.3V), while for Max 
II you'll need just the one (3.3V).  And you won't need a seperate 
configuration RAM.  Also, I'd look into those costs again.  The EPM1270 will 
be in production shortly and should be cheaper longer term than low-end 
FPGAs such as S-3 since Max II has a smaller die.

Regards,

Paul Leventis
Altera Corp. 



Article: 81236
Subject: Re: Spartan 3E vs. Cyclone2
From: "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca>
Date: Sat, 19 Mar 2005 16:42:05 -0500
Links: << >>  << T >>  << A >>
>> On a performance front, you will find that Cyclone and Cyclone II have
>> a significant performance advantage over Spartan-3.  We're talking
>> 50-60% (core performance on 100+ designs, comparing fastest speed grade
>> to fastest speed grade using best-possible software settings).
>
> BTW, the Cyclone manual says that the highest speed of
> an M4K RAM bank is 200MHz, but Quartus estimates it to
> about 250MHz (Cyclone 1C6, speed grade 6). So, which
> information is right?

Always trust the latest version of Quartus -- the datasheet is supposed to 
follow whatever we put in the software, not vice versa.  I will check into 
this and get the datasheet corrected if neccessary.

Regards,

Paul Leventis
Altera Corp.



Article: 81237
Subject: Is the Xilinx EDK free?
From: "Paul Marciano" <pm940@yahoo.com>
Date: 19 Mar 2005 14:53:13 -0800
Links: << >>  << T >>  << A >>

I am a hobbyist, actually an embedded software engineer trying to learn
about verilog and FPGAs, and would like some advice.

I'm thinking of buying either the Xilinx Spartan 3 starter kit or the
Digilent Spartan 3 board with a larger FPGA (say, the 400 instead of
the Xilinx one with the 200).  It's the same board, but Digilent allow
me to order a larger part.

Do I need a larger FPGA?  I can't answer that...  but I figure it's
like RAM... better to have too much and not need it than need it and
not have it.  What am I going to do with it?  My first project will be
to make an LED flash.  Beyond that, I have no idea, but the
Digilent-built boards have lots of ins and outs to play and learn with.


The Xilinx starter kit comes with ISE6.1 Evaluation, WebPack and also
the EDK evaluation and MicroBlaze license.  The Digilent board is just
a board.

I'd like to use the latest tooks (WebPack 7.1), and use the MicroBlaze
core, but I'm not a professional, don't have a rep and don't have a
budget.


If I buy the Digilent board, can I just download the EDK, or is it
something Xilinx charges for so I'd be better off buying the Xilinx
starter kit?

Advice appreciated.

Thanks.
Paul.


Article: 81238
Subject: Re: Spartan 3E vs. Cyclone2
From: Ben Twijnstra <btwijnstra@gmail.com>
Date: Sun, 20 Mar 2005 00:14:48 GMT
Links: << >>  << T >>  << A >>
Hi Luc,

> What about DDR or DDR2 support?
> This is certainly somthing I'm looking for. Multipliers are benificial
> but not a necessity.

I don't have definite specs handy, but Cyclone 1 can control DDR SDRAM at
133MHz (see the Twister board at http://www.fpga.nl). The device chosen was
a 240-pin QFP, which caused the PCB and FPGA designer some headaches to
meet timing. Had he been allowed to use an F256 device, things would have
been a lot easier.

The Cyclone and Cyclone II will do both DDR and DDR2. I'd personally just go
for DDR using a Cyclone(II) in an FPBGA package - this mainly due to
availability of DDR chips compared to DDR2 chips and ease of design in the
FPGA.

BTW: the Cyclone II multipliers are currently rated at 250MHz. I have a
standing bet (6 beers) that production silicon will be fast enough to reach
something in bthe range of 270-320MHz, and I'm not expecting to give out
any beer.

Best regards,



Ben


Article: 81239
Subject: Re: Newbie: Slow FPGAs
From: dave <dave@dave.dave>
Date: Sun, 20 Mar 2005 00:44:36 +0000
Links: << >>  << T >>  << A >>
Jonathan Bromley wrote:
> On Thu, 17 Mar 2005 21:16:49 +0000, dave <dave@dave.dave> wrote:
> 
> 
>>Contrary to what you may think there is a market for
>>Ghz speed flexible FPGAs.
> 
> 
> I don't doubt it, but I suspect the market is unlikely to be 
> satisfied with the cost/performance compromise.
> 
> Every gate in an FPGA costs...
> - the gate itself (or LUT, or whatever)
> - programming infrastructure to allow you to
>   configure it
> - programmable routing - that means switching matrices
> - probably, some unused stuff around the gate because your
>   chosen function doesn't fully occupy the FPGA cell (logic
>   block, slice, whatever)
> 
> All these increase die area and therefore cost-per-function;
> some worsen signal delays as well.  By contrast, a gate on
> a custom device is just that: a gate and some hardwired
> routing.  It's sure to be faster than the FPGA equivalent.
> 
> There have been a few attempts, over the 20+year history
> of FPGAs, to introduce more ASIC-like structures in FPGA
> fabric.  Most have failed horribly - remember Pilkington?
> 
> However, you can get amazing bang-per-buck in an FPGA if 
> you use it to solve the right sort of problems.  Any DSP-ish
> problem that keeps a lot of arithmetic units busy for a lot
> of the time will be a good candidate.  Simple bit twiddling
> is always much faster in FPGAs than in programmable CPUs -
> try writing a piece of C to do this...
> 
>    reg [15:0] R;
>    ...
>    R = {R[15:12], R[2:0], ~R[11:8], R[7:3]};
> 
> It's almost free in hardware, messy and slow in software.
> 
> And then the FPGA vendors have been very ingenious in adding
> a few dedicated functions that make it easier to map common
> problems on to the FPGA fabric.  Embedded multipliers and
> RAMs are obvious examples.  SERDES on I/O pins allows you
> to fan out a multi-GHz input to a much slower but wider
> data path in the FPGA fabric, and achieve stuff that would
> be impossible in software.
> 
> So, although I sense your frustration, things are probably
> the way they are for a good reason; and if you want 2GHz CPU
> then you better go and buy one from the usual suspects.
> I imagine that there will always be a factor of 10 difference
> between the fastest you can do a dedicated function in ASIC
> and the speed you can do the same thing in regular FPGA fabric.

Thanks. Your reply follows the general theme of others: FPGA speeds are 
sufficiently high, it is the design of FPGA technologies that can 
sometimes result in what might appear slow performance, but in fact this 
is the generic FPGA functionality at work.

I (inappropriately) was complaining about why "one size fits all" FPGA 
devices did not meet my specific requirements. Stupid now I consider it 
and the flames will continue to burn me for a while!!

Article: 81240
Subject: Re: Spartan 3E vs. Cyclone2
From: "Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl>
Date: Sun, 20 Mar 2005 02:30:12 +0100
Links: << >>  << T >>  << A >>
Ben Twijnstra wrote:

> I don't have definite specs handy, but Cyclone 1 can control DDR SDRAM
> at 133MHz (see the Twister board at http://www.fpga.nl).

Yes, I have seen the same specification and I wonder why it is
so slow. I have some SDR memories with fmax = 183MHz, so
I would like to know whether it is possible to use them with a
Cyclone at that speed. The next problem is that the data path
width will be 48 bits and the megafunction documentation says
that the controller is capable of doing 16-, 32- and 64-bit transfers.
But how about 48 bits? :-)

    Best regards
    Piotr Wyderski


Article: 81241
Subject: DATA2MEM, how do I get the ELF file?
From: "Lin MuIin" <lin_mulin@yah0o.c0m.au>
Date: Sun, 20 Mar 2005 10:17:35 +0800
Links: << >>  << T >>  << A >>
My scheme is like this, I generated a 32Bit*1024word DPRAM with Coregen
and inserted that into my design to store some initialization data. After I 
generated
bitstreams of the entire design, I will use DATA2MEM to generate bitstreams
according to each different initialization. The initializationdata are 
stored in hex
format, 4bytes/1024rows in text files.

I failed to find any information on how to generate ELF/DRF/MEM files, and
I have difficulty coding BMM file. Where can I find such reference 
materials?

Thank you.





Article: 81242
Subject: Re: Spartan 3E vs. Cyclone2
From: Sander Vesik <sander@haldjas.folklore.ee>
Date: Sun, 20 Mar 2005 02:52:52 +0000 (UTC)
Links: << >>  << T >>  << A >>
Marc Randolph <mrand@my-deja.com> wrote:
> 
> Ben Twijnstra wrote:
> > Hi Austin,
> >
> > > Spartan 3S100E was just announced, so to ask if a 3S1500E is
> sampling is
> > > a bit like asking if we are ready to go visit Mars.
> >
> > So this Mars Rover thing is all a lie? I knew the whole thing was
> fake, just
> > like the moon landings! ;-)
> 
> I'm going majorly off-topic here...
> 
> That reminds me of an mpeg clip I collected a while back: it has aliens
> on Mars holding up a print-out of a barren Martian landscape - so
> that's all the Mars rover can see.  It's pretty funny... but I don't
> currently have anywhere to post it, and I can't find it online any
> more.

It comes from a long and god tradition though - there have been ones with
for example martians "manning" large fans to create dust storms to hinder
poor earth-sent satellites ;-)

> 
>    Marc
> 

-- 
	Sander

+++ Out of cheese error +++

Article: 81243
Subject: Re: Altera free web FPGA software license question
From: Sander Vesik <sander@haldjas.folklore.ee>
Date: Sun, 20 Mar 2005 03:01:35 +0000 (UTC)
Links: << >>  << T >>  << A >>
Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote:
> 
> The MAC address should be unique for every piece of ehternet connectable
> kit.

at least in theory. most cards support changing it because well... 
its just in a serial eeprom that can be read/written from the host.
which is so because nobody wants to have two serial eeproms per card.

-- 
	Sander

+++ Out of cheese error +++

Article: 81244
Subject: Re: DATA2MEM, how do I get the ELF file?
From: "Nju Njoroge" <njoroge@stanford.edu>
Date: 19 Mar 2005 19:07:25 -0800
Links: << >>  << T >>  << A >>

Lin MuIin wrote:
> My scheme is like this, I generated a 32Bit*1024word DPRAM with
Coregen
> and inserted that into my design to store some initialization data.
After I
> generated
> bitstreams of the entire design, I will use DATA2MEM to generate
bitstreams
> according to each different initialization. The initializationdata
are
> stored in hex
> format, 4bytes/1024rows in text files.
>
> I failed to find any information on how to generate ELF/DRF/MEM
files, and
> I have difficulty coding BMM file. Where can I find such reference
> materials?
Try this link:
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&key=dr_dt_data2mem

Or a direct link to the PDF is:

http://www.xilinx.com/ise/embedded/data2bram.pdf

This is a reference that details what you are trying to do.
Good luck,

NN


Article: 81245
Subject: Re: Bit-Rounding Algorithm
From: "morpheus" <saurster@gmail.com>
Date: 19 Mar 2005 20:50:21 -0800
Links: << >>  << T >>  << A >>
Thanks Dough,
I am aware of the overflow, infact, my adder is 25 bits but I was just
concerned with the rounding of the 24  data bits. I was going to
account for the sign bit as part of the rounding algo(once I got one).
Regards
MORPHEUS


Article: 81246
Subject: Re: Is the Xilinx EDK free?
From: "Alex Gibson" <news@alxx.net>
Date: Sun, 20 Mar 2005 17:40:49 +1100
Links: << >>  << T >>  << A >>

"Paul Marciano" <pm940@yahoo.com> wrote in message 
news:1111272793.613101.5520@l41g2000cwc.googlegroups.com...
>
> I am a hobbyist, actually an embedded software engineer trying to learn
> about verilog and FPGAs, and would like some advice.
>
> I'm thinking of buying either the Xilinx Spartan 3 starter kit or the
> Digilent Spartan 3 board with a larger FPGA (say, the 400 instead of
> the Xilinx one with the 200).  It's the same board, but Digilent allow
> me to order a larger part.

Also a 1mil gate S3

If you can wait a while(like until end of the year)
http://www.xilinx.com/products/spartan3e/s3eboards.htm

Also are the Xess boards
www.xess.com

fpga4fun
http://www.fpga4fun.com

Tony Burch
http://www.burched.biz/

>
> Do I need a larger FPGA?  I can't answer that...  but I figure it's
> like RAM... better to have too much and not need it than need it and
> not have it.  What am I going to do with it?  My first project will be
> to make an LED flash.  Beyond that, I have no idea, but the
> Digilent-built boards have lots of ins and outs to play and learn with.

Depends what you want to do but can't hurt.
Lots of xilinx app notes.
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Application+Notes
Can also request a resource cd that has all the xilinx docs on it,
link on s3 starter kit page

Lots of potential projects
http://www.xess.com/ho03000.html  may need modifying slightly do to board 
differences

digilentic have a few reference designs and also
addon boards like usb and ethernet , lcd etc
reference designs http://www.digilentinc.com/Materials/BoardProducts.html
peripheral boards https://www.digilentinc.com/Sales/Peripheral.cfm
xilinx link for daughter boards 
http://www.xilinx.com/products/spartan3/boards/daughtercards.htm

xilinx has a few for the S3 starter kit at the bottom of this page
http://www.xilinx.com/products/spartan3/s3boards.htm

old arcade games
http://www.fpgaarcade.com/

Good stuff here
http://www.fpga4fun.com/
http://www.burched.biz/links.html

picoblaze core from xilinx
http://www.xilinx.com/products/design_resources/proc_central/grouping/picoblaze.htm

> The Xilinx starter kit comes with ISE6.1 Evaluation, WebPack and also
> the EDK evaluation and MicroBlaze license.  The Digilent board is just
> a board.
>
> I'd like to use the latest tooks (WebPack 7.1), and use the MicroBlaze
> core, but I'm not a professional, don't have a rep and don't have a
> budget.

webpack is free
edk is not, supposedly you get an eval copy when you buy
an S3 starter kit from Xilinx
and xilinx were supposedly shipping copies
of the eval edk to everyone that bought an S3 starter kit but
I haven't receieved an eval edk cd yet.

> If I buy the Digilent board, can I just download the EDK, or is it
> something Xilinx charges for so I'd be better off buying the Xilinx
> starter kit?

They charge for it US$450 ?
The eval version is 30 days only I think ?

There are a couple of opensource cores from www.opencores.org
that  have compilers for them but not prepackaged with gui tools

Also for microblaze - uclinux port
http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux

Aklex 



Article: 81247
Subject: Re: One-hot statemachine design problems
From: Preben Holm <64bitNOnoNOSPAM@mailme.dk>
Date: Sun, 20 Mar 2005 10:39:20 +0100
Links: << >>  << T >>  << A >>
DerekSimmons@FrontierNet.net wrote:
> What is this for? If you are a student and this is part of an
> assignment I don't want to just give you the answer but that doesn't
> mean I won't try to help you.

I am ofcourse a student, but it's quite some time ago that I learned 
about statemachine design (two years actually). Right now I'm trying to 
do my bachelor, where I deciden to use VHDL and the Spartan III for my 
project. I am supposed to build the digital sampling part of a digital 
storage oscilloscope.
But all the theory and implementation which I haven't done a lot of work 
of is being my trouble.
So it's not an assignment, more a tiny part of my own project.


> Are there any design requirements that need to be followed or met?

Well, as fast as possible (aiming for 200MHz maximum speed)!


> Style and presentation is very important with VHDL. WIth a programming
> language like 'C' you can get away with creating compound and nested if
> statements with different structures and with an optimizing compiler
> end up with the same result.

Well, if my litterature is outdated I'm very happy if someone could give 
me advice for some more updated litterature.


> Early when I was learning VHDL, I noticed that depending on how you
> structure your code effects the circuit design. In VHDL the compiler
> tries to implement designs it recognizes ie. state machines.

Both the single-process, the xilinx-template, and the one-hot approach I 
tried to build did the job as being recognized as statemachines (FSM's).


> As, someone else pointed out, the way you went about implementing your
> state machine isn't the expected way. Try implementng using case
> structure instead of if control structure. Don't forget the differences
> between case and if statements - if statements are evaluated sequential
> and case states are evaluated parallel.

I'm aware of that if-statements are "sequential" (the last if-statement 
  has the "power"), but in hardware they are still quite parallel (even 
though more if's costs more time in some cases).


> In VHDL as in C, if you have a large chunk of code and are having
> trouble with it you should break it up into smaller chunks. Use block
> and process structures to make your code smaller. It should make your
> code easier to read and make the compilers job easier.

Yeah, but I'm not able to break a state machine into smaller pieces, and 
this is even though quite simple!



How do you like my new design (single-process)
----------------------------------------------
entity holdoffcontroller is
     Port ( clk : in std_logic;
            reset : in std_logic;
            save : in std_logic;
            trig : in std_logic;
            read : in std_logic;
            holdoff : in std_logic;
            hold : out std_logic := '0';
            state : out std_logic_vector(4 downto 0));
end holdoffcontroller;

architecture Behavioral of holdoffcontroller is
     type states is (stateStart, stateWait, stateTrigger, stateHold, 
stateRead);
begin

     STATEMACHINE: block
         signal current_state : states := stateStart;
     begin
         stateRegister : process(clk, reset)
         begin
             if reset = '1' then
                 current_state <= stateStart;
             elsif rising_edge(clk) then
                 current_state <= current_state;

                 case current_state is
                     when stateStart =>
                         --holdoff_counter_enable <= '0';
                         --holdoff_counter_reset <= '1';
                         hold <= '0';

                         if holdoff = '0' and read = '0' and trig = '0' then
                             current_state <= stateWait;
                         end if;


                     when stateWait =>
                         if trig = '1' then
                             current_state <= stateTrigger;
                         end if;


                     when stateTrigger =>
                         --holdoff_counter_enable <= '1';
                         hold <= '1';

                         if holdoff = '1' and read = '0' then
                             current_state <= stateHold;
                         end if;

                         if holdoff = '0' and read = '1' then
                             current_state <= stateRead;
                         end if;

                         if holdoff = '1' and read = '1' then
                             current_state <= stateStart;
                         end if;


                     when stateHold =>
                         --holdoff_counter_enable <= '0';

                         if read = '1' then
                             current_state <= stateStart;
                         end if;


                     when stateRead =>
                         if holdoff = '1' then
                             current_state <= stateStart;
                         end if;

                 end case;
             end if;
         end process;


         process(current_state)
         begin
             case current_state is
                 when stateStart   => state <= "00001";
                 when stateWait    => state <= "00010";
                 when stateTrigger => state <= "00100";
                 when stateHold    => state <= "01000";
                 when stateRead    => state <= "10000";
             end case;
         end process;
     end block;

end Behavioral;

----------------------------------------------

Article: 81248
Subject: Post-map simulation models
From: Preben Holm <64bitNOnoNOSPAM@mailme.dk>
Date: Sun, 20 Mar 2005 11:04:34 +0100
Links: << >>  << T >>  << A >>
Hi everyone...

Why is my statemachine not functioning the first many clock-cycles of 
the post-map simulation?

Any explanation to that?



Thanks
Preben Holm

Article: 81249
Subject: Re: Spartan 3E vs. Cyclone2
From: "Thomas Entner" <aon.912710880@aon.at>
Date: Sun, 20 Mar 2005 11:22:08 +0100
Links: << >>  << T >>  << A >>
When we are talking about IO: Does anybody (i.e. Austin ;-) know the max. 
LVDS-transmit-rate of Spartan 3E, slowest speed-grade?

Regards,

Thomas

www.entner-electronics.com

"Luc" <lb.edc@pandora.be> schrieb im Newsbeitrag 
news:lmmm31lrm84tielfem34qtqdmfj9eu8gpg@4ax.com...
> Ben & Paul,
>
> Thanks for the feedback.
> I wonder what X & L could add to their defence.
>
> What about DDR or DDR2 support?
> This is certainly somthing I'm looking for. Multipliers are benificial
> but not a necessity.
>
> Regards,
>
> Luc
> On 18 Mar 2005 13:55:56 -0800, "Paul Leventis"
> <paul.leventis@utoronto.ca> wrote:
>
>>Hi Luc,
>>
>>I don't have much to add -- Ben has covered most of the high points.
>>
>>> Has someone seen samples yet, knows something more how they compare
>>> (performance, pricewise).
>>
>>On a performance front, you will find that Cyclone and Cyclone II have
>>a significant performance advantage over Spartan-3.  We're talking
>>50-60% (core performance on 100+ designs, comparing fastest speed grade
>>to fastest speed grade using best-possible software settings).
>>
>>But don't take my word on it.  Download our freely available Quartus II
>>Web Edition and give your design a whirl in Cyclone/Cyclone II.  Do the
>>same for Spartan-3.
>>
>>Regards,
>>
>>Paul Leventis
>>Altera Corp.
> 





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