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hi mk, thanks much for the explanation! (couldn't figure out what ISI stands for, though) thanks, skArticle: 81301
Dr Justice wrote: > Hi Paul! > > Go for the Picoblaze instead, it's free and comes with tools. I didn't know that. Thanks - Picoblaze will do nicely :-)Article: 81302
hi rajeev, thanks for your suggestions. >X485= RS485? yes, I guess that's what they meant. I've just played a bit around with an ADM3491. Doesn't really add any functionality compared to my hack, but if it buys better protection I might end up using it. Thanks, skArticle: 81303
I received an email from someone at Xilinx saying these are available now through distributors with an 8 week lead time. Sales rep just called; she says this part is "not open for orders". It is expected to be available for ordering at the "end of April". Pricing: FF668 package: $172 qty 1-24, $148 qty 25-99 SF363 package: $143 qty 1.24, $123 qty 25-99 Paul Smith wrote: > Has anyone actually purchased an XC4VFX12 yet? They supposedly went on > the market in January; parts don't show up in Xilinx online store, > distributors don't stock them yet; Xilinx sales rep is "checking", but > wasn't particularly encouraging or knowledgable. > > Paul Smith > Indiana University PhysicsArticle: 81304
>Our system integration tool (SOPC Builder) is included free with >Quartus, and with Nios II you get a whole suite of IP, configurable >processor choices, and IDE Thanks Jesse - I'll definately download it and take a look. The problem I have is the $295 evaluation kit and $1K license for the processor IP. Both of these are outside my budget. Why not make these available for free under a non-commercial license? That would allow anyone to freely evaluate it without restriction, until they make the decision to commercialize their design, at which point they must pay. I guess that requires a level of trust in the customer ;-) I imagine the Xilinx/Digilent relationship does a good job of grabbing mindshare of hobbyists and students who may eventually become real customers in their corporate/engineering lives. I read a lot of good things about Quartus, and the companies I have worked at have used Altera FPGAs... but for me, to learn, the cost of entry is too high. I will look at it. Thanks for the links! Regards, Paul.Article: 81305
Paul Marciano wrote: > >Our system integration tool (SOPC Builder) is included free with > >Quartus, and with Nios II you get a whole suite of IP, configurable > >processor choices, and IDE > > Thanks Jesse - I'll definately download it and take a look. The > problem > I have is the $295 evaluation kit and $1K license for the processor IP. > Both of these are outside my budget. > > Why not make these available for free under a non-commercial license? > That would allow anyone to freely evaluate it without restriction, > until > they make the decision to commercialize their design, at which point > they must pay. I guess that requires a level of trust in the customer > ;-) Hi Paul, Well I think that is the intent of the 'tethered' evaluation mode. The idea is that you get full use as long as the target board (Altera dev board or not) is connected to the PC... but I will leave the reasoning behind all this to the marketing force; "I'm just an engineer". Is this an academic project of some sort? If so, you might contact the Altera University Program. Depending on your project and circumstances they may be able to get you boards and/or licenses without cost. Jesse KempaArticle: 81306
Hi Paul, > Thanks Jesse - I'll definately download it and take a look. The > problem > I have is the $295 evaluation kit and $1K license for the processor IP. > Both of these are outside my budget. If you don't pay for the core or the software, you can still build a NIOS II system that will run either for 1 hour when standalone, or indefinitely as long as it's attached to the PC running Quartus through the cable supplied with the eval board. Cost: $295. Of course, you could also look at the Pluto II board (http://www.fpga4fun.com/board_pluto-II.html) for $54,95. A NIOS II will fit into the EP1C3T144 FPGA on that board. You won't have the capability of 'tethered operation', but 1 hour of running time should give you lots of opportunities to learn stuff. Best regards, BenArticle: 81307
kempaj@yahoo.com wrote: > Is this an academic project of some sort? If so, you might contact the > Altera University Program. Depending on your project and circumstances > they may be able to get you boards and/or licenses without cost. I'm a working stiff, not a student, so I can't use the AUP. Thanks for the idea though - I'm sure there are students out there with similar cost concerns who could benefit. Regards, Paul.Article: 81308
In article <423e77ae$1@clear.net.nz>, no.spam@designtools.co.nz says... > >The Eighth Doctor wrote: >> Hello from the Eighth Doctor >> (Apologies if this question is not group appropriate.) >> It seems my company's perenial problem with the PAL chips have sprouted again. >> The same individual that we created a something or other for, using a collection of >> PAL chips, and some normal glue logic wants us to make more of these things. >> Essentially a follow on to that thing. What it's supposed to do isn't the problem. >> Yet. It's the programming of the blank parts that is the problem. We've located >> which parts we want to use, and the PALASM software for writing the programs. >> But we need reccomendations on which programmer to select, and whose. >> --- >> Gregg drwho8 atsign att dot net >> "This signature disavows itself of the above message." >> >> However we need a programmer for the little devils. > > Some part numbers would help.. > You need to look at the Programmer vendor web sites, such as >eetools.com, and search their device lists. > Just type the PAL part numbers into google, and it usually finds >the programmer device lists, so you can work from those. > Hello from the Eighth Doctor Part numbers? Oh right. Yes, that's a good idea, to search based on the part numbers that we have chosen for our Bill of Materials. --- Gregg drwho8 atsign att dot netArticle: 81309
Ben Twijnstra wrote: > Of course, you could also look at the Pluto II board > (http://www.fpga4fun.com/board_pluto-II.html) for $54,95. A NIOS II will > fit into the EP1C3T144 FPGA on that board. You won't have the capability of > 'tethered operation', but 1 hour of running time should give you lots of > opportunities to learn stuff. That's a nice little board, thanks! Q. How do you limit the operation to 1hr? Do you have a countdown timer hard wired for a configured clock frequency? What if the processor is configured for xHz and an x/2 Hz oscillator is fitted - will it run 2hrs? Regards, Paul.Article: 81310
Try www.Salary.comArticle: 81311
Eric, First, thank you very much. I saw this web site intuitively. It's the same source as in www.monster.ca/.com, I think this is a reliable source, but not a REAL source. Thanks a lot again, V "Eric" <ericjohnholland@hotmail.com> wrote in message news:1111430133.617226.89510@g14g2000cwa.googlegroups.com... > > Try > > www.Salary.com >Article: 81312
Peter Sommerfeld wrote:
> I'm sure you should just be able to tie the upper 16 to ground on a
> 64-bit controller? Hopefully synthesis will remove most of the
> registers and logic for those unused data lines.
:-) Yes, this kludge might work...
Best regards
Piotr Wyderski
Article: 81313Hi Paul, > Q. How do you limit the operation to 1hr? Do you have a countdown > timer hard wired for a configured clock frequency? What if the > processor is configured for xHz and an x/2 Hz oscillator is fitted - > will it run 2hrs? Yep. There's about a 36-cell difference between a licensed core and an unlicensed one, and that's the down counter and its clock-enabling logic. Note that in the EP1C3, without any external SRAM or Flash, you only have room for ~4K ROM and ~2K RAM (or the other way around). No problem if you want to learn assembly, but for C you'll be on a tight budget. I've written small control applications in C with this configuration (not for this board) and as long as you don't use printf or other size hogs, there's a surprising lot of functionality you can stick into 4K of code. Also, Quartus is smart enough only to update the internal hardware ROM pattern after you recompile your software, so software changes can be relatively quick. Best regards, BenArticle: 81314
Vladislav Muravin wrote: > Hello, everyone. > > I could not find am answer on the web for the following question, which i am > not > quite comfortable to ask, but who else to ask it, except FPGA/ASIC people? > > Can anybody, please, point me to a website or give me any approximations > about > what salary is considered "average" and what is considered "top" in the > following places, > if we are talking about senior FPGA design engineer position? > (I have 6 years of ASIC/FPGA design experience, 4 from Israel + 2 from > Canada) > > (1) Montreal > (2) Vancouver > (3) Toronto > (4) Ottawa > > I would also highly appreciate any info/weblinks about living cost in > Vancouver. > > Thank you all very much for your time and attention. > > Sincerely, > Vladislav Muravin > > IEEE-USA has a nice salary survey -- you may see if it covers Canada, or if there is an equivalent IEEE group up there. I sometimes refer to the US Bureau of Labor statistics but they are (a) not very detailed, and (b) not at all interested in Canada -- but perhaps the Canadian equivalent would have some guidance? In general I would assume that a really good FPGA designer would get somewhat more than a generalist circuit designer, but probably not much more than a really good analog guy. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 81315
Thomas, See comments in line below, Austin Thomas Entner wrote: > Hi Austin, > > thanks for your comments. > > As I understand you, the logic-fabric is the limiting factor in Spartan > 3(E), not the IOs. Yes > > I do not need Gbs-speed, just around 600 Mbs will be OK. (So I think I need > 300MHz with DDR at the IO.) Yes, that is the use model that we would support. > > Can this be done in the Spartan3(E)? When doing simple tests with D-FFs and > T-FFs, I got frequencies in the range from > 300 to 600 MHz, not really reproducable. Strange... I have not tried to > implement the complete serializer yet. I do not see why not. We usually use a duty cycle corrected clock out of the DCM at 300 MHz (clk0, and clk180) on two bufgs so you can do all the double data rate stuff at 300 MHz, and then recreate the 600 Mbs at the input, or output pins. The trick is to multiplex this down to 150 MHz ASAP, as 300 MHz data paths are going to be tough to route in the fabric. Mux'ing right next to the IOBs is what is typically done. Is there > also a limit from the clock-network? In the datasheet I states, that > the -4-speedgrade can produce up to 330MHz at the DLL-CLKOUT_FREQ_2X, so I > think the clock-network can > handle this frequency? That is my understanding, too. But remeber that this will also probably require a package with some better SI than a pq208 (which definitely is something I would not recommend!). With the package SI, IO SI, bypassing, etc. you may be better off with a V4 package. The V4 is in a SF363 which is a laminate package with great SI, for example. > > I understand that you want to sell Virtex, but please understand that we > want to buy Spartan or Cyclone, even if it > are just 1000+ pieces ;-) Yeah, I know. But if the low cost part can't do it, please do take a look at the V4 parts: I doubt there will be a cost advantage, even in larger quantities. The small V4 devices are a great deal($).Article: 81316
Hello,
I would like to test my implementation of a DSP block
(CORDIC-based quadrature mixer + several filters and
decimators + two NCOs etc.). It has been written in pure
VHDL and should work on a Cyclone device. I have
a copy of Quartus 2 Web Edition and will not buy a full
version of it, since it is a non-profit enterprise. The problem
is that I don't want to check whether a finite automaton
is correct, but to perform a full-scale simulation (spectral
analysis, SNR, SFDR estimations etc.) and compare the
results with my reference design in Octave (Matlab).
So I need a VHDL simulator which can read and write
data (24-bit integers) from/to a text file. The simulator
shipped with Quartus doesn't support this feature and,
unfortunately, there is no free version of ModelSim at
Altera's website. So, could you please recommend me
a suitable tool (it doesn't have to provide a GUI, a batch
simulator would be even better)?
Best regards
Piotr Wyderski
Article: 81317
hi All,
I am trying to initialize the BLOCK RAM :- RAM16_S2 in a design using the
following statements
On simulation using MODELSIM , I dont get the correct values of the BLOCK
RAM, looks like
the the BLKRAM is failing to Initialize ,inspite of these INIT statements.
What could be the reason?
Thanks
Faizal
generic map (
INIT_00 =>
X"FFFFFFF000000000000000000000000000000000000000000000000000000000",
-----
------
Article: 81318Piotr Wyderski wrote: > I would like to test my implementation of a DSP block > (CORDIC-based quadrature mixer + several filters and > decimators + two NCOs etc.). It has been written in pure > VHDL and should work on a Cyclone device. I have > a copy of Quartus 2 Web Edition and will not buy a full > version of it, since it is a non-profit enterprise. The problem > is that I don't want to check whether a finite automaton > is correct, but to perform a full-scale simulation (spectral > analysis, SNR, SFDR estimations etc.) and compare the > results with my reference design in Octave (Matlab). > So I need a VHDL simulator which can read and write > data (24-bit integers) from/to a text file. The Quartus VWF files are readable text files, and the format is pretty simple to understand. It is not hard at all to write programs to generate them from 24 bit integers, and to generate 24 bit integers from them. I have not yet found a limit to the length of the files that can be processed. -- glenArticle: 81319
Paul Leventis (at home) wrote: > Hi Andy, > > >>I use the ISE Web Version at the moment, but I really don't ever want >>to shell out $2,500 for the Foundation version given my opinion of this >>software.... are there other alternatives around the same price >>bracket? > > > Try out Quartus II. You can download the free version (called "Web > Edition") from our website www.altera.com. The Quartus GUI is generally > pretty easy-to-use and has the look-and-feel of a modern Windows > application. > does it support V II Pro and the likes ? (nope, i don't mean migration;o) sorry, couldn't resist ;o) lArticle: 81320
you can create your own ROM block declaring an array of std_logic_vector
that is constant, i don't remember well if you should necessary ragister
adress_in and data_out but for frequency it's better (name are just for
example you could choose what you want)
ex:
entity block_ROM is
Port ( clk : in std_logic;
adress_in : in std_logic (2 downto 0);
data_out : out std_logic_vector(7 downto 0)
)
end block_ROM;
architecture Behavioral of block_ROM is
signal adress_reg: std_logic_vector(2 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
type TYPE_ROM is array (8 downto 0) of
std_logic_vector(7 downto 0);
----------------------------------------------------
constant memory : TYPE_ROM :=
(
"00000000",
"01111000",
"01000100",
"01111100",
"01000010",
"01000010",
"01111100",
"00000000",
);
-------------------------------------------------------
begin
process(clk)
begin
if rising_edge(clk) then
adress_reg <= adress_in;
data_reg <= memory( integer( to_unsigned(adress_reg)) ;
data_out <= data_reg;
end if;
end process;
"faizal" <faizal@ieee.org> a écrit dans le message de news:
d1n8j9$lme$1@news.fsu.edu...
> hi All,
> I am trying to initialize the BLOCK RAM :- RAM16_S2 in a design using
> the
> following statements
> On simulation using MODELSIM , I dont get the correct values of the
> BLOCK
> RAM, looks like
> the the BLKRAM is failing to Initialize ,inspite of these INIT statements.
> What could be the reason?
> Thanks
> Faizal
>
>
>
> generic map (
> INIT_00 =>
> X"FFFFFFF000000000000000000000000000000000000000000000000000000000",
> -----
> ------
>
>
Article: 81321Hi: Have a look at www.mediatronix.com/tools for a free simulator for DDC designs. You will find a FIR designtool too. Henk van Kampen. www.mediatronix.com Nemesis wrote: > Hi all, > I'm implementing a Digital Down Converter for Virtex II pro device. > > I think I'll not use the builtin DDC IP core because I'm using this > project to learn something about FPGAs and VHDL. > > Essentially I have samples coming from an A/D at 64MHz. The signal is > bandpass, centered at 112 MHz and it can have to different bandwidth > 5MHz and 25MHz. > > I've already implemented in VHDL the I and Q components splitting, now I > have to filter these signals with low pass filter and decimate the > sequence. I'm going to use the "MAC FIR Filter" IP core (shipped with > Xilinx ISE). > > I have some questions, I'm a newbie digital designer so please consider > this :-) > > 1) using a polyphase decimator is exactly the same of using a > single rate filter and then downsampling the output? > > 2) I need the same filter on both I and Q channels, so I think I could > set the core to use 2 channels, but I'm not sure how it works, is it > realized with time sharing? I'd need the two samples I(k) Q(k) at the > same time. > > Thank you all, and > -- > I tried switching to gum but I couldn't keep it lit. > > |\ | |HomePage : http://nem01.altervista.org > | \|emesis |XPN (my nr): http://xpn.altervista.orgArticle: 81322
> If you ever are able to reproduce the problem at will, probably > the easiest way to check the health of the internal CCLK is to place > the part in master serial mode before initial powerup, so you can > observe the behavior of the CCLK output under the lockup-generating > conditions. I don't know if the problem would show up in master mode. I don't want to introduce any other variables into the system. I know it has this problem with the current configuration. I had tried to send out a few seconds of normal clock cycles once the part was locked and was not able to get it to recover. But, again if the device's internal clock was dead, then the device would not be able to sample the Reset state. After playing with various near field probe designs, I now have one that appears to pick up the 1MHz internal clock. The probe hooks directly to a 20db amplifier and off to the spectrum analyzer. I am not working in a screen room right now but the signal does appear to be from the FPGA and not a local radio station. It is very close (within 50KHz) to the 1MHz that is called out. I have run three more days of tests and was not able to get the part into the strange mode. I am curious if Xilinx has had troubles with their internal oscillators in the past. The newer parts are programmable where this part is not (fixed clock rate). So some changes were made to the design. I will post again once I can see if it is the clock or not.Article: 81323
Sylvain Munaut wrote: > >> Well, they also screwed up the WebPack installer apparently ;( >> A don't have any RHEL 3.0 handy to install and copy, I'll have to find >> another >> way. > > > Apparently just installing openmotif did the trick ( missing libXm.so.3 was > the problem ) > I'm on gentoo btw Well, I get an error about libcurl.so.2, I only have libcurl.so.3.0.0. I tried creating an symbolic linking from libcurl.so.2 to libcurl.so.3.0.0 but this doesn't work: ------ echelon tmp # ./WebPACK_71_fcfull_i.sh Verifying archive integrity... All good. Uncompressing Xilinx ISE WebPACK Installer.............................................................................................................................................................................. /tmp/selfgz27591/platform/lin/bin/lin Cannot register service: RPC: Unable to receive; errno = Connection refused unable to register (registryProg, registryVers, tcp) Wind/U Error (248): Failed to connect to the registry on server echelon _X11TransSocketOpen: socket() failed for tcp _X11TransSocketOpenCOTSClient: Unable to open socket for tcp _X11TransOpen: transport open failed for tcp/echelon:0 Wind/U X-toolkit Error: wuDisplay: Can't open display ************ setup done! *************** echelon tmp # ------ So, any idea what to do about this. Thanks, Preben (at the gentoo-box)Article: 81324
Sander Vesik wrote: > Nial Stewart <nial@nialstewartdevelopments.co.uk> wrote: >>The MAC address should be unique for every piece of ehternet connectable >>kit. > at least in theory. most cards support changing it because well... > its just in a serial eeprom that can be read/written from the host. > which is so because nobody wants to have two serial eeproms per card. Traditionally it was stored in ROM, and at initialization the software driver would read the ROM and write into the appropriate register on the ethernet controller. It might be that they are now in EEPROM, but I believe they are still read/written by software, in part to support systems that require special MAC addresses (DECNet, for one). I don't know if license software uses the ROM/EEPROM address, or the one assigned to the ethernet hardware. -- glen
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