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larwe@larwe.com wrote: > >>Are ISA covered by patents or trademarks? Is it allowed to develop a >>processor core for a popular ISA as long as no reference is made to > > any > > Depends on the ISA. ARM, for instance, is covered by thick IP > protection layers, and is vigorously defended. 8051, not so much :) > W/ ARM for instance, I understand that they can protect their IP implementation w/ patents or copyrights but what would be the lawwhich prevent someone from implementing a processor core running an ARMv5? If someone implements a core able to run any compiled w/ gcc using some of the x86 flags, could INTEL prevent him from distributing the core. No mention is directly done of the INTEL name; no claim would be done for any INTEL compatibility of the processor core. What could happen? EricArticle: 82001
> Now, that doesnt mean the lawers want come after you, they can try at least. > But by being VERY VERY Careful it is possible to make the case a 'no case' > for the lawers. But you really have to have a 'clean implementation' - and > you have to withstand any pressure from the lawers who try to prove the > opposite. The keypoint, I think, is: are we talking about 1) patents (but the ARM ISA is full of instructions developped before it appears) 2) trademarks (but as long as no mention/no claim regarding the original names are done, would it be ok?) 3) copyright (but if an ISA is a language, an someone copyright it?) EricArticle: 82002
> W/ ARM for instance, I understand that they can protect their IP > implementation w/ patents or copyrights but what would be the lawwhich > prevent someone from implementing a processor core running an ARMv5? Patents relating to specific instruction set features. I don't know what patents they hold specifically; I'm sure there are some. > If someone implements a core able to run any compiled w/ gcc using some > of the x86 flags, could INTEL prevent him from distributing the core. No > mention is directly done of the INTEL name; no claim would be done for > any INTEL compatibility of the processor core. What could happen? You could be sued for distributing a product in violation of another party's intellectual property rights. For example, suppose Intel has patents on some aspect of MMX. You implement MMX compatible instructions in an infringing way. They have a claim against your product. Example: I make a device that plays video off optical disks. It just so happens by accident that my design is exactly the same as, and in fact compatible with, the DVD standard. The DVD consortium can sue me for infringement. They could still sue me with equal success if I can PROVE that I developed my device totally without any reference to their designs.Article: 82003
Hi all, Up to now i've been using ISE 6.3 together with gplcver for simulation. Some things seem to have changed with ISE 7.1, since gplcver doesn't seem to like the simulation verilog modules of some components. For example, when simulating the DCM, cver tells me the following : **/opt/xilinx/verilog/src/unisims/DCM.v(43) ERROR** [1044] instance/gate "MAXPERCLKIN" type "localparam" connection list expected - = read **/opt/xilinx/verilog/src/unisims/DCM.v(44) ERROR** [1044] instance/gate "MAXPERPSCLK" type "localparam" connection list expected - = read **/opt/xilinx/verilog/src/unisims/DCM.v(46) ERROR** [1044] instance/gate "SIM_CLKIN_CYCLE_JITTER" type "localparam" connection list expected - = read **/opt/xilinx/verilog/src/unisims/DCM.v(47) ERROR** [1044] instance/gate "SIM_CLKIN_PERIOD_JITTER" type "localparam" connection list expected - = read **/opt/xilinx/verilog/src/unisims/DCM.v(356) ERROR** [753] instance i_max_clkin pound parameter maximum_period (pos. 1) expression MAXPERCLKIN only parameters and constants - is parameter from other module? **/opt/xilinx/verilog/src/unisims/DCM.v(357) ERROR** [753] instance i_max_psclk pound parameter maximum_period (pos. 1) expression MAXPERPSCLK only parameters and constants - is parameter from other module? (sorry for the unwrapped long lines, but that's just the output) I must admit I haven't looked into much details about what might be causing the errors, I first wanted to check if anybody else ran into this, and if there's a (simple) solution. Any hints ? Thanks, _Ico -- :wq ^X^Cy^K^X^C^C^CArticle: 82004
For some reason, this only works in simulation, when I probe the pins on the chip, nothing shows up. If i have the WE toggle, then it works, I can see the data whenever WE is low. If after setting WE to 1'b1 for 20 cycles, I set WE to low all the time, no data on the scope. I triggered on the negative edge WE on the Oscilloscope and WE looks like it went to 1.2 V so not quiet a "1" and data[0] went to like 1.02 and that's it, nothing else happens. Same thing happens when I trigger on the rising edge of data[0].Article: 82005
http://gforge.openchip.org/projects/a86/ I had some working demos for ML300, but the project was iced oct'2004 the core is not nearly finished, only a subset of commands is working, just releasing as it is/was anttiArticle: 82006
I am trying to connect a custom IP to my MicroBlaze design. This custom IP is connected to the OPB Bus. It reads data from MicroBlaze, performs some computations and gives data back to the processor. I cannot figure out how to write data into the custom IP or how to read data from that IP. When we use Xilinx IP Cores, like GPIO, we are provided with functions like XGpio_Read, XGpio_Write etc. How do we communicate with our custom peripherals if we do not have such functions related to the custom peripheral? Do you have to write these drivers or is it sufficient just to make a wrapper for the custom peripheral so that all bus signals match the signals of the top-level wrapper? I would really appreciate if someone could guide me to an appropriate document or list out the steps of how to do this. ThanksArticle: 82007
I second the picoBlaze recomendation. We have a design that uses an
embeddec picoBlaze, and it worked great.
If you use the picoBlaze, be sure and download pBlazeIDE, the free IDE,
from: http://www.mediatronix.com/pBlazeIDE.htm
Urb
Paul Marciano wrote:
> Dr Justice wrote:
>
>>Hi Paul!
>>
>>Go for the Picoblaze instead, it's free and comes with tools.
>
>
> I didn't know that. Thanks - Picoblaze will do nicely :-)
>
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Article: 82008MikeJ wrote: > mmm, next time you want one done send me to India ! Haven't been there yet > :) > > Depends how big the asic is and how much info you have on it. > > www.fpgaarcade.com > > I have cloned a few early NAMCO asics and made plug in 28pin replacements. > No documentation on them, but functionally simple. Very small amounts of > code compared to my normal large virtex4 type stuff, but lots of debugging > and trial and error to get exact behaviour under all (tested at least) > cases. > > I have also (almost) finished the atari st custom chip sets, for which there > is a lot of documentation. > > What are you after ? > /Mike. > > You are almost done with your ST chips? Cool! thats one i personally am looking forward too ( but dont have the time, or experience yet, to do that on my own )Article: 82009
If your probes show that electrically the signals are not what you expect in a digital signal, the power supplies to your chip may be wrong. Please check your device for appropriate voltages to Vcco, Vccaux, and Vccint relative to ground. Have you verified that the chip is programming correctly? Are you driving an unusual load such as a 30 ohm resistor? Do you have your I/O signal format specified in your constraints as LVCMOS? LVTTL? 2mA? 24ma? What frequency is the design running? If the rest checks out, bottom line is if the I/O are bad, the design will run bad. A transition on WE may give the signal enough "oomph" to get past the invalid logic level to something that registers. With 1.2V and 1.02V signals, something is very wrong. It's certainly not the RAMB16_S9 primitive that's having troubles. "Ann" <ann.lai@analog.com> wrote in message news:ee8d229.9@webx.sUN8CHnE... > For some reason, this only works in simulation, when I probe the pins on the chip, nothing shows up. If i have the WE toggle, then it works, I can see the data whenever WE is low. If after setting WE to 1'b1 for 20 cycles, I set WE to low all the time, no data on the scope. I triggered on the negative edge WE on the Oscilloscope and WE looks like it went to 1.2 V so not quiet a "1" and data[0] went to like 1.02 and that's it, nothing else happens. Same thing happens when I trigger on the rising edge of data[0].Article: 82010
You should be able to bypass PALASM and use VHDL or Verilog for
programming some PALs and GALs. Latteice appears to have the best (free)
solution.
Lattice has a tool that supports their SPLDs (Simple PLDs). The link
below is for the ispLEVER Starter kit, which is free. SPLD support in
the free version includes 16V8, 20V8, 22V10, which will can be
configured to work like almost any 16/20/22 A/R/RA PAL device.
This is probably your best choice, because:
1. Reads and compiles ABEL, VHDL, Verilog, mixed schematic/HDL designs
2. Has a functional simulator (although you could use ModelSim XE for
that purpose)
http://www.latticesemi.com/products/devtools/software/ispLEVER-starter/index.cfm
Urb
Luc wrote:
> I do agree with Ben, there are a lot of super-PALs (or CPLDs) with
> JTAG capabilities. On the other hand, GALs are a very good replacement
> for PALs and these are still available. If you chech Lattice's
> website, you will find some documents about programmer support for
> GAL's and therefore also PAL's.
>
> Regards,
>
> Luc
>
> On Tue, 22 Mar 2005 08:23:07 GMT, Ben Twijnstra <btwijnstra@gmail.com>
> wrote:
>
>
>>Hi Gregg,
>>
>>
>>>Hello from the Eighth Doctor
>>>(Apologies if this question is not group appropriate.)
>>>It seems my company's perenial problem with the PAL chips have sprouted
>>>again. The same individual that we created a something or other for, using
>>>a collection of PAL chips, and some normal glue logic wants us to make
>>>more of these things. Essentially a follow on to that thing. What it's
>>>supposed to do isn't the problem. Yet. It's the programming of the blank
>>>parts that is the problem.
>>
>>Can't you convince your colleague to use something slightly more modern than
>>a PAL? I see more and more manufacturers dropping support for PALs (great
>>pity), and PALASM is not the most user-friendly way to develop logic or
>>testing harnesses in.
>>
>>Especially now that (s)he is going to use multiple PALs on a board (s)he
>>might take a look at CPLDs (sort of a super-PAL), which have a larger
>>capacity for logic and registers, plus the great majority can simply be
>>programmed while already soldered on the board through JTAG.
>>
>>I'm professionally biased towards Altera MAX devices, but there's a whole
>>bunch of other CPLD vendors that offer JTAG programmability.
>>
>>Best regards,
>>
>>
>>Ben
>
>
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Article: 82011Eric DELAGE <"eric UNDERSCORE delage AT yahoo DOT fr"> writes: >> Now, that doesnt mean the lawers want come after you, they can try at least. >> But by being VERY VERY Careful it is possible to make the case a 'no case' >> for the lawers. But you really have to have a 'clean implementation' - and >> you have to withstand any pressure from the lawers who try to prove the >> opposite. > > The keypoint, I think, is: are we talking about 1) patents (but the > ARM ISA is full of instructions developped before it appears) 2) > trademarks (but as long as no mention/no claim regarding the original > names are done, would it be ok?) 3) copyright (but if an ISA is a > language, an someone copyright it?) Point 1: As for MIPS, the unaligned load/store instructions (i think) are covered by patents. In order to implement these, you must obtain a license from MIPS technologies. Point 2: For trademark reasons you cannot call a processor for MIPS compatible or compliant, without implementing the full ISA. Goto point 1. (Infinite loop exception, program aborted). That hasn't stopped people from implementing processors with the MIPS ISA, *except* for the patented instructions. But the people doing this are very careful about not calling the processor for anything related to MIPS... Kai -- Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>Article: 82012
Hi, I have checked, Vcco, Vccaux, and Vccint are correct, other designs work fine. The input clk is 30 MHz and I have used this frequency before for all my other designs, and the chip can handle it. But the question is how come it works right when I toggle the WE signal. It works exactly like how you would expected it to. It's only when I have WE high for write then 0 the rest of the way, then it's didn't behave like the ModelSim Simulation, I am really confused!!! In my ucf file I didn't add any constraint to the signal. I don't see a reason to, but should I? Thanks, AnnArticle: 82013
I wrote: > But if there isn't a patent on an architecture, you don't need a license > to implement it. The purpose of the license is to grant you a right that > was taken away from the patent. If there's no patent, you haven't been > denied the right. ["from the patent" was supposed to read "by the patent"] Tobias Weingartner wrote: > No, you are wrong. I do not need a patent on my IP in order for me to > license it to you. It's called copyright. You can't copyright an idea. You can only copyright a specific expression of an idea. If you invent a new processor architecture, and publish the architecture specifications, copyright does not prevent me from designing my own processor compatible with your specifications. This is a very well- established principle of US copyright law, and AFAIK the copyright laws of most other countries work similarly. If you published Verilog code for your core, that could be copyrighted, and I wouldn't be able to use your Verilog code without a license, though I could still write my own. On the other hand, patents *do* protect ideas. If you patent a feature of your processor architecture, I can't use it without a license. If you have a patent that doesn't apply to the architecture, but only to a feature of your implementation (e.g., your Verilog design), I could either license that patent or try to figure out a different way to implement the architecture that didn't infringe your patent. For instance, if your processor architecture had an (unpatented) multiply-by-37 instruction, but you have a very clever patented multiply-by-37 circuit, and I didn't want to license your patent, I could still design my own processor compatible with your architecture by using a different (probably less clever) multiply-by-37 circuit.Article: 82014
"Alex Freed" <alexf@mirrow.com> writes: > "Ziggy" <Ziggy@TheCentre.com> wrote in message > news:XYS3e.131292$r55.32410@attbi_s52... > > Eric Smith wrote: > >. A reproduction of a 486 or base Pentium would > > be plenty for what i want to do. Careful with those quotes/attributions! Eric Smith didn't say any such thing!Article: 82015
Austin Lesea wrote:
> All,
>
> <snipped>
> One big advantage they have, is they have schematics, verilog, or
> VHDL, so they can simulate, and put together test benches.
>
> Without the schematics, or HDL, it is a very tough job to convert to
> anything at all.
>
> Austin
Right you are. Without the source, it is usually easier to start with a
clean sheet and design to the specifications. Having a device with the
original design in it but no source is only good for verifying the
design and perhaps for extracting the specification. I've been down
this road more than once, usually on legacy FPGA designs that no longer
have source and either need a "minor change" or need to be migrated to a
newer device family.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 82016Williams, By default, an IBUFG & BUFG are instantiated, but if you specify something like: wire dcmclkout; // synthesis attribute clock_signal of dcmclkout is true // synthesis attribute clock_buffer of dcmclkout is none the synthesis tool will not issue a clock buffer placement. i usually instantiate IBUFG & BUFG, for safety. hope this helps. Vladislav "williams" <stud_lang_jap@yahoo.com> wrote in message news:d02ff4ca.0504040358.600e560e@posting.google.com... > Hello Guys, > I had a doubt about the IBUFG and BUFG in xilinx. > 1.I have connected clock from oscillator to CLKG IO of the Xilinx. In > this case is it required to instantiate the IBUFG inside my code > also?. > 2. The DCM output is already BUFG i think and so is it required to > BUFG again in my code? > > Thanks and regards > WilliamsArticle: 82017
What if you route an IBUFG input pin to a regular BUF?...will the tools still treat it as global clock? "Jim George" <send_no_spam_to_jimgeorge@gmail.com> wrote in message news:J8udnYxr4psU1s_fRVn-1w@comcast.com... > williams wrote: > > Hello Guys, > > I had a doubt about the IBUFG and BUFG in xilinx. > > 1.I have connected clock from oscillator to CLKG IO of the Xilinx. In > > this case is it required to instantiate the IBUFG inside my code > > also?. > > 2. The DCM output is already BUFG i think and so is it required to > > BUFG again in my code? > > > > Thanks and regards > > Williams > > If you manually insert BUFGs and IBUFGs, the tools will not try to > insert another one, so put them in to make sure. Otherwise you can find > that later on, when your design becomes more dense, your clock can > suddenly be put onto longlines or even local routing. > > -Jim > > PS, I think your post belongs only on comp.arch.fpga, the others are for > language specific questions.Article: 82018
The "Create and Import Peripheral Wizard" (chapter 4: http://www.xilinx.com/ise/embedded/est_rm.pdf) is a good starting point. Use the skeleton files created as a starting point for your own custom core. An example device driver to access the custom core from the procossor is generated as well. Paul kittyawake@gmail.com wrote: > > I am trying to connect a custom IP to my MicroBlaze design. This custom > IP is connected to the OPB Bus. It reads data from MicroBlaze, performs > some computations and gives data back to the processor. I cannot figure > out how to write data into the custom IP or how to read data from that > IP. > > When we use Xilinx IP Cores, like GPIO, we are provided with functions > like XGpio_Read, XGpio_Write etc. How do we communicate with our custom > peripherals if we do not have such functions related to the custom > peripheral? Do you have to write these drivers or is it sufficient just > to make a wrapper for the custom peripheral so that all bus signals > match the signals of the top-level wrapper? > > I would really appreciate if someone could guide me to an appropriate > document or list out the steps of how to do this. > > ThanksArticle: 82019
Can an FPGA have two JTAG ports for programming an FPGA chip? One is conected thro XCf02s to the FPGA and the other is directly connected to the FPGA (XC3S400). What is the significance of having two ports? What files are used for programming this FPGA thro each of those ports?Article: 82020
The reason the problems exist is that your I/O isn't valid. Bottom line, if you have bad input, you'll probably get bad output. If your write enable has some "reason" to be 1.2V logic high for LVCMOS33, toggling the signal low then high will present a higher voltage until the signal again reaches a DC level of 1.2V. You get a valid state for a short amount of time before you get an invalid. Show me why the I/O are not giving valid digital levels and you'll find why your design isn't "working." "Ann" <ann.lai@analog.com> wrote in message news:ee8d229.11@webx.sUN8CHnE... > Hi, I have checked, Vcco, Vccaux, and Vccint are correct, other designs work fine. The input clk is 30 MHz and I have used this frequency before for all my other designs, and the chip can handle it. But the question is how come it works right when I toggle the WE signal. It works exactly like how you would expected it to. It's only when I have WE high for write then 0 the rest of the way, then it's didn't behave like the ModelSim Simulation, I am really confused!!! In my ucf file I didn't add any constraint to the signal. I don't see a reason to, but should I? Thanks, AnnArticle: 82021
"Eric DELAGE" <"eric UNDERSCORE delage AT yahoo DOT fr"> skrev i meddelandet news:4252ccf3$0$3139$8fcfb975@news.wanadoo.fr... > larwe@larwe.com wrote: > > > >>Are ISA covered by patents or trademarks? Is it allowed to develop a > >>processor core for a popular ISA as long as no reference is made to > > > > any > > > > Depends on the ISA. ARM, for instance, is covered by thick IP > > protection layers, and is vigorously defended. 8051, not so much :) > > > W/ ARM for instance, I understand that they can protect their IP > implementation w/ patents or copyrights but what would be the lawwhich > prevent someone from implementing a processor core running an ARMv5? > You protect an ISA by patenting some special thing which is required to implement the ISA. I happen to think that the ARM Thumb patent is a load of rubbish. The basis of the patent is the "ARM Ltd discovery" that less code is better than more code. Code compression for RISC is mentioned already in the original RISC paper by Katevenis. > Eric -- Best Regards Ulf SamuelssonArticle: 82022
> What is the significance of having two ports? i think one of them are to config the FPGA and the other is an soft jtag you use to program embedded softcore uC with. KasperArticle: 82023
Repzak wrote: >>What is the significance of having two ports? > > i think one of them are to config the FPGA and the other is an soft jtag you > use to program embedded softcore uC with. > > Kasper > > or use JTag instruments or any fancy things clever guys do today. Temento for example is embedding PSL assertions and can keep an eye on them in real time (they can usually use the stndard JTag too). Altium does use two JTag ports, one being dedicated for their instruments / debuggers. The JTag FSM isn't that difficult ;-)Article: 82024
Synplify projects are in fact Tcl scripts. So you might write a MIF parser in Tcl (easy) and write down a synthesizable vhdl Rom table (entity). I did this in C for a DDFS. Probably free on my website. Bert Cuzeau
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