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In order to keep costs down and since most users already have a download/programming cable we don't ship them with our boards. We do disclose this on our ML40x product pages http://www.xilinx.com/ml401 You can not program through a serial null modem or a generic USB cable. You will need to buy a parallel cable (PC-4) or the new Platform USB cable. One other alternative if you have the ML40x board that includes the System ACE controller and a compact flash card you can create a new ACE file and write it, in the appropriate place, to the compact flash card using your PC. Ed p.s. Why are you using a fake email address that points to a Xilinx address? Most people just insert a nospam add on to slow down the spam. R!SC wrote: > Hi i have buy, > > virtex 4 evalutation board. In the box there isn't any cable for the > bitstream download. > > Can i download with impact the fpga bitstream with serial null modem cable > or usb cable? > > ThaNKS > bss > >Article: 82351
"Preben Holm" <64bitNOnoSPAMno@mailme.dk> wrote in message news:425a9590$0$79454$14726298@news.sunsite.dk... > Hi, > > I have an A/D-converter attached to my Spartan3 starter kit, running at > 100Mhz Maximum speed. > > But the A/D converter only has valid data 7 ns after the rising clock > edge and until 2ns after the next rising clock edge? > Where should I sample running a low-frequent sampling of fx. 10 MHz? > Preben, The IOBs have an optional delay element. RTM. If you use this with the IOB input flip-flop, you eliminate pad-to-pad hold time. Cheers, Syms.Article: 82352
I encountered the following problem in a design of a reprogrammable processing device. Not to go into to much detail : I use PLB IPIF to connect custom cores on a PLB bus, transfers in between them and from/towards workstation are controlled by the PPC, master of this bus ... all IPIFs are slave only implemented now since each IPIF implements FIFOs as buffer in between the core and the bus, i need to know if it possible to retreive from these FIFOs more then one data word without actually popping the data. At first my design implemented an intermediate buffer, so if i wouldn't be able to send data because of to little space at a certain time to a certain destination, it could have been buffered. This design i cannot make anymore, since I didn't succeeded in implementing a ddr sdram for my board. I could use BRAM but i want to save it for the cores performing the algorithms. Since I encapsulate my data on which an algorithm needs to be performed with headers and the first header serves for a device on which this PPC-IPIF system connects, the second dword is used for telling the PPC performing transfers the destination(s) of the data encapsulated by it. Therefor i need to extract all the headers withouth popping them, since i need a solution where they are not stored intermediate. thx, PaoloArticle: 82353
> You can fit yourself if you are very good with a soldering iron but beware as the resistor sites > are 0201 size. 0201! I thought 0402 was bad, 0201 must be like dust. I presume components this size remove all the headache of decoupling/ terminating BGA designs, but are they easy to get hold of, and where do you source them in the UK (they're not in the RS catalogue :-( ). Nial.Article: 82354
Hi, I have now my first layout of my lcd state machine ready. Any comments and hints are welcome. regards, Benjamin entity lcd is port ( clk : in STD_LOGIC; Rst : in STD_LOGIC; LCD_da : out STD_LOGIC_vector(7 downto 0); LCD_en: out STD_LOGIC; LCD_re: out STD_LOGIC ); end lcd; architecture Behavioral of lcd is signal x: std_logic; signal arg : std_logic; type Zustaende is (init1,init2,init3); signal akt_zustand,naechster_zustand:Zustaende; signal sending,go_send:std_logic; --signal count: integer; begin NZ:process(akt_zustand,arg) begin case akt_zustand is when init1 => naechster_zustand<=init2; when init2 => naechster_zustand<=init3; when init3 => naechster_zustand<=init1; end case; end process; Z:process(clk,rst) begin if sending = '1' then akt_zustand <= akt_zustand; -- wait if still sending elsif rst='1' then akt_zustand<=init1; elsif clk'event and clk='1' then akt_zustand<=naechster_zustand; end if; end process; A:process(akt_zustand) begin if sending = '0' then -- don't change outputs if they are already set (otherwise go_send would never go 0) case akt_zustand is when init1 => x<='0'; LCD_re <= '0'; go_send <= '1'; when init2 => x<='0'; LCD_re <= '0'; go_send <= '1'; when init3 => x<='0'; LCD_re <= '0'; go_send <= '1'; end case; end if; end process; sendbyte:process(go_send) begin if go_send = '1' then sending <= '1'; LCD_en <= '1'; --- wait for some CLKs maybe I have to use a counter here... LCD_en <= '0'; sending <= '0'; go_send <= '0'; end if; end process; end Behavioral;Article: 82355
Hi, http://www.enterpoint.co.uk/moelbryn/broaddown2.html this board looks nice, also the price is okay... regards, BenjaminArticle: 82356
Why don't you get it at : http://www.alse-fr.com/English/ips.html Free, works very nicely, and does a lot of the ugly and slow sequency required by these old drivers. Bert Cuzeau Benjamin Menküc wrote: > Hi, > > I want to write an interface in vhdl for a HD44780 LCD Controller. What > is the best methodology to do that? Moore-Automat? How should I realize > the neccessary wait operations? Especially the initialization of the LCD > requires about 7 steps to be performed in order with some waits in > between.... > > regards, > BenjaminArticle: 82357
Benjamin Menküc wrote: > Hi, > > does anybody know where to find code for the 2-line lcd? For now I want > to talk to the lcd without any processor (no EDK). > > regards, > Benjamin Why don't you get it at : http://www.alse-fr.com/English/ips.html Free, works very nicely, and does a lot of the ugly and slow sequency required by these old drivers. Bert CuzeauArticle: 82358
> Preben, > The IOBs have an optional delay element. RTM. If you use this with the IOB > input flip-flop, you eliminate pad-to-pad hold time. Thanks, but I guess it's quite more than I've learned so far during courses! What is pad-to-pad holdtime? How do I setup the delay element? Input flip-flops are these any different from other flip-flops? I have an idea about some constraint-editor may be able to help me out here, but searching the net gives me nothing! Thanks PrebenArticle: 82359
Recent version of Quartus do not support user defined libraries. The only way is to add each file to the project separately (you can, of course, write a small tcl script that automates this task). Avishay Orpaz. Clemens Hermann wrote: > Hi, > > with the latest quartus II software I created two VHDL packages. After > testing the packages I wanted to combine them in a custom VHDL library > with no success. My goal is to have a directory that contains the > library (preferrably precompiled) so that I can pass it around and it > could be used by others as simple as the standard VHDL libraries (e.g. > ieee) like > > LIBRARY my_lib; > USE my_lib.package1.all; > USE my_lib.package2.all; > > without adding each single VHDL file the packages are based on. > > Any pointer to information or hints how I could get things up and > running would be a great help. > > thanks in advance, > > /chArticle: 82360
Hi,
I want to set the load input for a counter to 1 and set it at the next
clk automatically back to 0.
But I get this error: ERROR:Xst:528 - Multi-source in Unit <lcd> on
signal <load>
Sources are:
Signal <load> in Unit <lcd> is assigned to GND
this is my code:
a1: process (state) -- output-routine of a state machine
begin
if state = init1 then
load <= '1';
end if;
end process;
a2: process (clk)
begin
if clk'event and clk = '0' then -- falling edge
if load = '1' then
load <= '0';
end if;
end if;
end process;
Thanks for your help.
regards,
Benjamin
Article: 82361Hi, very nice, that is exactly what I am looking for. Thank You! regards, BenjaminArticle: 82362
Hi Clemens, > with the latest quartus II software I created two VHDL packages. After > testing the packages I wanted to combine them in a custom VHDL library > with no success. My goal is to have a directory that contains the > library (preferrably precompiled) There is no way Quartus can precompile a package (or a design entity) because it has to elaborate the package everytime it is being used. Thus, you will always have to keep the source code accessible. There's ways to encrypt the source code, but you will have to either use a code obfuscator or become part of Altera's AMPP program in order to encrypt the code in a way that Quartus can understand, but the rest of the world can't. > so that I can pass it around and it > could be used by others as simple as the standard VHDL libraries You could use a library directory and add this directory to your project. However, I don't believe the current versions support automatic filename inferencing for packages (i.e. if your package is called my_pkg, it will try to find my_pkg.vhd). Also, the current version always compiles into library "work". As long as there's no namespace conflicts this is quite workable, but not quite what the LRM specifies. I have heard that version 5.0 will support named libraries. Whether 5.0 also does automatic package filename inferencing is unclear to me. Hmmm.... would definitely be a wannahave... Quartus II 5.0 is due out early May, so let's just wait and see. Best regards, Ben Twijnstra SascoArticle: 82363
Hi Andrew Holme, > In the MAX7000S datasheet, it says the I/O pins are tri-stated and > (weakly) > pulled-up, to avoid board conflicts, during programming. What should the > state of the I/O pins be _before_ programming? I have a sample EPM7128S > device here which appears to be pulling them low - but it also fails the > blank test, so I think it must have been programmed. How should a > brand-new part behave? There's some internal bit in the MAX7000A and later that says that the device contains a valid configuration. If this bit is not set, the device remains in tristate. In the MAX7000S, this bit is not present, but if the device is blank, it should still stay in slightly-pulled-up-tristate. Only if the device is not blank (this does _not_ mean that it has a _valid_ configuration), it will go out of tristate and do something. Blank that sample and see what happens ;-) Hope this helps. Best regards, BenArticle: 82364
You cannot assign values to the same signal in two different process's as they are evaluated concurrently. Change your code to evaluate the "load" signal in the same process.Article: 82365
Hi, kittyawake@gmail.com wrote: > I also have an interrupt controller in my system.If I include the > xmdstub then wont it overwrite my interrupt handler which is at > 0X00000010?I read somewhere that xmdstub is 800 bytes and starts from > 0x00000000 memory location.How does this work then? > Does anyone has experience in dealing with a system in which microblaze > will have several interrupts through the OPB_INTC?I am having hard time > figuring out what exactly the INTC sends to the microblaze when it gets > an interrupt request. xmdstub is a software-intrusive tool, and has certain limitations as a result. Unless you are really tight on logic, I recommend following Paul Hartke's earlier suggestion to use the MDM hardware debug capability. It's totally non-intrusive, and makes it trivial to debug otherwise difficult situations like interrupt handlers and so on. It will maybe take you a couple of hours to integrate MDM into your system and learn the (very) slightly modified development/debug flow that results, but after that you will never look back. Regards, JohnArticle: 82366
Benjamin Menküc wrote: > I want to set the load input for a counter to 1 and set it at the next > clk automatically back to 0. > But I get this error: ERROR:Xst:528 - Multi-source in Unit <lcd> on > signal <load> > Sources are: > Signal <load> in Unit <lcd> is assigned to GND > > this is my code: > > a1: process (state) -- output-routine of a state machine > begin > if state = init1 then > load <= '1'; > end if; > end process; > > a2: process (clk) > begin > if clk'event and clk = '0' then -- falling edge > if load = '1' then > load <= '0'; > end if; > end if; > end process; Well - the reason you can't do that is that you can't have multiple processes writing to the same signal in VHDL (Unless of course you have a tristate bus) - both these processes are executed in parallel. One way (in pure language terms) to express what you are trying to express is: a: process(state,clk) begin if state = init1 then load <= '1'; elsif rising_edge(clk) then if load = '1' then load <= '0'; end if; end if; end process; This is close to what you attempted to express - the difference being that if state = init1 and rising_edge(clk) are simulataneously true, then the behavior is defined. Whether or not this is a good idea (probably not) is entirely another question - it's a synchronous D flip-flop with asynchronous reset. It is usually much better to stick to purely synchronous design, as asynchronous designs tend to break unless you know exactly what you're doing (And then they may just break anyway). One hazard with the code above is that if the state signal changes too close to a clock edge, then the output may go metastable, or if routed to multiple sinks, may resolve to different values at each endpoint. I'm guessing you need to restructure your code. Jeremy.Article: 82367
"Preben Holm" <64bitNOnoSPAMno@mailme.dk> wrote in message news:425ae804$0$79456$14726298@news.sunsite.dk... > > Thanks, but I guess it's quite more than I've learned so far during courses! > > What is pad-to-pad holdtime? > How do I setup the delay element? > Input flip-flops are these any different from other flip-flops? > > I have an idea about some constraint-editor may be able to help me out > here, but searching the net gives me nothing! > Search harder! Look for xapp133 "input delay properties" Good luck, Syms.Article: 82368
>if falling_edge(clk) then > adtemp <= adin; > end if; > > if rising_edge(clk) then > addata <= adtemp; > end if; This is (as I know) definitely not a good idea. You cannot using both the edges of a clock in evaluating. Somebody please correct me if I am wrong. Thanks.Article: 82369
Here's the link: http://www.xilinx.com/ise_eval/index.htm Eric Smith wrote: > leexiaofat@eyou-dot-com.no-spam.invalid (leexiaofat) writes: > >>is there anybody knows? > > > You can order it from Xilinx.Article: 82370
Hello, does anyone know a good website that has examples of verilog programs you can implement on FPGA's. I have implemented basic programs that use the LED's, switches and push buttons. However, I am looking for verilog programs that can show me how to utilise the I/O expansion sockets, VGA connector and the 7 segment digital display.........Cheers !!!!!!!!!Article: 82371
Thanks for the posts, tips , and help. Great articles and web site links. Very much appreciated. Jason "Symon" <symon_brewer@hotmail.com> wrote in message news:425708f8$1_1@x-privat.org... > "Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message > news:qqD5e.26388$Fy3.1624833@news20.bellglobal.com... > > Then am I to assume that the capacitors on the underside of the PCB share > > the power and ground vias with the FPGA power and ground vias, or do the > > capacitors have their own power and ground vias. I always assumed that it > > was a "no no" to use the vias from the BGA power ground for the > > capacitors? > > > Hi Jason, > Absolutely, it's a "yes yes" to share the vias for the BGA grounds/power > with the bypass caps. It works great. > Another site you might be interested in is > http://www.sigcon.com/pubsIndex.htm > Click on 'bypass capacitors' for some interesting stuff. This article shows > where to put your vias relative to the capacitors. > http://www.sigcon.com/Pubs/news/6_09.htm > Best, Syms. > > >Article: 82372
The examples you are looking for would have to be specific to the board you are using and you haven't told us that. DerekArticle: 82373
"Pi" <hoebenNOSPAM@bigfoot.com> wrote in message news:mdoi519beqigig4jovkobaecd3738ftbnc@4ax.com... > On 08 Apr 2005 12:53:25 -0700, Eric Smith <eric@brouhaha.com> wrote: > > >Ray Andraka wrote about reverse-engineering ASICs based on behavior vs. > <snip> > >Can anyone recommend a lab that will do this, and take photomicrographs, at > >a "reasonable" price? > >Before everyone jumps on me about piracy, I'll explain that the ROM > >and PLA code in question is NOT copyrighted. > > So why not look at what they do, the functionality and re-create it > with new parts? That way you avoid legal problems. > > Regards, > Pieter I think maybe IDC in Arizona, (Phoenix), and MOSAID used to do a lot of this delayering and taking picture stuff. Else, anybody that is in the Failure Analysis business for Semiconductors. Lucky for you these are from a vintage that makes it conceivable to me. Doing what the chinese probably did to that crypto equipment on something modern is way beyond my scope. delArticle: 82374
My problem has been fixed http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=21168 Ross
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