Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 83025

Article: 83025
Subject: JTAG and SPROM for Spartan II-e
From: aosik5@gmail.com
Date: 21 Apr 2005 14:16:28 -0700
Links: << >>  << T >>  << A >>
I'm currently laying out a PCB containing a Spartan II-E (XC2S200E
PQ208).  I'm laying out the circuitry for an SPROM chip to store my bit
file, but due to time constraints I would like to be able to program
the chip using the JTAG interface (similiar to the one on the
development board I am using, a Digilent development board from
NuHorizons) in case, due to time constraints, I am unable to program
the SPROM before a presentation.

I'm familiar with the way the JTAG cable works but am a little confused
as to how the four pins (TMS TDI TDO TCK) interact with the FPGA.
Based on my knowledge, I am assuming that the four pins are wired one
to one with the corresponding FPGA input pins (and one output).  The
board I'm using has a parallel port to JTAG interface which makes
tracing the port routes confusing.  I really only have one or at most
two shots at the PCB so I was just wondering if the JTAG pins can be
wired directly to the FPGA, no buffer chip or anything in their way.

Thanks!

George


Article: 83026
Subject: Re: CAM for FPGA ...
From: "John_H" <johnhandwork@mail.com>
Date: Thu, 21 Apr 2005 21:30:47 GMT
Links: << >>  << T >>  << A >>
Note that Altera has or had CAM functionality for 16 or 32 words at a time
in their memories starting in the 20K family.  That size was never
interesting for my applications so I didn't pursue them.

If you use a BlockRAM with a counter, you're going to have a maximum delay
of the number of entries in the RAM before a match: much, much longer than
commercial CAMs.

Hash tables or dictionaries built from parts of the value and pointers to
other values in a search tree can reduce your search times but they aren't
simple.

1) If you want a 1kx64 CAM, I'd suggest the FPGA isn't the way to go.  2)
Look at Altera's CAM functionality.  3) If you want small CAMs or have lots
of FPGA space, let us know.  We can't devine your requirements from the CAM
"idea" you're asking about.




Article: 83027
Subject: Re: Xilinx Impact in Linux 2.6.x
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Thu, 21 Apr 2005 21:40:34 +0000 (UTC)
Links: << >>  << T >>  << A >>
Trond Egil Gran <nospam@for.me> wrote:
> Have anyone got Impact working in Fedora Core 3? Or any similar Linux?

> I have tried this:

> http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm

> but I probably get 1000 compile errors.

> Is there any other possibilities for programming xilinx FPGA's?
> I have read about NAXJP but can't find any places to download it,
> I have tried http://www.nahitech.com/nahitafu/naxjp/naxjp-j.html#down
> but can't find any links to click on to download it. I'm using a spartan
> 2E at the moment.

Try
http://www.rogerstech.force9.co.uk/xc3sprog/

XC2S should work too.


> Why don't just Xilinx program against the parallelport in user-space
> (ppdev) Instead of having two drivers??

Or if Xilinx would publish an interface to adapt one's own Jtag interfaces...

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 83028
Subject: Re: Xilinx Impact in Linux 2.6.x
From: "dlharmon" <mail@dlharmon.com>
Date: 21 Apr 2005 14:45:45 -0700
Links: << >>  << T >>  << A >>

Trond Egil Gran wrote:
> Have anyone got Impact working in Fedora Core 3? Or any similar
Linux?
>
> I have tried this:
>
> http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm
>
> but I probably get 1000 compile errors.
>
> Is there any other possibilities for programming xilinx FPGA's?
> I have read about NAXJP but can't find any places to download it,
> I have tried http://www.nahitech.com/nahitafu/naxjp/naxjp-j.html#down
> but can't find any links to click on to download it. I'm using a
spartan
> 2E at the moment.
>
> Why don't just Xilinx program against the parallelport in user-space
> (ppdev) Instead of having two drivers??
>
>
> TEG


Check out XAPP058. It describes how to program the FPGA with a
microcontroller.  Should be simple to create a program to do this via
the parallel port.  There is a schematic for the cable on the Xilinx
web site.

I have not used the method in XAPP058, but have loaded a Spartan 3 by
using slave serial and a microcontroller.  It really works well.  It is
convenient too since the microcontroller has ethernet.

Darrell Harmon
http://dlharmon.com/sbc.html


Article: 83029
Subject: Looking for a RocketIO expert in Ottawa, ON
From: "MM" <mbmsv@yahoo.com>
Date: Thu, 21 Apr 2005 18:00:42 -0400
Links: << >>  << T >>  << A >>
Just as the subject says I am looking for someone local who has experience
in using RocketIO and possibly Aurora protocol for simple data streaming.
This is a contract position.

Thanks,
/Mikhail



Article: 83030
Subject: Re: CAM for FPGA ...
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 21 Apr 2005 15:19:45 -0700
Links: << >>  << T >>  << A >>
John_H wrote:
> Note that Altera has or had CAM functionality for 16 or 32 words at a time
> in their memories starting in the 20K family.  That size was never
> interesting for my applications so I didn't pursue them.

Nor did anyone else.
The function was dropped after the 20K.

> We can't devine your requirements from the CAM
> "idea" you're asking about.

Yes, "getting into a CAM design for FPGA" is a little unfocused.

       -- Mike Treseler

Article: 83031
Subject: Re: CAM for FPGA ...
From: Thomas Womack <twomack@chiark.greenend.org.uk>
Date: 21 Apr 2005 23:27:16 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <bYU9e.32$jt6.335@news-west.eli.net>,
John_H <johnhandwork@mail.com> wrote:
>Note that Altera has or had CAM functionality for 16 or 32 words at a time
>in their memories starting in the 20K family.  That size was never
>interesting for my applications so I didn't pursue them.
>
>If you use a BlockRAM with a counter, you're going to have a maximum delay
>of the number of entries in the RAM before a match: much, much longer than
>commercial CAMs.

That's why I was proposing using lots of blockRAMs with a counter;
given that the cycle times for block RAM are so much shorter than the
ones I see for commercial CAMs, the trade-off might be less completely
hopeless than you'd fear; the catalogue in

http://www.music-ic.com/index.php?section1=products&section2=function

has a lot of CAMs with a compare time as long as 90ns, in which time
you can look up quite a lot of entries in quite a lot of block RAMs in
parallel..

Tom

Article: 83032
Subject: Re: Xilinx Impact in Linux 2.6.x
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 21 Apr 2005 15:38:01 -0700
Links: << >>  << T >>  << A >>
Does the Platform USB cable help? $149 ;-(
http://www.xilinx.com/bvdocs/ipcenter/product_brief/usb_cable_overview.pdf



Article: 83033
Subject: Re: VHDL or Verilog
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Apr 2005 19:14:21 -0400
Links: << >>  << T >>  << A >>
Clemens Hagen wrote:

>Hello
>
>I have a very basic question. Normally you have the choice if you want to 
>use VHDL or Verilog for
>describing you hardware architecture. I would be interested when do you 
>decide for VHDL and when for
>Verilog. Are the special cases when it makes more sense to use one or the 
>other language?
>
>Thanks for helpful tips
>
>Clemens 
>
>
>  
>
Muslim or Christian.  Normally you have the choice of which you want to 
follow.....

Choice of HDL boils down mostly to a religious argument.  Both have 
their plusses and minusses.  Either will work fine for straight RTL 
coding.  VHDL is more structured, and as a result is more verbose.  The 
structure and verbosity bother some folks.  Verilog is less precise, so 
although easier to code, it can let things slip through that are perhaps 
harder to find during integration.  Verilog is also somewhat clumsy for 
generates with placement, but then the average designer doesn't do 
that.  I use mostly VHDL because of the structural generation nature of 
a large portion of my work. 

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 83034
Subject: Re: Unconstrained ports for synthesis
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Apr 2005 19:18:27 -0400
Links: << >>  << T >>  << A >>
Mohammed A khader wrote:

> Hi all,
>
> I am having a component Multiplier with unconstrained ports. But this
>is not my top_level_entity and ports are implicity constrained while
>instanciating this component.
>
> It simulates well but while synthezing Quartus says that ports must be
>constrained. I think that Quartus could infer it from instanciation
>syntax. Is there any solution to get around it
>
>Thanks.
>
>-- Mohammed A Khader.
>
>  
>
I do not believe the Quartus compiler supports unconstrained ports.  
Either use generics to size the port, or use a synthesizer such as 
synplify that does support unconstrained ports.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 83035
Subject: Re: JTAG and SPROM for Spartan II-e
From: "Gabor" <gabor@alacron.com>
Date: 21 Apr 2005 16:51:53 -0700
Links: << >>  << T >>  << A >>

aos...@gmail.com wrote:
> I'm currently laying out a PCB containing a Spartan II-E (XC2S200E
> PQ208).  I'm laying out the circuitry for an SPROM chip to store my
bit
> file, but due to time constraints I would like to be able to program
> the chip using the JTAG interface (similiar to the one on the
> development board I am using, a Digilent development board from
> NuHorizons) in case, due to time constraints, I am unable to program
> the SPROM before a presentation.
>
> I'm familiar with the way the JTAG cable works but am a little
confused
> as to how the four pins (TMS TDI TDO TCK) interact with the FPGA.
> Based on my knowledge, I am assuming that the four pins are wired one
> to one with the corresponding FPGA input pins (and one output).  The
> board I'm using has a parallel port to JTAG interface which makes
> tracing the port routes confusing.  I really only have one or at most
> two shots at the PCB so I was just wondering if the JTAG pins can be
> wired directly to the FPGA, no buffer chip or anything in their way.
>
> Thanks!
>
> George

The Xilinx Platform Flash data sheet shows the connections required.
TMS, and TCK are wired in parallel to all devices in the JTAG chain.
TDI and TDO form a loop where the TDO of each device in the chain
connects to the TDI of the next device.  Normally the SPROM is in the
chain before the FPGA it programs, but this isn't necessary.  The
Platcorm Flash datasheet also shows the serial connections from the
SPROM to the FPGA for boot time loading in master serial mode.

See figure 8 in:
http://direct.xilinx.com/bvdocs/publications/ds123.pdf


Article: 83036
Subject: Re: FIFO as a Logic Analyzer; Clock synthesizer
From: "Len" <LeonardGabrielson@adelphia.net>
Date: 21 Apr 2005 16:55:39 -0700
Links: << >>  << T >>  << A >>
Re the clock:  If you're going to put a processor in the project that's
I2C capable, use the AD9834 to divide down a nice high frequency
oscillator to any frequency you want.  Analog Devices has a web tool to
help you get the hang of programming it, and it's a GREAT chip!

http://www.analog.com/Analog_Root/static/techSupport/designTools/interactiveTools/ad98334/ad9834.html

Good luck!
Len


Article: 83037
Subject: Re: PPCs sharing an OCM BRAM
From: "Joseph" <joeylrios@gmail.com>
Date: 21 Apr 2005 17:06:57 -0700
Links: << >>  << T >>  << A >>
Not yet.  There is no custom logic whatsoever, so I didn't bother.  It
seemed that poking around with XMD would be sufficeint debugging until
I added custom blocks.

Joey


Article: 83038
Subject: Re: Spartan 3E slower that Spartan 3?
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Apr 2005 20:22:10 -0400
Links: << >>  << T >>  << A >>
austin wrote:

>
> If folks are looking for blazing speed, then I suggest they look at 
> Virtex 4. 
>
> Austin

Not for arithmetic in the fabric if you believe the speed files (and I 
have to):

parameter                V2Pro -7         V4sx55-10 (slice L)   (slice M)
topcyf                     560-731            460-572                  
   465-576
tbyp                           73                     98               
                  98     
tdick                       174-208            299-1053               
    293-1162

Time to get on the carry chain is a little faster, but time per bit 
(tbyp) is 30% slower and time to get off the carry chain is 200+% 
slower.  Xilinx says use DSP48  adders for anything over about 12 bits.  
Yes, that makes the design faster, but there is not nearly enough adders 
this way, and unless you need a mult in front of your add, you throw 
away one of the multipliers.  Real world DSP designs have more than just 
multiply accumulates.  More typically, there is an order of magnitude or 
more difference in the number of multipliers vs the number of adders.  
I'm currently working a  design that  illustrates the slow down in the 
carry chain in a way that really hurts.  In this case, it is a 
beamforming receiver that needs nearly all the multipliers, plus needs 
to do a large number of adds, which are forced to be in the fabric.  The 
achievable clock speed is no greater than the V2Pro version of the 
design because of this carry chain slow down.  In order to be used as a 
350+ MHz device, BOTH the fabric and the DSP48's have to be able to work 
at those speeds, and for realistic designs, that includes arithmetic in 
the fabric.

Austin, please tell me that these numbers are going to improve 
substantially and soon.  It is really dissappointing to see the carry 
chains lose performance despite the shift to 90nm.  Being that this is a 
real design, not a lab exercise, I have to use the results of the timing 
analyzer (which means the speed file numbers are treated as gospel as 
far as the customer is concerned) to get the design past the review.




-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 83039
Subject: Re: FIFO as a Logic Analyzer; Clock synthesizer
From: Eric Smith <eric@brouhaha.com>
Date: 21 Apr 2005 17:30:34 -0700
Links: << >>  << T >>  << A >>
TPM wrote:
> Moreover, what is the cheapest way to produce a variable clock speed
> up to 166MHz (and possibly beyond, for other applications)?  A PLL?
> Any chip you may suggest me?

Larry Amontec wrote:
> Why not a CPLD or FPGA. And do your own frequency synthesizer using an
> accumulator. For high speed accumulator, use pipeline methodology.

Leonard Gabrielson wrote:
> Re the clock: If you're going to put a processor in the project that's
> I2C capable, use the AD9834 to divide down a nice high frequency
> oscillator to any frequency you want.

Both suggestions are DDS (Direct Digital Synthesis).  That's great for a
lot of things but not so great for producing high frequency square
waves.  For that, you're much better off with a PLL.  You might try the
Cypress CY22150 or CY22393/4/5 programmable clocks.  They're fairly
inexpensive, and available from Digikey.

	http://tinyurl.com/923g2
	http://tinyurl.com/dyden

For the CY22150, they have a nifty little "Licorice" demo board (CY30700),
that only costs $20.

Eric
	

Article: 83040
Subject: Re: PPCs sharing an OCM BRAM
From: "Joseph" <joeylrios@gmail.com>
Date: 21 Apr 2005 17:55:51 -0700
Links: << >>  << T >>  << A >>
Well, it turns out that I didn't hook the reset or clk signals up to
the 2nd DOCM bus (the first one was set up automatically by the Base
System Builder).  For *some* reason it didn't want to work without a
clock--touchy little bus, huh?  : )

Thanks for the read/response, Paul.  And thanks to anyone who spent any
time reading this... I am sure I will be back before too long...

Joey


Article: 83041
Subject: Re: source control and Xilinx ISE 6 and 7
From: Ray Andraka <ray@andraka.com>
Date: Thu, 21 Apr 2005 23:28:13 -0400
Links: << >>  << T >>  << A >>
Eric Smith wrote:

>"Andy Peters" <Bassman59a@yahoo.com> writes:
>  
>
>>I think you misunderstand my question, which is: what files are
>>necessary and what files are cruft?
>>    
>>
>
>Your Verilog and/or VHDL files, and your UCF files are necessary.  Anything
>else that you create yourself is necessary.  All those things should be
>checked into your repository.
>
>Everything that is generated by the tools should not be checked into
>the repository.
>  
>
I put the NCD and the generated bitstream in the repository.  The ncd 
because it makes guided revisions possible, as well as getting into the 
editors, and the bitstream because it is a deliverable with a date on it.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 83042
Subject: Re: VHDL or Verilog
From: Erik Walthinsen <omega@pdxcolo.net>
Date: Thu, 21 Apr 2005 20:32:21 -0700
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> Muslim or Christian.  Normally you have the choice of which you want to 
> follow.....

I find my self speechless, shocked that this thread hasn't deteriorated 
into a lengthy battle of people talking past each other, calling names 
and so on.

What's wrong with this group?  Am I on the wrong Usenet???

<g>

Article: 83043
Subject: Timing Reports Xilinx.....Max. freq of operation?
From: "CODE_IS_BAD" <Puneetsingh81@gmail.com>
Date: 21 Apr 2005 22:24:36 -0700
Links: << >>  << T >>  << A >>
Hi all...
 After i synthesize my code i get the following timing reports in my
synthesis report file.

   Minimum period: 11.536ns (Maximum Frequency: 86.685MHz)
   Minimum input arrival time before clock: 22.952ns
   Maximum output required time before clock: 7.829ns
   Maximum combinational path delay: No path found

 Now it says maximum frequency as 86.685 MHz.
 But at the same time the minimum i/p arrival time before clock is
22.952 ns. So in this case what will be my maximum clock frequency of
operation ?
 Also can anyone explain the significance of all the tree timing
parameters listed above. That will b of some help to me. Thanx a lot.
puneet


Article: 83044
Subject: Re: Simulation in modelsim.... Multiple Drivers.......
From: Klaus Falser <kfalser@durst.it>
Date: Fri, 22 Apr 2005 09:15:49 +0200
Links: << >>  << T >>  << A >>
In article <1114097509.171256.192550@z14g2000cwz.googlegroups.com>, 
Puneetsingh81@gmail.com says...
> hello Brijesh...
>    yes yaar i have already done that... But i wanted to know wether
> there is any mechanism with which we can also u know 'deposit' values
> instead of 'freezing' it as we do in modelsim. Waise thanx again for
> the suggestion.
> 
> Puneet
> 
> 
In a VHDL testbench there is no concept of "deposit" or "freeze".

Your testbench has to simulate the behavior of the other 
participants to the data bus.
This means, the testbench has to drive the bus with something 
like "3B" when it wants to write to the data bus.
Immediately after the DUT (device under test = your code you want to 
test) has read the data or at least shortly before your 
DUT has to write the bus itself, the testbench must free the bus  
by tri-stating the testbench (writing 'Z' to the bus).
This follows exactly the behavior of the electronics, your testbench 
has to write 'Z' to the data bus when the electronic of the other bus 
participants disables their output drivers.
The exact time this tri-stating is done depends on the electronic you 
want to simulate.

Klaus

Article: 83045
Subject: Re: Xilinx ISE Warning: FF/Latch <> is unconnected in block <>
From: Klaus Falser <kfalser@durst.it>
Date: Fri, 22 Apr 2005 09:21:02 +0200
Links: << >>  << T >>  << A >>
In article <4267a83b$1@e-post.inode.at>, nospam@nospam.com says...
> Hi there,
> 
> I created a CPLD design which works perfect in simulation, but does not work
> in hardware. There are many warnings from the Xilinx ISE looking like
> 
> WARNING:Xst:1291 - FF/Latch <Sig> is unconnected in block <Blck>.
> 
> or
> 
> WARNING:Xst:1710 - FF/Latch  <Sig> (without init value) is constant in block
> <Blck>.
> 
> These come up only in the Low Level Synthesis processing step. There is one
> relevant solution record on the Xilinx website (see
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18396)
> with the following suggestion:
> 
> >> When this warning occurs, a register or latch in your design has been
> created, but the output is never connected or the signals or logic it drives
> have been trimmed. Check the XST log for messages such as the following to
> find signals that have been trimmed out of the design:
> 
> "WARNING:Xst:646 - Signal <my_sig> is assigned but never used." <<
> 
> However, there are no such warnings in my XST log.
> 
> Any help would be appreciated.
> 
> Christian
> 
> 
> 

If working with ISE/Webpack 7.1, did you apply the the patch 21168?

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=21168  

Best regards
Klaus

Article: 83046
Subject: Re: Bug in DDR template in Lattice FPGAs ?
From: ALuPin@web.de (ALuPin)
Date: 22 Apr 2005 00:25:58 -0700
Links: << >>  << T >>  << A >>
OK, maybe my question was not clear enough, one more try:

Having a look at the data bus DQ I can see the following in the
PERFORMANCE ANALYST (that is the STATIC TIMING ANALYSIS):

SOURCE       DESTINATION      DELAY (ns)

CLK             Dq_15         9.971
CLK             Dq_14         9.971
CLK             Dq_13         9.701
CLK             Dq_12         9.701
CLK             Dq_11         9.698
CLK             Dq_10         9.698
CLK             Dq_9          9.974
CLK             Dq_8          9.974
CLK             Dq_7         10.574
CLK             Dq_6         10.070
CLK             Dq_5         10.350
CLK             Dq_4         10.314
CLK             Dq_3         10.070
CLK             Dq_2         10.574
CLK             Dq_1         10.350
CLK             Dq_0         10.314


As you can see there are different tCO for the bits of the bus,
the same for DQS, ALTHOUGH using the Lattice datapath template as
described in my previous post.

Any ideas?

Rgds
André

Article: 83047
Subject: Re: CAM for FPGA ...
From: ALuPin@web.de (ALuPin)
Date: 22 Apr 2005 00:30:04 -0700
Links: << >>  << T >>  << A >>
"Moti Cohen" <Moti.cohen@alvarion.com> wrote in message news:<1114067899.464241.13230@f14g2000cwb.googlegroups.com>...
> Hi all,
> I would like to get into a CAM design for FPGA.
> Does any of you know about where can I find material on this subject? I
> will appreciate stuff like tutorials and reference designs (examples in
> any HDL)..
> 
> Thanks in advance, Moti.

Maybe there could be some possibility to build a CAM by using
the integrated RAM of a FPGA / CPLD ...

What are going to use ? Altera, Lattice, ... ?

Rgds
André

Article: 83048
Subject: Re: Xilinx Impact in Linux 2.6.x
From: Erik Walthinsen <omega@pdxcolo.net>
Date: Fri, 22 Apr 2005 00:55:57 -0700
Links: << >>  << T >>  << A >>
Symon wrote:
> Does the Platform USB cable help? $149 ;-(
> http://www.xilinx.com/bvdocs/ipcenter/product_brief/usb_cable_overview.pdf

Holy cow.

Exact same price as the "coming soon" Spartan 3E starter kit, which also 
has an FPGA (xc3s500e), 32MB of DDR SDRAM, flash, Ethernet PHY, USB 2.0 
(Cypress EZ-USB FX2 I hope), etc.  I'm assuming it will come with Impact 
drivers to use the FX2 to drive the JTAG chain, and/or use serial slave 
mode, and hopefully an appnote on writing your own download sequence 
into your FX2 firmware.  Then again the Xilinx page lists the good old 
parallel JTAG cable as coming with it.  Just as long as they hook up 
enough pins to let the USB controller config the FPGA, I'll be happy.

Article: 83049
Subject: ispTRACY-Lattice vs. SignalTap-Altera
From: ALuPin@web.de (ALuPin)
Date: 22 Apr 2005 01:29:00 -0700
Links: << >>  << T >>  << A >>
Hi newsgroup,

can someone explain to me which architecture characteristics of
Lattice EC vs.
Altera Cyclone lead to the fact that
in ispTRACY I can sample data AND other clocks and in SignalTap only
data but not other clocks ?

Thank you.

Rgds
André



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search