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Messages from 83700

Article: 83700
Subject: Re: Availability of the Xilinx ML481 Development Board
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 5 May 2005 07:46:22 -0700
Links: << >>  << T >>  << A >>
I have been told that it can be sold, but it is expensive.
Contact Saeid.
Peter Alfke


Article: 83701
Subject: Re: how to constrain this
From: Brijesh <brijesh_xyz@cfrsi_xyz.com>
Date: Thu, 05 May 2005 11:13:56 -0400
Links: << >>  << T >>  << A >>
Benjamin Menküc wrote:
> Hi,
> 
> my pad input clock is 100 MHz (clk_ibufg). I have constrained this to 
> period 10 ns. How should I constrain the lvds_tick, which runs at max. 
> 360 MHz ? Is this done automatically when I constrain clk_ibufg?
> Should I constrain the 180 MHz clock too?
> 
> regards,
> Benjamin
> 
> dcm2_1 : dcm2 port map (
>     CLKIN_IN => clk_ibufg,
>     RST_IN => RESET,
>     CLKFX_OUT => clk_180m,
>     CLKDV_OUT => pixel_clk,
>     LOCKED_OUT => lvds_locked,
>     CLK0_OUT => open);
> 
> dcm3_1: dcm3 PORT MAP(
>         CLKIN_IN => clk_180m ,
>         RST_IN => not lvds_locked,
>         CLK0_OUT => open,
>         CLK2X_OUT => lvds_tick,
>         LOCKED_OUT => open
>     );

When you are cascading DCM's you should bring out the second DCM out of 
reset after some delay from the time the first DCM is locked. There was 
an appnote which used 16 bit shift register to delay the 'locked' signal 
from the first DCM. That could be one of the problems.

Other thing I noticed is
"Clock period: 14.088ns (frequency: 70.984MHz) "
You said you constrained it to 100Mhz.
Probably the constraint was not properly applied and hence ignored by 
the tool.

Brijesh



Article: 83702
Subject: Re: Xilinx V4 Power Calculations
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Thu, 05 May 2005 08:34:26 -0700
Links: << >>  << T >>  << A >>
JD,

The only difference for power at high temp versus low temp is
leakage current.  All of these blocks (DCM, DSP40, PPC405) are
in the silicon and whether or not you are actively using them
they are sitting there and leaking current from the VCCINT
supply.

Adding these into the power tool as a "used" element will change
the dynamic portion of the power consumption for the device, but
it won't change the leakage current component as this is function
of the device that you selected which includes leakage from
everything that is in the silicon.

Ed

JD_Design wrote:
> Austin,
> 
> I am probably not planning on using any of the DSP48 blocks, but I
> noticed the same for them (no change over temperature).  Apologies for
> the skepticism, but it seems strange to me that I could load up my
> device with DCMs, DSP48s, PPC405s and measure the power at room temp
> and at high temp and have the difference between those two values be
> the same difference I would get if I were using NONE of those resources
> in the first place.
> 
> Anyway, is there a spreadsheet for power calculations that I can get
> that would allow me to both do this analysis offline?
> 
> Thanks,
> 
> JD
> JDDC
> 

Article: 83703
Subject: Re: how to constrain this
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Thu, 05 May 2005 17:49:11 +0200
Links: << >>  << T >>  << A >>
Hi Brijesh,

> When you are cascading DCM's you should bring out the second DCM out of 
> reset after some delay from the time the first DCM is locked. There was 
> an appnote which used 16 bit shift register to delay the 'locked' signal 
> from the first DCM. That could be one of the problems.

I will look at that, but I think thats no problem at the moment.

> 
> Other thing I noticed is
> "Clock period: 14.088ns (frequency: 70.984MHz) "
> You said you constrained it to 100Mhz.
> Probably the constraint was not properly applied and hence ignored by 
> the tool.

Yes, my first experiments with the constraints didn't work, but now its 
already a little bit better (see my subposts to this topic) :)

regards,
Benjamin

Article: 83704
Subject: Re: I got it!
From: "John_H" <johnhandwork@mail.com>
Date: Thu, 05 May 2005 15:53:48 GMT
Links: << >>  << T >>  << A >>
The LCD has to support a data stream with a divide-by-7 reference clock.
Good info.

Using the DDR registers you can have an effective divide-by-3.5 applied to
your 360 MHz clock and DDR generated from the same 360 MHz clock.  This
looks from the outside as if it's a 720 MHz clock providing the divide-by-7
and the data running at 720 Mbits/s/pin just as if it were clocked with a
720 MHz clock.

Your LCD doesn't have to understand DDR to receive 720 Mbit/s data streams
and a 102.86 MHz clock.


"Benjamin Menküc" <benjamin@menkuec.de> wrote in message
news:d5dar6$nms$00$2@news.t-online.com...
> Hi John,
>
> the clock is actually 360 MHz divided by 7. It's an asyncronous clock
> like this "--___--". However the data goes at 360 MHz SDR. I have to use
> SDR, because the LCD doesn't support DDR.
>
> regards,
> Benjamin



Article: 83705
Subject: Re: I got it!
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Thu, 05 May 2005 18:15:59 +0200
Links: << >>  << T >>  << A >>
Hi John,

> Using the DDR registers you can have an effective divide-by-3.5 applied to
> your 360 MHz clock and DDR generated from the same 360 MHz clock.  This
> looks from the outside as if it's a 720 MHz clock providing the divide-by-7
> and the data running at 720 Mbits/s/pin just as if it were clocked with a
> 720 MHz clock.
> 
> Your LCD doesn't have to understand DDR to receive 720 Mbit/s data streams
> and a 102.86 MHz clock.

the max. pixelclock of the LCD is 80 MHz, that would be a LVDS clock of 
560 MHz. Maybe when everything works (DVI-Link is the next challange 
now), I will try to tune up the LCD to 80 MHz using your DDR methodology.

Thanks for the information.

regards,
Benjamin

Article: 83706
Subject: Re: Xilinx V4 Power Calculations
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 05 May 2005 09:46:12 -0700
Links: << >>  << T >>  << A >>
JD,

As I have said before (and also explained it to you), the differences 
are swamped by the margin for process.

As for a local version of the predictor, we no longer support the excel 
spreadsheet downloaded version.  We are reconsidering that decision. 
Initially, there was only a spreadsheet for download.  Then we had both 
the spreadsheet and the web based spreadsheet.

How many folks out there want to have the local spreadsheet version for 
estimating?

Austin

JD_Design wrote:

> Austin,
> 
> I am probably not planning on using any of the DSP48 blocks, but I
> noticed the same for them (no change over temperature).  Apologies for
> the skepticism, but it seems strange to me that I could load up my
> device with DCMs, DSP48s, PPC405s and measure the power at room temp
> and at high temp and have the difference between those two values be
> the same difference I would get if I were using NONE of those resources
> in the first place.
> 
> Anyway, is there a spreadsheet for power calculations that I can get
> that would allow me to both do this analysis offline?
> 
> Thanks,
> 
> JD
> JDDC
> 

Article: 83707
Subject: Re: Gated clock problem
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 5 May 2005 10:01:03 -0700
Links: << >>  << T >>  << A >>
NET "YOU_CRAZY_MADMAN" MAXSKEW=100ps;
"Wenjun Fu" <fwj@nmrs.ac.cn> wrote in message
news:ee8dffe.9@webx.sUN8CHnE...
> Thank you for your advice. I'll try to use DLL to double the FPGA Clock.
>
> But another question, can I use any timing constrains limits the delay
difference of 2 inputs of a LUT to an accepted level? How?



Article: 83708
Subject: VIIPro on-chip LVDS termination
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Thu, 05 May 2005 18:06:53 GMT
Links: << >>  << T >>  << A >>
As I understand it, the VIIPro devices have on-chip differential termination 
resistors which can be brought into play by selecting the XXX_LVDS_25_DT 
buffers. I've looked at several designs using VIIPro devices from different 
manufacturers but they all seem to use external 100R resistors to achieve 
LVDS termination. Can anyone tell me why this would be the case please? I 
thought the reduction in component count would be very welcome. Is it 
because of heat dissipation?

TIA,

Rog. 



Article: 83709
Subject: Re: VIIPro on-chip LVDS termination
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Thu, 05 May 2005 11:45:05 -0700
Links: << >>  << T >>  << A >>
Roger,

This is likely a case of old habits die hard.  Also since this
wasn't officially supported when Virtex-II Pro was first released
the early the board was created the more likely the external
resistor would be present.

Since the "_DT" is true differential termination, there is no
significant heat dissipation caused by using it.  Unlike, the
previous thevenin equivalent split termination version with a
two 100 ohm loads between 2.5V and GND.

Ed

Roger wrote:
> As I understand it, the VIIPro devices have on-chip differential termination 
> resistors which can be brought into play by selecting the XXX_LVDS_25_DT 
> buffers. I've looked at several designs using VIIPro devices from different 
> manufacturers but they all seem to use external 100R resistors to achieve 
> LVDS termination. Can anyone tell me why this would be the case please? I 
> thought the reduction in component count would be very welcome. Is it 
> because of heat dissipation?
> 
> TIA,
> 
> Rog. 
> 
> 

Article: 83710
Subject: Re: Xilinx V4 Power Calculations
From: "JD_Design" <JDDesignAndConsulting@hotmail.com>
Date: 5 May 2005 11:51:11 -0700
Links: << >>  << T >>  << A >>
Austin,

Obviously, I vote for the spreadsheet :)

Thanks!

JD


Article: 83711
Subject: Re: Help
From: Rob Gaddi <rgaddi@bcm.YUMMYSPAMtmc.edu>
Date: Thu, 05 May 2005 13:52:41 -0500
Links: << >>  << T >>  << A >>
Marco wrote:
> Hallo,
> where I could find a complete manual (pdf) for programming in Ansi C?
> 
> I need to understand the meaning of operators like:
> |=
> ^=
> a & 0x07
> 
> Many Thanks
> Marco
> 
> 
Not sure, I'd recommend Google.

As to your immediate question, &, |, and ^ are bitwise operators, not to 
be confused with &&, ||, ^^, which are logical operators.

int A, B, C;
C = A & B;	/* bitwise and */
C = A | B;	/* bitwise or */
C = A ^ B;	/* bitwise xor */

The bitwise operators take two integers (run like hell if they're not 
integers), and perform an operation combining the high bit of A with the 
high bit of B, storing the result in the high bit of C, the next bit of 
A with the next bit of C into the next bit of C, and etc.

The logical operators take two boolean values ( 0 is FALSE, anything 
else is TRUE ) and compare them in the same way.

int A, B, C;
C = A && B;	/* set C true if A is true and B is true */
C = A || B;	/* set C true if A is true or B is true */
C = A ^^ B;	/* set C true if A is true xor B is true */

Your question as to |= and &= follow the C convention of allowing 
shorthand for assignment operators.

A &= 5;		/* A = A & 5 */
A |= 5;		/* A = A | 5 */
A += 5;		/* A = A + 5 */

Hope this helps.
--Rob

Article: 83712
Subject: Clock Gating
From: Rob Gaddi <rgaddi@bcm.YUMMYSPAMtmc.edu>
Date: Thu, 05 May 2005 13:56:48 -0500
Links: << >>  << T >>  << A >>
So, it seems from another thread that the general consensus is somewhat 
against clock gating.  I'm still somewhat new at the whole FPGA thing, 
so I was hoping for some input as to:

a) Is this a general rule, or does it only apply to high speed clocks, 
and if so, what starts to become "high speed"?

b) I'm using a Spartan III and currently using a BUFGCE to gate a 40 MHz 
clock that is only used externally.  Is this poor form, or is it just 
clock gating through LUTs that's frowned upon?

Any advice is, as always appreciated.

-- Rob

Article: 83713
Subject: DVI implementation
From: Luc <lb.edc@pandora.be>
Date: Thu, 05 May 2005 21:05:34 +0200
Links: << >>  << T >>  << A >>
I wonder if DVI can be implemented on an FPGA fabric - I mean receiver
and transmitter.
Some concerns I have:
I/O cell
Tx/Rx protocol
Serialization

Thanks in advance,

Luc

Article: 83714
Subject: Re: Clock Gating
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 05 May 2005 12:31:56 -0700
Links: << >>  << T >>  << A >>
Rob Gaddi wrote:
> So, it seems from another thread that the general consensus is somewhat 
> against clock gating.  

let's count up the score:
http://groups-beta.google.com/groups?q=gated+clock+enable+synchronous

     -- Mike Treseler

Article: 83715
Subject: Re: Clock Gating
From: "Peter Alfke" <peter@xilinx.com>
Date: 5 May 2005 13:22:12 -0700
Links: << >>  << T >>  << A >>
Clock gating has two bad effects:
The output of the gating is unavoidably delayed, so you end up with two
flavors of the same basic clock, but with a slight timing difference.
Can lead to bad hold-time isseus when your signal crosses between the
domains.

But the biggest problem occurs when the gating signal is asynchronous
with the clock being gated. Then all hell breakes loose, since it will
generate runt pulses and slivers in a totally uncontrolled way.
There are clever ways around this (as I described in TechXclusives "Six
Easy Pieces" and as implemented in the Virtex-4 clock multiplexer), but
most savvy designers consider clock gating a "criminal offense".

Peter Alfke


Article: 83716
Subject: Re: Does this group allow JobPostings?
From: David <david.nospam@westcontrol.removethis.com>
Date: Thu, 05 May 2005 22:22:51 +0200
Links: << >>  << T >>  << A >>
On Wed, 04 May 2005 14:32:19 -0700, EveEllsworth wrote:

> I am a senior technical recruiter with a very reputable firm, Common
> Agenda.  I have postitions to post in the SF Bay Area and very real.
> My client company is actively interviewing.
> 
> Please advise if it is acceptable to post here.
> 
> Eve Ellsworth
> 
> Senior Recruiter
> Common Agenda, LLP
> Tel: (732) 223-7114 Ext. 108
> 
> Fax: (732) 223-7116
> Email:  eve@commonagenda.com
> 
> Web:  www.commonagenda.com
> ...Partnering with progressive companies in the quest for exceptional
> talent...

This is an international newsgroup - if you want to post something that is
specific to some little country south of Canada, have the courtesy to the
newsgroup and the pride in your country to make it clear which country you
are referring to, both in the subject line and in the post, and remember
that your post is irrelevant to a large proportion of readers (unless you
are willing to pay *large* moving fees!).


Article: 83717
Subject: Re: VIIPro on-chip LVDS termination
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Thu, 05 May 2005 21:20:45 GMT
Links: << >>  << T >>  << A >>
Ed,

Thanks again. So do the later Xilinx boards utilise the on-chip termination?

Rog.

"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message 
news:427A69B1.9060709@xilinx.com...
> Roger,
>
> This is likely a case of old habits die hard.  Also since this
> wasn't officially supported when Virtex-II Pro was first released
> the early the board was created the more likely the external
> resistor would be present.
>
> Since the "_DT" is true differential termination, there is no
> significant heat dissipation caused by using it.  Unlike, the
> previous thevenin equivalent split termination version with a
> two 100 ohm loads between 2.5V and GND.
>
> Ed
>
> Roger wrote:
>> As I understand it, the VIIPro devices have on-chip differential 
>> termination resistors which can be brought into play by selecting the 
>> XXX_LVDS_25_DT buffers. I've looked at several designs using VIIPro 
>> devices from different manufacturers but they all seem to use external 
>> 100R resistors to achieve LVDS termination. Can anyone tell me why this 
>> would be the case please? I thought the reduction in component count 
>> would be very welcome. Is it because of heat dissipation?
>>
>> TIA,
>>
>> Rog. 



Article: 83718
Subject: Re: System Ace: How many FPGA's in the JTAG chain before require buffers?
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 05 May 2005 16:56:58 -0500
Links: << >>  << T >>  << A >>
>I am designing a board with 9 Xilinx V4FX60 FPGA's configured via
>System Ace CF controller.
>
>Does anyone have any experience regarding the max number of FPGA's in a
>JTAG chain that can be succesfully configured?

9 is a big number.  Be very careful of the clocks.
I wouldn't expect problems with anything else.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 83719
Subject: Re: System Ace: How many FPGA's in the JTAG chain before require
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 05 May 2005 15:13:21 -0700
Links: << >>  << T >>  << A >>
Jason,

The Rosetta arrays use 100 devices in a single chain.

We do buffer the clock to groups of ten FPGAs at a time.

Austin

jason.stubbs wrote:

> I am designing a board with 9 Xilinx V4FX60 FPGA's configured via
> System Ace CF controller.
> 
> Does anyone have any experience regarding the max number of FPGA's in a
> JTAG chain that can be succesfully configured?
> 
> Was any signal buffering required to acieve this?
> 
> Thanks
> 
> Jason
> 

Article: 83720
Subject: Re: VIIPro on-chip LVDS termination
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Thu, 05 May 2005 15:17:32 -0700
Links: << >>  << T >>  << A >>
They should, but sometimes a circuit cut-and-paste from a
previous schematic may have left in place or we may have
left the external pads in place for flexibility.  You can
always desolder the external resistor and use the internal
one instead.

I'm fairly certain I had all of the external differential
resistors removed for the Virtex-4 boards (ML40x, ML41x, ML42x)
during the schematic reviews, but we may have simply missed
one or two.

Ed

Roger wrote:
> Ed,
> 
> Thanks again. So do the later Xilinx boards utilise the on-chip termination?
> 
> Rog.
> 
> "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message 
> news:427A69B1.9060709@xilinx.com...
> 
>>Roger,
>>
>>This is likely a case of old habits die hard.  Also since this
>>wasn't officially supported when Virtex-II Pro was first released
>>the early the board was created the more likely the external
>>resistor would be present.
>>
>>Since the "_DT" is true differential termination, there is no
>>significant heat dissipation caused by using it.  Unlike, the
>>previous thevenin equivalent split termination version with a
>>two 100 ohm loads between 2.5V and GND.
>>
>>Ed
>>
>>Roger wrote:
>>
>>>As I understand it, the VIIPro devices have on-chip differential 
>>>termination resistors which can be brought into play by selecting the 
>>>XXX_LVDS_25_DT buffers. I've looked at several designs using VIIPro 
>>>devices from different manufacturers but they all seem to use external 
>>>100R resistors to achieve LVDS termination. Can anyone tell me why this 
>>>would be the case please? I thought the reduction in component count 
>>>would be very welcome. Is it because of heat dissipation?
>>>
>>>TIA,
>>>
>>>Rog. 
> 
> 
> 

Article: 83721
Subject: cascaded dcms
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Fri, 06 May 2005 00:53:36 +0200
Links: << >>  << T >>  << A >>
Hi,
> When you are cascading DCM's you should bring out the second DCM out of 
> reset after some delay from the time the first DCM is locked. There was 
> an appnote which used 16 bit shift register to delay the 'locked' signal 
> from the first DCM. That could be one of the problems.

I have to do that now, because simulation doesn't work if I connect the 
inverted locked signal directly to the 2nd DCM.

http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=19005&BV_SessionID=@@@@0453148829.1115333172@@@@&BV_EngineID=ccccaddeifmhfficflgcefldfhndfmo.0

Here Xilinx says the same, however it seems that this is only neccessary 
for simulation? Or is this any good for in hardware too?

regards,
Benjamin

Article: 83722
Subject: Re: Simulating custom peripherals
From: "Joseph" <joeylrios@gmail.com>
Date: 5 May 2005 16:06:29 -0700
Links: << >>  << T >>  << A >>
Thanks for the reply digi.

The "BFM" acronym you gave reminded me that I had this package
installed.  When creating the custom peripheral, there was a options to
generate simulation files (I think) and this prompted me to download
edk_bfm_6_3.exe.  I ran this and I suppose I am ready to run these BFM
simulations.  I found a .pdf on the Xilinx site about BFM simulations,
but it isn't exhaustive (10 pgs).  Assuming I have this piece of custom
IP (built with the wizard to act as a slave on the PLB bus), do I start
a new project in XPS to test it out?  I see the bfm modules under the
"add/edit cores" dialog but don't know how to go about using them.  Do
I do something like drop a PLB bus and hook my IP to it along with one
of these bfm modules?  If so, how do I get anything useful to play with
in ModelSim?  Any further advice is appreciated!


Article: 83723
Subject: Re: Altera Excalibur EBI problem
From: "bta3" <bta3@iname.com>
Date: Thu, 5 May 2005 19:12:46 -0400
Links: << >>  << T >>  << A >>
Thanks Mike.

 Now if there is a way to turn off the DCache register in C rather than in
assembly.....


"Mike Lewis" <someone@micrsoft.com> wrote in message
news:p5qdneneUqv2TOXfRVn-gQ@magma.ca...
> You have that area of the memory mapped cached ... you are seeing a cache
> line
> burst for the first access and nothing after that because it is
manipulating
> the cache memory ... turn off the cache for this memory region.
>
> Mike
>
> "bta3" <bta3@iname.com> wrote in message
> news:4JTde.11307$o32.1391@fe09.lga...
> > BlankHi,
> >  I seem to have a problem talking to a MAC chip that is connected as a
> > memory mapped device on the EBI bus of an EPXA1-672 chip (EBI2 for CS,
no
> > split reads and no prefetch). EBI1 is connected to a flash chip. I am
> > using
> > the GNU toolset to develop code and no OS (as yet).
> >
> >  Apparently, if I read a single register (in my code), a series of 16
read
> > accesses are made by the chip and cached. Subsequent reads do not access
> > the
> > MAC, rather return values from the cache - I do not see any CS
transitions
> > at the chip pins. The write operations function perfectly well if I do
not
> > perform a read - one CS for every write request. Once a read is
performed,
> > the writes also cease to be "executed" and change the register value in
> > the
> > cache only.
> >
> >  Has anyone seen a similar problem? The Altera folks have not responded
to
> > my trouble tickets - their support is not what it used to be.
> >
> > Thanks, bta3
> >
> >
>
>



Article: 83724
Subject: including components, i.e. SRL16
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Fri, 06 May 2005 01:22:15 +0200
Links: << >>  << T >>  << A >>
Hi,

when I want to use a SRL16, I have to "include" the component in my 
entity like this:

component SRL16
    port (
       Q  : out std_logic;       -- SRL data output
       A0: in std_logic;     -- Select[0] input
       A1 : in std_logic;     -- Select[1] input
       A2 : in std_logic;     -- Select[2] input
       A3 : in std_logic;     -- Select[3] input
       CLK : in std_logic;   -- Clock input
       D : in std_logic        -- SRL data input
    );
end component;

Can I find templates for these component declarations somewhere? In the 
lib.pdf I can find only instantiation templates. Besides that, I can not 
use the generic map (INIT => X"0000")...
How do I do it properly? Are there any include files for all the design 
elements?

regards,
Benjamin



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