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"Vladislav Muravin" <muravinv@advantech.ca> wrote in message news:h9Oee.15785$VL3.778457@news20.bellglobal.com... > hi Ken, > > First question - no. tried almost the same thing on Virtex 2 (was locking > and losing lock periodically). > What you should do is to multiply by a larger number using CLKFX as now, > and then used FFs to divide the clock down for feeding it to the next DCM > stage. > In this fashion, the output jitter on DCM1/CLK0 is divided as well to be > suitable for the DCM2/CLKIN jitter tolerance. > How, pray tell, do the FFs divide the jitter? The peak-to-peak jitter, measured in units of time, can only get worse though a FF divsion. > > I tried, it works PERFECTO! > What happens, is that DCM multiplies whatever jitter you have at your clock > source plus adding some cycle-cycle > jitter, due to its tapped delay line nature. I think there is some web page > in Xilinx website or tools that > calculates that output jitter per given input jitter. > How does the DCM multiply input jitter? Are you getting confused between pk-pk jitter in terms of time as opposed to pk-pk jitter in terms of unit intervals? If you look at the DCM input timing specs, you'll see they're specified in terms of time, not UIs. In my experience, problems with DCMs often derive from noise on the supplies from inadequate Vccaux bypassing. Whatever, I'll wait for Austin to post and clear this up! Cheers, Syms.Article: 83776
Bob Perlman wrote:
>On Fri, 06 May 2005 10:50:54 -0400, Brijesh
><brijesh_xyz@cfrsi_xyz.com> wrote:
>
>
>
>>I know that we can vary the drive strength of the Virtex outputs and
>>control the rise time. This just for my understanding of things.
>>
>>Using a capacitor to ground to slow the rise time feels like a very
>>wrong thing to do. But I am not able to convince others why its a bad
>>practise?
>>
>>The reasons I can come up with are
>>1) It increases the total current and hence can contribute to ground
>>bounce and cross talk.
>>2) Total power dissipation in the device is increased.
>>
>>3) It takes up board space, requires more components etc.(for now lets
>>stick to the electrical aspect of things and ignore this issue)
>>
>>I am unable convince that this practise is bad and a real issue.
>>
>>Is there something I am missing?
>>
>>Brijesh
>>
>>
>
>I've avoided using capacitors on digital lines for the last 30 years.
>Actually, that's not quite true. About 10 years ago, another designer
>I was working with convinced me that we had a special situation in
>which a capacitor was called for. So now my policy is, every 20 years
>or so, go nuts. Now that I think of it, I've also suggested using RCs
>on I2C drivers that are too fast. But that's about it.
>
>And some folks might say that it's acceptable to filter
>non-speed-critical digital signals that enter or leave a system, for
>EMI purposes. I haven't found it necessary, but I won't argue the
>point.
>
>I avoid capacitors on digital lines because (1) the resulting risetime
>is usually poorly controlled, (2) the resulting additional signal
>delay is usually poorly controlled, (3) the capacitor is often used to
>cover up an underlying design problem, e.g., a glitchy decoder driving
>a synchronous input, and (4) I've always been able to find a better
>solution.
>
>I don't know how many people on this group read Joel Spolsky's "Joel
>on Software" blog. Spolsky has an interesting idea called the Joel
>Test, a list of 12 questions with yes/no answers that you can use to
>evaluate the quality of a software team. You can find it here.
>
>http://www.joelonsoftware.com/articles/fog0000000043.html
>
>I think it would be an interesting idea to come up with a similar list
>for digital hardware design. And now Brijesh has provided me with the
>inspiration to start such a list:
>
>1) Do you use capacitors on digital lines?
>2) Do you use analog one-shots in your designs?
>
>
3) do you connect logic outputs to clock inputs (or do you use gated
clocks)?
>A "yes" answer to either question should be accompanied by a whole lot
>of 'splaining.
>
>One other thought: CPLD and FPGA vendors did the digital design
>community a great and lasting service by not including an "add a
>capacitor to this net" feature.
>
>Bob Perlman
>Cambrian Design Works
>
>
>
>
>
>
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 83777"Ray Andraka" <ray@andraka.com> wrote in message news:iHOee.5377$aB.4807@lakeread03... > Bob Perlman wrote: > > > > >1) Do you use capacitors on digital lines? > >2) Do you use analog one-shots in your designs? > > > > > 3) do you connect logic outputs to clock inputs (or do you use gated > clocks)? > > 4) Have you had any bugs that 'fixed themselves' without you knowing why? (They always come back!) 5) Any unterminated digital lines going off board and/or longer than c.15cm? Cheers, Syms.Article: 83778
I hope one of the Xilinx gurus can help me out here...
I've got a design that uses multiple V2Pro parts receiving
a common high speed clock. The clock is well laid out to
equalize trace lengths and is differential. I also have
the ability to cleanly start/stop the clock.
I'd like to use the CLKIN_DIVIDE_BY_2 option on the DCMs in
the V2Pro parts to cut the rate down, but I'd like to make sure
that the CLK0 outputs of the DCMs in the different parts come
up in phase.
For this design, I'd hook the CLK0 output to the DCM feedback
pin in each FPGA.
If I stop the input clock, reset the DCMs in each part, then
start the input clock again...
a) Will the input dividers of the DCMs be in phase?
b) After the DCMs achieve lock, will the CLK0 outputs of
the DCMs in the different parts also be in phase?
Thanks!
John Providenza
Article: 83779Hi, I'm using the EDK 7.1 for a project and I need to use a memory manager like malloc. According to Xilinx' documentation there should be a xil_malloc() function. I have set flag "requires malloc" in the software properties in system platform and re-generated the libraries. The tool creates a nice xil_malloc.h file for me but when I try to link my program the linker cannot find it. What is wrong?? I have been plagued with this for quite a while ;-) thanks, peterArticle: 83780
At this link the source is free for a pci 32 bit slave. http://www.latticesemi.com/products/devtools/ip/refdesigns/pcitarget.cfm Don't know about CAN controller costs, you might want to use a discrete device to avoid the IP price. Open cores is best for free processors. Good luck.Article: 83781
Symon wrote: > "Ray Andraka" <ray@andraka.com> wrote in message > news:iHOee.5377$aB.4807@lakeread03... > >>Bob Perlman wrote: >> >> >>>1) Do you use capacitors on digital lines? >>>2) Do you use analog one-shots in your designs? >>> >>> >> >> 3) do you connect logic outputs to clock inputs (or do you use gated >>clocks)? >> >> > > 4) Have you had any bugs that 'fixed themselves' without you knowing why? > (They always come back!) > 5) Any unterminated digital lines going off board and/or longer than c.15cm? Iam not aware what c.15cm means? Guess what we already have 32 bit bus which is going off board without any termination on the board. The reasoning was "its a slow bus we are only going to operate it at xMHz". The layout was originally intended to be used as LVDS bus and had termination for LVDS. But now its being used as LVTTL outputs over 6ft SCSI cable. I just lowered the drive strength to 4mA and crossed my fingers. :-) Worst part is it is working, making me wonder if I am the one who is paranoid? I have observed that even though people have read and know that its the rise time that matters. They still tend to think like "its only 4MHz, termination is not a issue". I think we have already been burnt by this in a differnt project. Solution that is being adapted is to slow the signal by putting a capacitor instead of treating the signal with care in layout and termination. (Iam talking about serial clk out of the FPGA in master serial programming mode) Ray, I think you know what I am talking about :-). These question are really helpful for the new engineers like me. Hope more people will contribute. :-) Brijesh > > Cheers, Syms. > >Article: 83782
Hello,
I want to start learning VHDL (or VERILOG) and FPGA programming. I have
ISE 6.1 and some FPGA board. Where is the best place to start? I am an
experienced C/C++ programmer.
What I need to develop a simple code in VHDL (or VERILOG)?
How should I compile route and place and.. ?
How can I see the output?
Best regards
Article: 83783All, Latest update on atmospheric upsets: http://tinyurl.com/c9y5l Virtex 4 memory cells are almost twice as hard to upset as Virtex II. We promised to reduce our susceptibility to atmospheric upsets, and we are fulfilling that promise. Not all semi companies have made this choice: it is hard to do, and increases area. I know of work being done at Intel, and Cypress to improve, but nowhere else. It is highly likely that competing 90nm FPGA companies have done anything at all (except get a lot worse). The ASIC (ASSP, hardened solutions, etc.) also have not made this choice (as it would really blow up their area a lot). Thus, 90nm ASIC technology has a typical SRAM FIT rate of 5,000 FIT/Mb (from neutron data error rate specifications for a typical 90nm SRAM ASIC cell), as compared to our less than 250 FIT/Mb. The ASIC DFF's, logic, etc. are also a fantastic neutron detector: the resulting hardness of the Virtex 4 is on par with, and better than a full custom 90nm ASIC doing the same task! Unfortunately, no data is available on ASIC's, as they just don't know. To test, one would have to place the part in a neutron beam, while running, which is rather hard to do with a complete system ... Caveat Emptor! Virtex 4 on the other hand, combines with built in ECC for the BRAM, and built in FRAME_ECC for the configuration, which allows for selecting whatever level of system hardness to soft errors is desired. AustinArticle: 83784
ma wrote:
> What I need to develop a simple code in VHDL (or VERILOG)?
A VHDL (or VERILOG) simulator.
> How should I compile route and place and.. ?
Don't worry about that until your simulation is OK.
> How can I see the output?
On the simulation waveforms.
-- Mike Treseler
Article: 83785Xilinx has "Getting started" tutorials for ISE. www.xilinx.com This is the first place you should look. This will teach you how to use the tools and give you sample VHDL code to try. To learn VHDL: 1)buy a book 2)Read book 3)try examples in ISE tool set I'm pretty happy with "VHDL PRIMER Third Edition" by J. Bhasker, My only complaint with this book is it doesn't differentiate between synthesizable code and code for simulation only. If you don't understand what I just said buy "The Design Warrior's Guide to FPGA's" by Clive Maxfield. This is a very good beginner book. This book won't show you how to code VHDL or Verilog, but it will explain how FPGA's work and the common "jargon" used when talking about FPGA's. There are lots of free VHDL tutorials online, but they are free for a reason. Nothing can substitute a good book as a reference. That's my two cents, EricArticle: 83786
Hi Austin, I'm really happy for you. Are there any V4s without the money-eating ECC stuff for us terrestrials? BenArticle: 83787
I believe this is a dll that comes with ISE. You can check your ISE install in the bin directory (e.g. $XILINX/bin/nt/libSecurity.dll) to see if it's there and make sure your PATH environment has this directory in it. If that's all good, make sure that you have the version of ISE installed that matches EDK. There's a list here. http://www.xilinx.com/ise/embedded/edk_download.htm Good luck ... nara_chak45 wrote: > Also I have another issue, > > I recently installed EDK 6.2 and when i try to open the application > from the menu, it says "file libSecurity.dll was not found, > reinstalling the application may solve the problem" . i reinstalled > twice but the same issue comes in. If someone has any solution for > this, it will be great if you could share the info. > > Thanks and Regards, > chak.Article: 83788
Nice try! ECC at the 64-bit parallel level eats only 8 extra bits, and our BlockRAMs had those traditional parity bits all the time. No extra storage cost. Just some clever partitioning... "The best things in life are (almost) free" Peter AlfkeArticle: 83789
>My only complaint with this book is it doesn't differentiate between >synthesizable code and code for simulation only. Yes, that is true. I am also looking for a good book which explains how to code for synthesizability. Somebody please suggest a book!Article: 83790
Hi Peter, I learned about SEU that you can design redundant (three times the logic if you can convince your compiler not to remove redundant logic). This will keep the user logic save. But is there a way to keep configuration save since this changes logic and routing? Regards, ThomasArticle: 83791
Make sure M0~M2 are set correctly to read config flash at FPGA startup.Article: 83792
I'm still new in FPGA design, and learning Verilog, and the EDA tools (Xilinx ISE, ModelSim, ...). I have a problem simulating Post-Map Simulation Model with ISE 6.3. I have a verilog project which consist of 2 files (a simple module and a test bench). My module file contain a module with ports defined as module mux4_to_1(out, i0, i1, i2, i3, s1, s0); And, from the testbench file, I instantiate mux4_to_1 as mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0); The sources are correct, and lower level of simulations work correctly. ISE generate the appropriate model files (.v, ...) and call the simulator (ModelSim). However, when I come to simulate Post Map, ISE generate the post map simulation model, and call ModelSim, but ModelSim complains about ports errors. Looking at the generated files, I clearly see the problem. The ports are inverted. Here are the generated models 'module' declarations: Post-Translate verilog source: module mux4_to_1 ( out, i0, i1, i2, i3, s0, s1 ); Post-Map verilog source: module mux4_to_1 ( s1, s0, i3, i2, i1, i0, out ); Here, you see that the ports list is inverted. And since the module is instantiated by passing port list by order, the ports get miss-connected. Anybody having this problem, and know what I can do (appart from specifying ports by name)? ThanksArticle: 83793
I'm pretty familair with the standard 2-DFF schemes for synchronization. I came across the URL below and have a question about Figure 1b: Why not use the clock-enable on the FF on the right-hand side instead of having the flop re-latch data at every clock? Is this because a CE on a flip-flop in an ASIC may not be available, as it is on an FPGA? http://www.eedesign.com/features/exclusive/showArticle.jhtml?articleId= 57701580&kc=4235 Thanks. H.Article: 83794
And, The frame_ecc is 12 bits per 1312, or less than 1% overhead. Austin Peter Alfke wrote: > Nice try! > ECC at the 64-bit parallel level eats only 8 extra bits, and our > BlockRAMs had those traditional parity bits all the time. No extra > storage cost. Just some clever partitioning... > "The best things in life are (almost) free" > Peter Alfke >Article: 83795
>Bob Perlman wrote: >1) Do you use capacitors on digital lines? >2) Do you use analog one-shots in your designs? >Ray Andraka wrote: >3) do you connect logic outputs to clock inputs (or do you use gated > clocks)? >Symon Brewer wrote: >4) Have you had any bugs that 'fixed themselves' without you knowing why? > (They always come back!) >5) Any unterminated digital lines going off board and/or longer than c.15cm? >Philip Freidin wrote: >6) Do you have any pet theories on how to fix metastables? > >7) Do you use the async set and reset pins on FFs for other than > system initialization?Article: 83796
Thomas, Yes. The Xilinx TMR (XTMR) tool converts the design from the designed and placed to a full TMR design automatically taking advantage of our structure so that no one config bit can upset the function. FRAME_ECC allows a design to do redundancy in time (RIT). Calculate what you need, check if an error has occured, if not, go on. If an error has occurred, fix the error, step back, recalculate. Repeat. Between XTMR which allows you to choose only those critical areas that need triplication for redundancy in space (RIS), and FRAME_ECC which enables redundancy in time, an arbritraily safe system can be implemented. For example: Simplest - do nothing. With an effective system FIT rate of 20 FIT/Mb of config memory, this may be so far down in the noise, it isn't an issue. Next step - when the FRAME_ECC indicates an error, reconfigure the chip. This creates some unavailability, but is able to keep any errors from propagating any further. Or back up, and recalculate the result after flipping the bit back (RIT). Little better - when a error is detected, correct it. Since from 1 in 10 to 1 in 80 flips actually hits something that matters (real data from real customers), there is a 1% to 10% chance that flip could ever cause an error, and since you fix it in less than 200 ms (for the largest part), the probability that in that 200 ms something critical changeds, and it mattered is even tinier (like maybe one in a thousand chance). And, if you add to this RIT, it is even more bulletproof. Even better - since this is a system that requires a hot spare (at this point, we are talking about 99.9995% available systems where the hard fail rate kills you first) you detect a soft error, and switch to the redundant unit immediately while you fix the bit, and do a system recheck. Best - triplicate critical elements AND have a hot standby that can be switched to in case of soft error detect. All of the above are enabled in V4 -- it is up to you to set your FIT rate goals, and then fufill them. Can't do that with the competition -- they just don't have all the options we do. For example, a complete reconfig takes them down, but we can reconfig while still operating, and fix the flipped bit back. Austin Thomas Rudloff wrote: > Hi Peter, > > I learned about SEU that you can design redundant (three times the logic > if you can convince your compiler not to remove redundant logic). This > will keep the user logic save. But is there a way to keep configuration > save since this changes logic and routing? > > Regards, > Thomas >Article: 83797
Philip Freidin wrote: >>Bob Perlman wrote: >>1) Do you use capacitors on digital lines? >>2) Do you use analog one-shots in your designs? >> >> > > > >>Ray Andraka wrote: >>3) do you connect logic outputs to clock inputs (or do you use gated >> clocks)? >> >> > > > >>Symon Brewer wrote: >>4) Have you had any bugs that 'fixed themselves' without you knowing why? >> (They always come back!) >>5) Any unterminated digital lines going off board and/or longer than c.15cm? >> >> > > > >>Philip Freidin wrote: >>6) Do you have any pet theories on how to fix metastables? >> >>7) Do you use the async set and reset pins on FFs for other than >> system initialization? >> >> > > > > > 8) Do you use pull up resistors on fast CMOS busses that require less than 10ns/V rise / fall time?Article: 83798
Austin Lesea wrote:
> The ASIC DFF's, logic, etc. are also a fantastic neutron detector: the
> resulting hardness of the Virtex 4 is on par with, and better than a
> full custom 90nm ASIC doing the same task!
BTW, is it possible to order a special, rad-hard version of
a modern medium-complexity FPGA chip, say, comparable
with Cyclone 1C3? Would it mean a complete redesign of
the chip internals or is it relatively simple?
Best regards
Piotr Wyderski
Article: 83799Hw wrote: >I'm pretty familair with the standard 2-DFF schemes for synchronization. > >I came across the URL below and have a question about Figure 1b: > >Why not use the clock-enable on the FF on the right-hand side instead of >having the flop re-latch data at every clock? Is this because a CE on a >flip-flop in an ASIC may not be available, as it is on an FPGA? > >http://www.eedesign.com/features/exclusive/showArticle.jhtml?articleId= >57701580&kc=4235 > >Thanks. >H. > > > It is the same. Maybe it is just for illustration purpose. Regards, Thomas
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