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And having said that... you've got to be sure of your clock synchronisation... i.e. the synchronisation bewteen SYS_CLK and SIO_CLK Hmm, and one other thing, i'd use numeric_std and make BC a Natural.. HTH, Ben "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> wrote in message news:d6004v$kk5$1@sunnews.cern.ch... > in your code, the value of synch_found is never reset after it has found > the first synchronisation byte... > Ben > > > > > "Weddick" <weddick@comcast.net> wrote in message > news:I_adnfHl47DWIR_fRVn-3A@comcast.com... >>I have what I thought was a simple problem. I need to count the number of >>clocks to determine when to take data out of the shift register. The data >>is a continuous stream and I want to be able to count every 8 bits. I >>thought I could use a 3 bit counter but can't seem to get the code >>correct. I then went to a 4 bit counter, and while it works I am not sure >>if the code is the best way. Any ideas? >> >> Thanks, >> Joel >> >> >> >> > >Article: 84101
It's again time for the annual bragging frenzy, where every FPGA manufacturer claims to have the biggest. It seems so simple: The Xilinx XC4VLX200 has 178,176 LUTs + associated flip-flops, while the Altera EP2S180 has 143,520 ALUTs + flip-flops. The conclusion is obvious, isn't it? But this is not that simple. In the world of creative marketing, everyone can claim to be the winner. First Xilinx muddies the water by adding 12.5% to the LUT count, to get credit for various embellishments, bringing the XC4VLX200 to 200,448 "Logic Cells". Crashing through the 200 000 barrier... But Altera cannot stand to be left behind. They get creative and apply a mysterious 1.3 multiplier which brings their EP2S180 up to 186,576 "equivalent LUTs", thus even bigger than the Xilinx behemoth. Altera also claims superiority in multipliers and RAM bits, but forgets that the cheaper XC4VSX55 or XC4FX140 are much better endowed with those attributes. It is so easy to ridicule this puerile bragging contest and its Freudian fix on one specific aspect, while ignoring far more important features. Unfortunately, some poor innocent person might actually get fooled by it. Too bad! For a more entertaining story, click on http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm Peter Alfke, Xilinx ApplicationsArticle: 84102
Thank you all for responses. I didn't mean to start a spark, even though I was curious about what Stratix/II could do in comparison. I'm now leaning toward doing it - parts of core @360, DDR data output @360 (720, effectively) along with forwarded clock @360. I'd be running simulation to make sure there isn't any big issue at 720Mbps, but since it's much lower than 1.2Gbps, I'm optimistic. Can't say Altera is out of running, however. I just wanted to make sure I could do it in some FPGA device before committing to the interface. Thanks again.Article: 84103
Hi, Oregano's core does not support an SFR bus. It's not a problem to add this feature as long as you don't need bitadressable SFRs. => So it's better to add your own SFRs to control_mem and connect them to your custom units (as it is done with the mc8051 peripherals) I have done this to upgrade the mc8051 core to an 8052 (added Timer 2).Article: 84104
Peter Alfke wrote:
> It is so easy to ridicule this puerile bragging contest and its
> Freudian fix on one specific aspect, while ignoring far more important
> features. Unfortunately, some poor innocent person might actually get
> fooled by it. Too bad!
One way to avoid being fooled is
to write portable code and run
a trial synthesis/route/STA
for all the contesting devices.
-- Mike Treseler
Article: 84105"Brian Davis" <brimdavis@aol.com> wrote in message news:1115862089.794227.150660@f14g2000cwb.googlegroups.com... > > Best wishes on getting Austin to stop with his > "but it's really half, differentially" handwaving. > > I've tried before, with results similar to that > "but it goes to Eleven" bit from "Spinal Tap". > Brian, LOL, I'm beginning to feel the same way. It's interesting that almost all the PCB differential pairs I've seen are edge coupled striplines or microstrips, very few are broadside coupled. Of course, usually with edge coupled lines most of the coupling is to the ground plane, and very little between the conductors. So, it's much more like two 50 Ohm lines rather than a 100 Ohm pair. Not that it makes any difference, of course. > > > >a way to improve things is to drive this capacitance > >with a lower impedance > > > > Also, when you've got plenty of drive margin, a differential > attenuator ahead of the FPGA (with internal termination) works > nicely to attenuate the reflection, and also makes for a convenient > differential probe point. If you have 6dB to spare, even the most > horrible of loads presents at least 12dB return loss, with the probe > seeing 1/4 the reflection voltage of the original circuit.(however, the > attenuator doesn't lower the drive impedance as does your suggestion ) > Yep! Cheers, Syms.Article: 84106
On 11 May 2005 10:50:16 -0700, rarteaga@gmail.com wrote: > >Hi, > > I'm interested in knowing how many equivalent gates are included in >a VirteX II slice for ASIC development. Thanks. Since FPGA resources can be used many different ways, there is a 1:100 ratio between the worst and best case FPGA resources to ASIC gates. If you have HDL code, you can synthesise it for both FPGA and ASIC, and extract some numbers. The ratio you get will be a reasonable estimate for similar designs. You may find the following helpful, or at least interesting: http://www.fpga-faq.org/compare/build_form.cgi =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 84107
Big Boy wrote: > I'm still new in FPGA design, and learning Verilog, and the EDA tools > (Xilinx ISE, ModelSim, ...). > > I have a problem simulating Post-Map Simulation Model with ISE 6.3. > > I have a verilog project which consist of 2 files (a simple module and > a test bench). > > My module file contain a module with ports defined as > > module mux4_to_1(out, i0, i1, i2, i3, s1, s0); > > And, from the testbench file, I instantiate mux4_to_1 as > > mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1, S0); > > The sources are correct, and lower level of simulations work > correctly. ISE generate the appropriate model files (.v, ...) and > call the simulator (ModelSim). However, when I come to simulate Post > Map, ISE generate the post map simulation model, and call ModelSim, > but ModelSim complains about ports errors. > > Looking at the generated files, I clearly see the problem. The ports > are inverted. > > Here are the generated models 'module' declarations: > > Post-Translate verilog source: > module mux4_to_1 ( > out, i0, i1, i2, i3, s0, s1 > ); > > Post-Map verilog source: > module mux4_to_1 ( > s1, s0, i3, i2, i1, i0, out > ); > > Here, you see that the ports list is inverted. And since the module is > instantiated by passing port list by order, the ports get > miss-connected. > > Anybody having this problem, and know what I can do (appart from > specifying ports by name)? > > Thanks I'd agree that this is a bug, but it should only show up when you use location to instantiate the top level module, not modules within your FPGA design. The "bug" is also evident in version 6.1i, but the actual behavior is not to reverse the port list, but rather to invert the order of port definitions to create the post map port list. In this case a work-around is to define your ports in the reverse order of the original port list like: module mux4_to_1 ( out, i0, i1, i2, i3, s0, s1 ); // reverse order of port list: input s1; input s0; input i3; input i2; input i1; input i0; output out; // code endmodule This should cause the post-map port order to remain the same as the source module.Article: 84108
Why would you want to know? A slice uses a large number of gates, but is laid out very efficiently. This structure is highly specialized and has >20 years of evolution behind it. I think there is nothing to be learned from it, except how to build FPGAs. Peter AlfkeArticle: 84109
Peter Alfke wrote: > > It's again time for the annual bragging frenzy, where every FPGA > manufacturer claims to have the biggest. > > It seems so simple: > The Xilinx XC4VLX200 has 178,176 LUTs + associated flip-flops, > while the Altera EP2S180 has 143,520 ALUTs + flip-flops. > The conclusion is obvious, isn't it? ... > It is so easy to ridicule this puerile bragging contest and its > Freudian fix on one specific aspect, while ignoring far more important > features. Unfortunately, some poor innocent person might actually get > fooled by it. Too bad! > > For a more entertaining story, click on > http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm > > Peter Alfke, Xilinx Applications Indeed a nice Article ! I feel it failed to address two important points that I, as a customer, also find very important: 1) When I send en email to a company that will be deeply involved in my revenue stream as a supplier of parts and tools, I expect them to be responsive. Every time I send an email to Xilinx (regardless if it is sales, tech support, or marketing) I get a reply within 24 hours (we are in a different time zone as well +9h). Out of the dozen or so emails we sent to Altera in the last year++ exactly zero where replied to (we either lost the customers who asked for Altera based solutions, or where able to convert them to Xilxinx based solutions). To bad ! 2) Look at this newsgroup. Peter and Austin are always there in the front line, standing up for their company, taking the heat and bs from an open public forum. Plus Xilinx makes it a point to have additional experts peeking in the group and helping out where needed. Any problem reported is discussed in the open and solved. There is no under the rug filing or shutting up the customers. I can download an errata or post to the newsgroup and get open solutions. I can't say that I see a lot of that from Altera. Yes Paul seems to be out there as well, taking on a fight here and there. But I find there is a lack of discussion level as with Xilinx. I know if I run in to a problem with Xilinx devices, I can always turn to this news group and get help. Just my two Euro-cent ... Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 84110
John W. Lockwood wrote:
> For those of us that build packet processing circuits in
> FPGA hardware, finding bugs in circuits is difficult.
> In the research and graduate courses at WashU, we have been
> using Synplicity's Identify tool to locate bugs in packet processing
> hardware. Based on our good experiences on this topic, I posted
> a tutorial from my class.
Nice job. Thanks for the posting.
I agree that debugging packet processing hardware
is challenging. My bugs are most often
due to missing a stimulus case or an assertion
in the testbench.
Once I know the symptom, and if I am lucky,
I can [1] find the event in the existing simulation
waveforms. Then I can easily fix the offending code and
and add an assertion to the testbench.
If I am unlucky, I have to [2] add stimulus cases
to provoke the bug event. In the hopefully
rare event that this can't be done
I am reduced to [3] bringing out testpoints
or [4] tainting the design with analysis hardware
for signaltap, chipscope or identify debugging
software.
So far 1, 2 and 3 have covered me. I am curious
what other debugging methods you use and
how identify compares to signaltap or chipscope
for your projects.
-- Mike Treseler
Article: 84111The conclusion clearly isn't obvious. Designs are not flip-flop limited so counting flip-flops and assuming this somehow equates to a customer experience is rather naive (though certainly convenient for an architecture that isn't optimized for logic efficiency). Altera has used our entire benchmark suite to validate the facts. Realistically of course customers should check out their own designs. No customer will ever find a real design that lines up with the 30% larger Xilinx claim (comparing the biggest devices). Most will find the 2S180 a little larger than the LX200 based on logic and a whole lot larger based on RAM and DSP resources. And customers should also try to actually purchase these large devices before making any decisions. Unfortunately the "vast" 90 nm experience making small density Spartan-3 devices doesn't translate to actually shipping high-density parts. While there are likely a few LX200 or LX160 devices that have shipped, facts are that Altera sales are greater on the 2S130 and 2S180 devices alone than the collective sales of all Virtex-4 products. Altera's patented redundancy, operational excellence, and strategy of sticking to a single fab partner significantly reduce risk for customers who need guaranteed delivery of high-density FPGAs. Dave Greenfield Altera Marketing > Peter Alfke wrote: > > > It is so easy to ridicule this puerile bragging contest and its > > Freudian fix on one specific aspect, while ignoring far more important > > features. Unfortunately, some poor innocent person might actually get > > fooled by it. Too bad! >Article: 84112
fpgabuilder wrote:
> Hi Folks,
>
> I am using Altera's LPM FIFOs. These are deep fifos and was wondering
> if there are any techniques that people follow to initialize the rd/wr
> pointers in the fifo so that I can quickly simulate the overflow
> condition. I use modelsim pe.
You could infer the same FIFO from code.
Simulating the code instead of using Altera's netlist
will speed up your simulation.
Or you could test overflow on a smaller FIFO.
-- Mike Treseler
Article: 84113Peter, Austin, someone Xilinxy, can anyone possibly put this in hands where it'll do some good? The cost of updating online PDF documentation is really pretty trivial. -- To whom it may concern: Page 53 of the Spartan-3 Starter Kit User's Guide claims that: The A1 expansion connector shares connections with the 256Kx16 SRAM devices, specifically the SRAM address lines, and the OE# and WE# control signals. Similarly, the JTAG chain is available on pins 36 through 40. Pin 20 is the FPGA DOUT/BUSY configuration signal and toggles during the FPGA configuration process. This, while accurate, is not the entire case. The A1 connector also shares connection with 8 of the SRAM data lines, though this is not indicated in any way by Table 13-2. This information, in fact, can only be deduced by close examination of the schematics, or alternatively when PACE informs you that the pins to your SRAM and the pins making hard connections to the board you've already spun are on the same pin of the FPGA. Had this information been made clear in the user's guide, rather than left out of the explicit statement of connection, I would now be saved a good deal of fairly extensive blue-wiring trying to save this project. Please update the User's Guide as soon as possible regarding this point, in the interests of saving a future customer my current aggravation. Regards, Rob GaddiArticle: 84114
At $49 it starts looking good for small throw-away prototypes. It's hard to tell, but it looks like the PCB has two unpopulated spots. SRAM? Benjamin Menküc wrote: > I would prefer a board with external RAM (DDR or SRAM). For the very > first step this board might be enough, but not for the second step :) Definitely, with short traces and lots of capacity. While we're doing the wishlist: Altera, *please* include support the the EP2S35 Stratix II in the WebPack. TommyArticle: 84115
Hi I am wondering again and again if xilinx does any testing of the software they release both ISE 7.1 and EDK 7.1 have service paks already so I assume some bug tesing and FIXIN has been done? well I am having some trouble with microblaze system that shoud connect to 4 64 bit SDRAM banks using 4 instances of opb2plb bridge. so, problem, oh well lets take a xilinx own KNOWN WORKING DESIGN and lets see what is done there, so I load the ML401 reference design in EDK 7.1, then I open add edit cores, and hit 'generate address map' waiting waiting ... and XPS is gone!!! yes it just silently closes itself. I am having some warnings when doing address generate so I wanted to compare those warning with the warnings that come with xilinx own design, but I can as the xilinx own desing makes xilinx own software to terminate itself. its not so impossible to test for software bugs, why xilinx isnt doing that? testing with its own design (like the ML401 ref design) would be good test for beta test of new releases. but it has not been done. anttiArticle: 84116
Austin Lesea wrote: <snip> >> There are ways around this, but life would be easier if Xilinx >> actually bothered to meet the spec in the first place. > > Already explained why we can't do that: 35 IO standards in one pin has > to make some compromises. Perhaps it is time to make some pins less "jack of all trades, master of none", and provide some with more focus ? -jgArticle: 84117
I'm upgrading a design, and I'm in the early phases of choosing a vendor.
I'm trying to compare parts based on experience I've had in the past, so I'm
focusing on block RAM clock to out delay as a critical performance number:
Altera M4K vs. Xilinx Block RAM clock to out delay, non-registered outputs:
Stratix-II -3 2.46 ns
Stratix-II -4 2.828 ns
Stratix-II -5 3.393 ns
Xilinx-V4 -11 1.83 ns
Xilinx-V4 -10 2.10 ns
Xilinx-V2 -4 2.65 ns (current part)
V4 appears to be 1.62 times faster for the slowest speed grade parts (which
I'm probably most interested in, though I should really compare equal priced
parts), and slower even than the original V2 design. Am I missing
something? Several posts here suggest that Stratix-II interconnect is
faster- is there any datasheet evidence to back this up? Lets say the RAM
output is at least feeding a 2:1 MUX before being registered, and porbably
has to travel ~1/3 the width of the chip.
Also, help me fill in my chart:
LUT delay:
Xilinx-V2 -4 439ps
Xilinx-V4 -10 200ps
Xilinx-V4 -11 170ps
Stratix-II ? (can't find any data)
Carry delay:
Xilinx-V2 -4 106ps
Xilinx-V4 -10 90 ps
Xilinx-V4 -11 80 ps
Stratix-II ? (can't find any data)
Routing delay:
I can do this with fpga_editor in Xilinx. How to do it for Stratix-II ?
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 84118Jim, It is something we agonize over everytime we look at a new family. Should we add IO standard specific IOB's? How many? How are they to be organized? What should the IO/CLB ratio be? Or, should we continue with the present plans (if it ain't broke, don't fix it)? What business did we lose because we could not meet a customer's requirement? How do we know we even lost any business at all? We did add MGTs (and PPC's, EMAC's, DSP48's, ECC_BRAM's, FIFO_BRAM's, etc), so it isn't like we are not looking at adding new things, or mixing things up (the patented ASMBL architecture for example). 360 MHz, 720 Mbs DDR LVDS is now over five years old as something that either X or A has provided with their devices. One can argue the fine points, but as a gross capability, it has been there for quite awhile. Austin Jim Granville wrote: > Austin Lesea wrote: > > <snip> > >>> There are ways around this, but life would be easier if Xilinx >>> actually bothered to meet the spec in the first place. >> >> >> Already explained why we can't do that: 35 IO standards in one pin >> has to make some compromises. > > > Perhaps it is time to make some pins less "jack of all trades, master > of none", and provide some with more focus ? > > -jg >Article: 84119
>One way to avoid being fooled is >to write portable code and run >a trial synthesis/route/STA >for all the contesting devices. Does anybody have any data on how much performance (space or time) you can gain by hacking some nice pretty portable code to take advantage of device specific features? How much time does it take to "try it" if that includes a round of manual placement? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 84120
Hi Peter, > It is so easy to ridicule this puerile bragging contest and its > Freudian fix on one specific aspect, while ignoring far more important > features. Unfortunately, some poor innocent person might actually get > fooled by it. Too bad! Yep. In The Netherlands we call it a far-peeing contest. However, I have been subjected to a customer who made a vendor decision for a low-cost device based on the fact that this vendor at the time also happened to have the largest high-end FPGA in the market. I kid you not. Took me two days to regain my confidence in humanity. If this happens in a postage-size country like The Netherlands, it must happen in other places - we're not _that_ much more unreasonable than other countries... > For a more entertaining story, click on > http://www.fpgajournal.com/articles_2005/20050510_worldsbest.htm Wonderful! Thanks for the link! BenArticle: 84121
I did a correlator for Stratix with 8 parallel MACs where the 2nd try was better than the 1st by 3x fewer logic cells and 50% better fmax, just by moving the accumulators and moving (not adding) pipelining. That's probably pretty extreme, but without taking a close look at the Stratix DSP block I don't think I would have realized it. Depending on how you code barrel shifters on Stratix II you can get big savings by using the ALM to its maximum capability. I'd love to find lots of other functions that map really well into the ALM. -- Pete > Does anybody have any data on how much performance (space or time) you > can gain by hacking some nice pretty portable code to take advantage > of device specific features? > > How much time does it take to "try it" if that includes a round > of manual placement? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 84122
> 2) Look at this newsgroup. Peter and Austin are always there in > the front line, standing up for their company, taking the heat > and bs from an open public forum. Plus Xilinx makes it a point > to have additional experts peeking in the group and helping > out where needed. Any problem reported is discussed in the open > and solved. There is no under the rug filing or shutting up the > customers. I can download an errata or post to the newsgroup > and get open solutions. I can't say that I see a lot of that > from Altera. Yes Paul seems to be out there as well, taking on > a fight here and there. But I find there is a lack of discussion > level as with Xilinx. I know if I run in to a problem with Xilinx > devices, I can always turn to this news group and get help. Rudi, I don't think this point is quite fair. Besides Paul there are myself (Nios/embedded questions here are what I answer), Vaughn, and others. On the embedded side a lot of people have moved over to asking questions on a new webaite (www.niosforum.com) where there area Altera people from the engineering/apps/marketing teams who respond quite regularly. I won't comment on the original FPGA Journal article, other than to say that I enjoyed it :) On the other hand, one should realize that X has been playing the same marketing games for years now without a peep from the press... Jesse Kempa AlteraArticle: 84123
Hi Joseph, I stopped reading data sheets since they're way too big and the information is never organized the way I need to have it. So I tend to simply write little test cases and let the tools tell me what I need to know. I would personally just compile the design with your new constraints in both ISE and Quartus II (v5 has just been released) and see who comes out best. > Altera M4K vs. Xilinx Block RAM clock to out delay, non-registered > outputs: > > Stratix-II -3 2.46 ns > Stratix-II -4 2.828 ns > Stratix-II -5 3.393 ns > > Xilinx-V4 -11 1.83 ns > Xilinx-V4 -10 2.10 ns > > Xilinx-V2 -4 2.65 ns (current part) I suggest you re-check Stratix-II timing with Quartus II 5.0 - Altera has been doing some re-characterization which seemingly hasn't made it to the handbook yet. In an M4K I am using in a Stratix II I'm getting 1.85ns for a -3 part and 2.4ns for a -5 part. > LUT Delay: > Stratix-II ? (can't find any data) Well, it kind of varies between (off the cuff) 83ps and 400ps depending on the input that changes and the mode the ALM is in. Easy to check in Quartus with, for example, an 8-input AND or so. I'm getting cell delays between 0.047 and 0.404ns depending on the mode and the input of the ALM (see below on how to do this). > Carry delay: > > Xilinx-V2 -4 106ps > Xilinx-V4 -10 90 ps > Xilinx-V4 -11 80 ps > Stratix-II ? (can't find any data) > > Routing delay: > > I can do this with fpga_editor in Xilinx. How to do it for Stratix-II ? Open the timing analyzer. Right-click a path and select "List Paths" from the menu. When expanding the messgaes in the status window you should get detailed info on both cell and routing delay of the path. Best regards, BenArticle: 84124
Hi Joseph,
Remember that in Q II 5.0 the M4k performance has increased from 400 to
550 MHz. It looks like you're using the out-of-date numbers for tCO.
The new ones should be ~ 1.88 ns (I'm guessing).
There's a few ways to find the routing delays in Q II. The most
detailed way is to open the Timing Floorplanner (Assignments/Timing
Closure Floorplan), right-click a used logic cell, and choose
Locate>Chip Editor.
>From here you can multi-select resources, choose View/Show Delays,
right-click, and choose "Generate Connections Between Nodes". You can
show the actual routes used with View/Highlight Routing.
The easier way is to stay in the Timing Floorplanner, Ctrl-click the
stuff you want to find delays for, make sure View/Routing/"Show Routing
Delays" is selected, and choose View/Routing/"Show Paths Between
Nodes".
Interesting ... the Sratix II handbook doesn't have LUT timing params.
I was sure they were there for Stratix. Well it shouldn't be too
difficult with Chip Editor ... maybe someone gets an answer before I do
...
-- Pete
Joseph H Allen wrote:
> I'm upgrading a design, and I'm in the early phases of choosing a
vendor.
> I'm trying to compare parts based on experience I've had in the past,
so I'm
> focusing on block RAM clock to out delay as a critical performance
number:
>
> Altera M4K vs. Xilinx Block RAM clock to out delay, non-registered
outputs:
>
> Stratix-II -3 2.46 ns
> Stratix-II -4 2.828 ns
> Stratix-II -5 3.393 ns
>
> Xilinx-V4 -11 1.83 ns
> Xilinx-V4 -10 2.10 ns
>
> Xilinx-V2 -4 2.65 ns (current part)
>
> V4 appears to be 1.62 times faster for the slowest speed grade parts
(which
> I'm probably most interested in, though I should really compare equal
priced
> parts), and slower even than the original V2 design. Am I missing
> something? Several posts here suggest that Stratix-II interconnect
is
> faster- is there any datasheet evidence to back this up? Lets say
the RAM
> output is at least feeding a 2:1 MUX before being registered, and
porbably
> has to travel ~1/3 the width of the chip.
>
> Also, help me fill in my chart:
>
> LUT delay:
>
> Xilinx-V2 -4 439ps
> Xilinx-V4 -10 200ps
> Xilinx-V4 -11 170ps
> Stratix-II ? (can't find any data)
>
> Carry delay:
>
> Xilinx-V2 -4 106ps
> Xilinx-V4 -10 90 ps
> Xilinx-V4 -11 80 ps
> Stratix-II ? (can't find any data)
>
> Routing delay:
>
> I can do this with fpga_editor in Xilinx. How to do it for
Stratix-II ?
>
> --
> /* jhallen@world.std.com (192.74.137.5) */ /* Joseph
H. Allen */
> int
a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
>
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n","
#"[!a[q-1]]);}
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